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[people/ms/u-boot.git] / board / omap2420h4 / omap2420h4.c
1 /*
2 * (C) Copyright 2004
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24 #include <common.h>
25 #include <asm/arch/omap2420.h>
26 #include <asm/io.h>
27 #include <asm/arch/bits.h>
28 #include <asm/arch/mux.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/sys_info.h>
31 #include <asm/arch/mem.h>
32 #include <i2c.h>
33 #include <asm/mach-types.h>
34 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
35 #include <linux/mtd/nand.h>
36 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
37 #endif
38
39
40 static void wait_for_command_complete(unsigned int wd_base);
41
42 /*******************************************************
43 * Routine: delay
44 * Description: spinning delay to use before udelay works
45 ******************************************************/
46 static inline void delay (unsigned long loops)
47 {
48 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
49 "bne 1b":"=r" (loops):"0" (loops));
50 }
51
52 /*****************************************
53 * Routine: board_init
54 * Description: Early hardware init.
55 *****************************************/
56 int board_init (void)
57 {
58 DECLARE_GLOBAL_DATA_PTR;
59
60 gpmc_init(); /* in SRAM or SDRM, finish GPMC */
61
62 gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */
63 gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */
64
65 return 0;
66 }
67
68 /**********************************************************
69 * Routine: s_init
70 * Description: Does early system init of muxing and clocks.
71 * - Called path is with sram stack.
72 **********************************************************/
73 void s_init(void)
74 {
75 int in_sdram = running_in_sdram();
76
77 watchdog_init();
78 set_muxconf_regs();
79 delay(100);
80
81 if(!in_sdram)
82 prcm_init();
83
84 peripheral_enable();
85 icache_enable();
86 if (!in_sdram)
87 sdrc_init();
88 }
89
90 /*******************************************************
91 * Routine: misc_init_r
92 * Description: Init ethernet (done here so udelay works)
93 ********************************************************/
94 int misc_init_r (void)
95 {
96 ether_init(); /* better done here so timers are init'ed */
97 return(0);
98 }
99
100 /****************************************
101 * Routine: watchdog_init
102 * Description: Shut down watch dogs
103 *****************************************/
104 void watchdog_init(void)
105 {
106 int mode;
107 #define GP (BIT8|BIT9)
108
109 /* There are 4 watch dogs. 1 secure, and 3 general purpose.
110 * I would expect that the ROM takes care of the secure one,
111 * but we will try also. Of the 3 GP ones, 1 can reset us
112 * directly, the other 2 only generate MPU interrupts.
113 */
114 mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
115 if (mode == GP) {
116 __raw_writel(WD_UNLOCK1 ,WD1_BASE+WSPR);
117 wait_for_command_complete(WD1_BASE);
118 __raw_writel(WD_UNLOCK2 ,WD1_BASE+WSPR);
119 }
120 __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
121 wait_for_command_complete(WD2_BASE);
122 __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
123
124 #if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
125 __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
126 wait_for_command_complete(WD3_BASE);
127 __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
128
129 __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
130 wait_for_command_complete(WD4_BASE);
131 __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
132 #endif
133 }
134
135 /******************************************************
136 * Routine: wait_for_command_complete
137 * Description: Wait for posting to finish on watchdog
138 ******************************************************/
139 static void wait_for_command_complete(unsigned int wd_base)
140 {
141 int pending = 1;
142 do {
143 pending = __raw_readl(wd_base+WWPS);
144 } while (pending);
145 }
146
147 /*******************************************************************
148 * Routine:ether_init
149 * Description: take the Ethernet controller out of reset and wait
150 * for the EEPROM load to complete.
151 ******************************************************************/
152 void ether_init (void)
153 {
154 #ifdef CONFIG_DRIVER_LAN91C96
155 int cnt = 20;
156
157 __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
158
159 __raw_writew(0x0, LAN_RESET_REGISTER);
160 do {
161 __raw_writew(0x1, LAN_RESET_REGISTER);
162 udelay (100);
163 if (cnt == 0)
164 goto h4reset_err_out;
165 --cnt;
166 } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
167
168 cnt = 20;
169
170 do {
171 __raw_writew(0x0, LAN_RESET_REGISTER);
172 udelay (100);
173 if (cnt == 0)
174 goto h4reset_err_out;
175 --cnt;
176 } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
177 udelay (1000);
178
179 *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
180 udelay (1000);
181
182 h4reset_err_out:
183 return;
184 #endif
185 }
186
187 /**********************************************
188 * Routine: dram_init
189 * Description: sets uboots idea of sdram size
190 **********************************************/
191 int dram_init (void)
192 {
193 DECLARE_GLOBAL_DATA_PTR;
194 unsigned int size0=0,size1=0;
195 u32 mtype, btype;
196 u8 chg_on = 0x5; /* enable charge of back up battery */
197 u8 vmode_on = 0x8C;
198 #define NOT_EARLY 0
199
200 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
201
202 btype = get_board_type();
203 mtype = get_mem_type();
204
205 display_board_info(btype);
206 if (btype == BOARD_H4_MENELAUS){
207 update_mux(btype,mtype); /* combo part on menelaus */
208 i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
209 i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
210 }
211
212 if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
213 do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
214 size0 = size1 = SZ_32M;
215 } else if (mtype == SDR_DISCRETE)
216 size0 = SZ_128M;
217 else
218 size0 = SZ_64M;
219
220 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
221 gd->bd->bi_dram[0].size = size0;
222 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
223 gd->bd->bi_dram[1].size = size1;
224
225 return 0;
226 }
227
228 /**********************************************************
229 * Routine: set_muxconf_regs
230 * Description: Setting up the configuration Mux registers
231 * specific to the hardware
232 *********************************************************/
233 void set_muxconf_regs (void)
234 {
235 muxSetupSDRC();
236 muxSetupGPMC();
237 muxSetupUsb0();
238 muxSetupUart3();
239 muxSetupI2C1();
240 muxSetupUART1();
241 muxSetupLCD();
242 muxSetupCamera();
243 muxSetupMMCSD();
244 muxSetupTouchScreen();
245 muxSetupHDQ();
246 }
247
248 /*****************************************************************
249 * Routine: peripheral_enable
250 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
251 ******************************************************************/
252 void peripheral_enable(void)
253 {
254 unsigned int v, if_clks=0, func_clks=0;
255
256 /* Enable GP2 timer.*/
257 if_clks |= BIT4;
258 func_clks |= BIT4;
259 v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
260 __raw_writel(v, CM_CLKSEL2_CORE);
261 __raw_writel(0x1, CM_CLKSEL_WKUP);
262
263 #ifdef CFG_NS16550
264 /* Enable UART1 clock */
265 func_clks |= BIT21;
266 if_clks |= BIT21;
267 #endif
268 v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
269 __raw_writel(v,CM_ICLKEN1_CORE );
270 v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
271 __raw_writel(v, CM_FCLKEN1_CORE);
272 delay(1000);
273
274 #ifndef KERNEL_UPDATED
275 {
276 #define V1 0xffffffff
277 #define V2 0x00000007
278
279 __raw_writel(V1, CM_FCLKEN1_CORE);
280 __raw_writel(V2, CM_FCLKEN2_CORE);
281 __raw_writel(V1, CM_ICLKEN1_CORE);
282 __raw_writel(V1, CM_ICLKEN2_CORE);
283 }
284 #endif
285 }
286
287 /****************************************
288 * Routine: muxSetupUsb0 (ostboot)
289 * Description: Setup usb muxing
290 *****************************************/
291 void muxSetupUsb0(void)
292 {
293 volatile uint8 *MuxConfigReg;
294 volatile uint32 *otgCtrlReg;
295
296 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
297 *MuxConfigReg &= (uint8)(~0x1F);
298
299 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
300 *MuxConfigReg &= (uint8)(~0x1F);
301
302 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
303 *MuxConfigReg &= (uint8)(~0x1F);
304
305 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
306 *MuxConfigReg &= (uint8)(~0x1F);
307
308 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
309 *MuxConfigReg &= (uint8)(~0x1F);
310
311 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
312 *MuxConfigReg &= (uint8)(~0x1F);
313
314 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
315 *MuxConfigReg &= (uint8)(~0x1F);
316
317 /* setup for USB VBus detection */
318 otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
319 *otgCtrlReg |= 0x00040000; /* bit 18 */
320 }
321
322 /****************************************
323 * Routine: muxSetupUart3 (ostboot)
324 * Description: Setup uart3 muxing
325 *****************************************/
326 void muxSetupUart3(void)
327 {
328 volatile uint8 *MuxConfigReg;
329
330 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
331 *MuxConfigReg &= (uint8)(~0x1F);
332
333 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
334 *MuxConfigReg &= (uint8)(~0x1F);
335 }
336
337 /****************************************
338 * Routine: muxSetupI2C1 (ostboot)
339 * Description: Setup i2c muxing
340 *****************************************/
341 void muxSetupI2C1(void)
342 {
343 volatile unsigned char *MuxConfigReg;
344
345 /* I2C1 Clock pin configuration, PIN = M19 */
346 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
347 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
348
349 /* I2C1 Data pin configuration, PIN = L15 */
350 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
351 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
352
353 /* Pull-up required on data line */
354 /* external pull-up already present. */
355 /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
356 }
357
358 /****************************************
359 * Routine: muxSetupUART1 (ostboot)
360 * Description: Set up uart1 muxing
361 *****************************************/
362 void muxSetupUART1(void)
363 {
364 volatile unsigned char *MuxConfigReg;
365
366 /* UART1_CTS pin configuration, PIN = D21 */
367 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
368 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
369
370 /* UART1_RTS pin configuration, PIN = H21 */
371 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
372 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
373
374 /* UART1_TX pin configuration, PIN = L20 */
375 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
376 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
377
378 /* UART1_RX pin configuration, PIN = T21 */
379 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
380 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
381 }
382
383 /****************************************
384 * Routine: muxSetupLCD (ostboot)
385 * Description: Setup lcd muxing
386 *****************************************/
387 void muxSetupLCD(void)
388 {
389 volatile unsigned char *MuxConfigReg;
390
391 /* LCD_D0 pin configuration, PIN = Y7 */
392 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
393 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
394
395 /* LCD_D1 pin configuration, PIN = P10 */
396 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
397 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
398
399 /* LCD_D2 pin configuration, PIN = V8 */
400 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
401 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
402
403 /* LCD_D3 pin configuration, PIN = Y8 */
404 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
405 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
406
407 /* LCD_D4 pin configuration, PIN = W8 */
408 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
409 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
410
411 /* LCD_D5 pin configuration, PIN = R10 */
412 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
413 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
414
415 /* LCD_D6 pin configuration, PIN = Y9 */
416 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
417 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
418
419 /* LCD_D7 pin configuration, PIN = V9 */
420 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
421 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
422
423 /* LCD_D8 pin configuration, PIN = W9 */
424 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
425 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
426
427 /* LCD_D9 pin configuration, PIN = P11 */
428 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
429 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
430
431 /* LCD_D10 pin configuration, PIN = V10 */
432 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
433 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
434
435 /* LCD_D11 pin configuration, PIN = Y10 */
436 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
437 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
438
439 /* LCD_D12 pin configuration, PIN = W10 */
440 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
441 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
442
443 /* LCD_D13 pin configuration, PIN = R11 */
444 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
445 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
446
447 /* LCD_D14 pin configuration, PIN = V11 */
448 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
449 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
450
451 /* LCD_D15 pin configuration, PIN = W11 */
452 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
453 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
454
455 /* LCD_D16 pin configuration, PIN = P12 */
456 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
457 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
458
459 /* LCD_D17 pin configuration, PIN = R12 */
460 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
461 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
462
463 /* LCD_PCLK pin configuration, PIN = W6 */
464 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
465 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
466
467 /* LCD_VSYNC pin configuration, PIN = V7 */
468 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
469 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
470
471 /* LCD_HSYNC pin configuration, PIN = Y6 */
472 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
473 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
474
475 /* LCD_ACBIAS pin configuration, PIN = W7 */
476 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
477 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
478 }
479
480 /****************************************
481 * Routine: muxSetupCamera (ostboot)
482 * Description: Setup camera muxing
483 *****************************************/
484 void muxSetupCamera(void)
485 {
486 volatile unsigned char *MuxConfigReg;
487
488 /* CAMERA_RSTZ pin configuration, PIN = Y16 */
489 /* CAM_RST is connected through the I2C IO expander.*/
490 /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
491 /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */
492
493 /* CAMERA_XCLK pin configuration, PIN = U3 */
494 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
495 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
496
497 /* CAMERA_LCLK pin configuration, PIN = V5 */
498 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
499 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
500
501 /* CAMERA_VSYNC pin configuration, PIN = U2 */
502 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
503 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
504
505 /* CAMERA_HSYNC pin configuration, PIN = T3 */
506 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
507 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
508
509 /* CAMERA_DAT0 pin configuration, PIN = T4 */
510 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
511 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
512
513 /* CAMERA_DAT1 pin configuration, PIN = V2 */
514 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
515 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
516
517 /* CAMERA_DAT2 pin configuration, PIN = V3 */
518 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
519 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
520
521 /* CAMERA_DAT3 pin configuration, PIN = U4 */
522 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
523 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
524
525 /* CAMERA_DAT4 pin configuration, PIN = W2 */
526 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
527 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
528
529 /* CAMERA_DAT5 pin configuration, PIN = V4 */
530 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
531 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
532
533 /* CAMERA_DAT6 pin configuration, PIN = W3 */
534 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
535 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
536
537 /* CAMERA_DAT7 pin configuration, PIN = Y2 */
538 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
539 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
540
541 /* CAMERA_DAT8 pin configuration, PIN = Y4 */
542 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
543 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
544
545 /* CAMERA_DAT9 pin configuration, PIN = V6 */
546 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
547 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
548 }
549
550 /****************************************
551 * Routine: muxSetupMMCSD (ostboot)
552 * Description: set up MMC muxing
553 *****************************************/
554 void muxSetupMMCSD(void)
555 {
556 volatile unsigned char *MuxConfigReg;
557
558 /* SDMMC_CLKI pin configuration, PIN = H15 */
559 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
560 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
561
562 /* SDMMC_CLKO pin configuration, PIN = G19 */
563 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
564 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
565
566 /* SDMMC_CMD pin configuration, PIN = H18 */
567 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
568 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
569 /* External pull-ups are present. */
570 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
571
572 /* SDMMC_DAT0 pin configuration, PIN = F20 */
573 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
574 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
575 /* External pull-ups are present. */
576 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
577
578 /* SDMMC_DAT1 pin configuration, PIN = H14 */
579 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
580 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
581 /* External pull-ups are present. */
582 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
583
584 /* SDMMC_DAT2 pin configuration, PIN = E19 */
585 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
586 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
587 /* External pull-ups are present. */
588 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
589
590 /* SDMMC_DAT3 pin configuration, PIN = D19 */
591 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
592 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
593 /* External pull-ups are present. */
594 /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
595
596 /* SDMMC_DDIR0 pin configuration, PIN = F19 */
597 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
598 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
599
600 /* SDMMC_DDIR1 pin configuration, PIN = E20 */
601 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
602 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
603
604 /* SDMMC_DDIR2 pin configuration, PIN = F18 */
605 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
606 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
607
608 /* SDMMC_DDIR3 pin configuration, PIN = E18 */
609 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
610 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
611
612 /* SDMMC_CDIR pin configuration, PIN = G18 */
613 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
614 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
615
616 /* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/
617 /* MMC_CD for 2422IP=K1 */
618 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
619 *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
620
621 /* MMC_WP pin configuration, PIN = B4 */
622 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
623 *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
624 }
625
626 /******************************************
627 * Routine: muxSetupTouchScreen (ostboot)
628 * Description: Set up touch screen muxing
629 *******************************************/
630 void muxSetupTouchScreen(void)
631 {
632 volatile unsigned char *MuxConfigReg;
633
634 /* SPI1_CLK pin configuration, PIN = U18 */
635 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
636 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
637
638 /* SPI1_MOSI pin configuration, PIN = V20 */
639 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
640 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
641
642 /* SPI1_MISO pin configuration, PIN = T18 */
643 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
644 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
645
646 /* SPI1_nCS0 pin configuration, PIN = U19 */
647 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
648 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
649
650 /* PEN_IRQ pin configuration, PIN = P20 */
651 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
652 *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
653 }
654
655 /****************************************
656 * Routine: muxSetupHDQ (ostboot)
657 * Description: setup 1wire mux
658 *****************************************/
659 void muxSetupHDQ(void)
660 {
661 volatile unsigned char *MuxConfigReg;
662
663 /* HDQ_SIO pin configuration, PIN = N18 */
664 MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
665 *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
666 }
667
668 /***************************************************************
669 * Routine: muxSetupGPMC (ostboot)
670 * Description: Configures balls which cam up in protected mode
671 ***************************************************************/
672 void muxSetupGPMC(void)
673 {
674 volatile uint8 *MuxConfigReg;
675 volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
676
677 /* gpmc_io_dir */
678 *MCR = 0x19000000;
679
680 /* NOR FLASH CS0 */
681 /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */
682 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
683 *MuxConfigReg = 0x00 ;
684
685 /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3 Pull/up - N/A */
686 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
687 *MuxConfigReg = 0x01 ;
688
689 /* MPDB(Multi Port Debug Port) CS1 */
690 /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */
691 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
692 *MuxConfigReg = 0x00 ;
693
694 /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
695 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
696 *MuxConfigReg = 0x00 ;
697
698
699 }
700
701 /****************************************************************
702 * Routine: muxSetupSDRC (ostboot)
703 * Description: Configures balls which come up in protected mode
704 ****************************************************************/
705 void muxSetupSDRC(void)
706 {
707 volatile uint8 *MuxConfigReg;
708
709 /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1 Pull/up - N/A */
710 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
711 *MuxConfigReg = 0x00 ;
712
713 /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2 Pull/up - N/A */
714 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
715 *MuxConfigReg = 0x00 ;
716
717 /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3 Pull/up - N/A */
718 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
719 *MuxConfigReg = 0x00;
720
721 if (get_cpu_type() == CPU_2422) {
722 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
723 *MuxConfigReg = 0x1b;
724 }
725 }
726
727 /*****************************************************************************
728 * Routine: update_mux()
729 * Description: Update balls which are different beween boards. All should be
730 * updated to match functionaly. However, I'm only updating ones
731 * which I'll be using for now. When power comes into play they
732 * all need updating.
733 *****************************************************************************/
734 void update_mux(u32 btype,u32 mtype)
735 {
736 u32 cpu, base = OMAP2420_CTRL_BASE;
737 cpu = get_cpu_type();
738
739 if (btype == BOARD_H4_MENELAUS) {
740 if (cpu == CPU_2420) {
741 /* PIN = B3, GPIO.0->KBR5, mode 3, (pun?),-DO-*/
742 __raw_writeb(0x3, base+0x30);
743 /* PIN = B13, GPIO.38->KBC6, mode 3, (pun?)-DO-*/
744 __raw_writeb(0x3, base+0xa3);
745 /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/
746 /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/
747 /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/
748 /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/
749 /* PIN = M1 (HSUSBOTG) */
750 /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/
751 __raw_writeb(0x3, base+0x9d);
752 /* PIN = U32, (WLAN_CLKREQ) */
753 /* PIN = Y11, WLAN */
754 /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */
755 __raw_writeb(0x3, base+0xe7);
756 /* PIN = AA8, mDOC */
757 /* PIN = AA10, BT */
758 /* PIN = AA13, WLAN */
759 /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */
760 __raw_writeb(0x3, base+0x10e);
761 /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */
762 __raw_writeb(0x3, base+0x110);
763 /* PIN = J15 HHUSB */
764 /* PIN = H19 HSUSB */
765 /* PIN = W13, P13, R13, W16 ... */
766 /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */
767 __raw_writeb(0x3, base+0xde);
768 /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
769 __raw_writeb(0x0, base+0x12c);
770 /* PIN = AA17->sys_clkreq mode 0 -DO- */
771 __raw_writeb(0x0, base+0x136);
772 } else if (cpu == CPU_2422) {
773 /* PIN = B3, GPIO.0->nc, mode 3, set above (pun?)*/
774 /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/
775 /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/
776 /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/
777 /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/
778 __raw_writeb(0x0, base+0x92);
779 /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/
780 /* PIN = M1 (HSUSBOTG) */
781 /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/
782 __raw_writeb(0x3, base+0x10c);
783 /* PIN = U32, (WLAN_CLKREQ) */
784 /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */
785 __raw_writeb(0x3, base+0x30);
786 /* PIN = AA8, mDOC */
787 /* PIN = AA10, BT */
788 /* PIN = AA12, WLAN */
789 /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */
790 __raw_writeb(0x3, base+0x10e);
791 /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */
792 __raw_writeb(0x3, base+0x110);
793 /* PIN = J15 HHUSB */
794 /* PIN = H19 HSUSB */
795 /* PIN = W13, P13, R13, W16 ... */
796 /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */
797 __raw_writeb(0x3, base+0xde);
798 /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
799 __raw_writeb(0x0, base+0x12c);
800 /* PIN = AA17->sys_clkreq mode 0 -DO- */
801 __raw_writeb(0x0, base+0x136);
802 }
803
804 } else if (btype == BOARD_H4_SDP) {
805 if (cpu == CPU_2420) {
806 /* PIN = B3, GPIO.0->nc mode 3, set above (pun?)*/
807 /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/
808 /* Pin = Y11 VLNQ */
809 /* Pin = AA4 VLNQ */
810 /* Pin = AA6 VLNQ */
811 /* Pin = AA8 VLNQ */
812 /* Pin = AA10 VLNQ */
813 /* Pin = AA12 VLNQ */
814 /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */
815 __raw_writeb(0x3, base+0x10e);
816 /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */
817 __raw_writeb(0x3, base+0x110);
818 /* PIN = J15 MDOC_nDMAREQ */
819 /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */
820 __raw_writeb(0x3, base+0x114);
821 /* PIN = W13, V12, P13, R13, W19, W16 ... */
822 /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */
823 } else if (cpu == CPU_2422) {
824 /* PIN = B3, GPIO.0->MMC_CD, mode 3, set above */
825 /* PIN = B13, GPIO.38->wlan_int, mode 3, (pun?)*/
826 /* Pin = Y11 VLNQ */
827 /* Pin = AA4 VLNQ */
828 /* Pin = AA6 VLNQ */
829 /* Pin = AA8 VLNQ */
830 /* Pin = AA10 VLNQ */
831 /* Pin = AA12 VLNQ */
832 /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */
833 __raw_writeb(0x3, base+0x10e);
834 /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */
835 __raw_writeb(0x3, base+0x110);
836 /* PIN = J15 MDOC_nDMAREQ */
837 /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */
838 __raw_writeb(0x3, base+0x114);
839 /* PIN = W13, V12, P13, R13, W19, W16 ... */
840 /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */
841 }
842 }
843 }
844
845 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
846 void nand_init(void)
847 {
848 extern flash_info_t flash_info[];
849
850 nand_probe(CFG_NAND_ADDR);
851 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
852 print_size(nand_dev_desc[0].totlen, "\n");
853 }
854
855 #ifdef CFG_JFFS2_MEM_NAND
856 flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
857 flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */
858 flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
859 flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
860 #endif
861 }
862 #endif
863
864
865
"Das U-Boot" Source Tree