board/overo/overo.h

   1 /*
   2  * (C) Copyright 2008
   3  * Steve Sakoman <steve@sakoman.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #ifndef _OVERO_H_
   8 #define _OVERO_H_
   9
  10 const omap3_sysinfo sysinfo = {
  11         DDR_STACKED,
  12         "Gumstix Overo board",
  13 #if defined(CONFIG_ENV_IS_IN_ONENAND)
  14         "OneNAND",
  15 #else
  16         "NAND",
  17 #endif
  18 };
  19
  20 int get_board_revision(void);
  21
  22 /* overo revisions */
  23 #define REVISION_0      0x0
  24 #define REVISION_1      0x1
  25 #define REVISION_2      0x2
  26 #define REVISION_3      0x3
  27 #define REVISION_4      0x4
  28
  29 /*
  30  * IEN  - Input Enable
  31  * IDIS - Input Disable
  32  * PTD  - Pull type Down
  33  * PTU  - Pull type Up
  34  * DIS  - Pull type selection is inactive
  35  * EN   - Pull type selection is active
  36  * M0   - Mode 0
  37  * The commented string gives the final mux configuration for that pin
  38  */
  39 #define MUX_GUMSTIX() \
  40   /*GPMC*/\
  41         MUX_VAL(CP(GPMC_NCS1),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
  42         MUX_VAL(CP(GPMC_NCS4),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
  43         MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
  44         MUX_VAL(CP(GPMC_NCS6),          (IEN  | PTD | DIS | M0)) /*GPMC_nCS6*/\
  45         MUX_VAL(CP(GPMC_WAIT1),         (IEN  | PTU | EN  | M4)) /*GPIO_63*/\
  46                                                                  /* - CAM_IRQ*/\
  47         MUX_VAL(CP(GPMC_WAIT2),         (IEN  | PTU | EN  | M4)) /*GPIO_64*/\
  48                                                                  /* - SMSC911X_NRES*/\
  49         MUX_VAL(CP(GPMC_WAIT3),         (IEN  | PTU | DIS | M4)) /*GPIO_65*/\
  50  /*DSS*/\
  51         MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
  52         MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
  53         MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
  54         MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
  55         MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
  56         MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
  57         MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
  58         MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
  59         MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
  60         MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
  61         MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
  62         MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
  63         MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
  64         MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
  65         MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
  66         MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
  67         MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
  68         MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
  69         MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
  70         MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
  71         MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
  72         MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
  73         MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
  74         MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
  75         MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
  76         MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
  77         MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
  78         MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
  79  /*CAMERA*/\
  80         MUX_VAL(CP(CAM_FLD),            (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
  81         MUX_VAL(CP(CAM_XCLKB),          (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
  82         MUX_VAL(CP(CAM_WEN),            (IEN  | PTD | DIS | M0)) /*CAM_WEN*/\
  83         MUX_VAL(CP(CAM_STROBE),         (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
  84         MUX_VAL(CP(CSI2_DX1),           (IEN  | PTD | EN  | M4)) /*GPIO_114*/\
  85                                                                  /* - PEN_DOWN*/\
  86  /*Bluetooth*/\
  87         MUX_VAL(CP(UART2_CTS),          (IEN  | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
  88         MUX_VAL(CP(UART2_RTS),          (IEN  | PTD | DIS | M4)) /*GPIO_145*/\
  89         MUX_VAL(CP(UART2_TX),           (IEN  | PTD | DIS | M4)) /*GPIO_146*/\
  90         MUX_VAL(CP(UART2_RX),           (IEN  | PTD | DIS | M4)) /*GPIO_147*/\
  91         MUX_VAL(CP(UART1_TX),           (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
  92         MUX_VAL(CP(UART1_CTS),          (IEN  | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
  93         MUX_VAL(CP(UART1_RX),           (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
  94  /*Serial Interface*/\
  95         MUX_VAL(CP(UART3_CTS_RCTX),     (IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
  96         MUX_VAL(CP(HDQ_SIO),            (IDIS | PTU | EN  | M4)) /*HDQ_SIO*/\
  97         MUX_VAL(CP(MCSPI1_CLK),         (IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
  98         MUX_VAL(CP(MCSPI1_SIMO),        (IEN  | PTD | DIS | M0)) /*McSPI1_SIMO */\
  99         MUX_VAL(CP(MCSPI1_SOMI),        (IEN  | PTD | DIS | M0)) /*McSPI1_SOMI */\
 100         MUX_VAL(CP(MCSPI1_CS0),         (IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
 101         MUX_VAL(CP(MCSPI1_CS1),         (IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
 102         MUX_VAL(CP(MCSPI1_CS2),         (IEN  | PTU | DIS | M4)) /*GPIO_176 */\
 103                                                                  /* - LAN_INTR */\
 104  /*Control and debug */\
 105         MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTU | EN  | M4)) /*GPIO_10*/\
 106         MUX_VAL(CP(SYS_CLKOUT2),        (IEN  | PTU | EN  | M4)) /*GPIO_186*/\
 107         MUX_VAL(CP(ETK_CLK_ES2),        (IEN  | PTU | EN  | M2)) /*MMC3_CLK*/\
 108         MUX_VAL(CP(ETK_CTL_ES2),        (IEN  | PTU | EN  | M2)) /*MMC3_CMD*/\
 109         MUX_VAL(CP(ETK_D0_ES2),         (IEN  | PTU | EN  | M4)) /*GPIO_14*/\
 110         MUX_VAL(CP(ETK_D3_ES2),         (IEN  | PTU | EN  | M2)) /*MMC3_DAT3*/\
 111         MUX_VAL(CP(ETK_D4_ES2),         (IEN  | PTU | EN  | M2)) /*MMC3_DAT0*/\
 112         MUX_VAL(CP(ETK_D5_ES2),         (IEN  | PTU | EN  | M2)) /*MMC3_DAT1*/\
 113         MUX_VAL(CP(ETK_D6_ES2),         (IEN  | PTU | EN  | M2)) /*MMC3_DAT2*/\
 114         MUX_VAL(CP(ETK_D7_ES2),         (IEN  | PTU | EN  | M4)) /*GPIO_21*/\
 115         MUX_VAL(CP(ETK_D8_ES2),         (IEN  | PTU | EN  | M4)) /*GPIO_22*/\
 116         MUX_VAL(CP(ETK_D9_ES2),         (IEN  | PTU | EN  | M4)) /*GPIO_23*/\
 117
 118 #define MUX_OVERO_SDIO2_DIRECT() \
 119         MUX_VAL(CP(MMC2_CLK),           (IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
 120         MUX_VAL(CP(MMC2_CMD),           (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
 121         MUX_VAL(CP(MMC2_DAT0),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
 122         MUX_VAL(CP(MMC2_DAT1),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
 123         MUX_VAL(CP(MMC2_DAT2),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
 124         MUX_VAL(CP(MMC2_DAT3),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
 125         MUX_VAL(CP(MMC2_DAT4),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT4*/\
 126         MUX_VAL(CP(MMC2_DAT5),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT5*/\
 127         MUX_VAL(CP(MMC2_DAT6),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT6*/\
 128         MUX_VAL(CP(MMC2_DAT7),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT7*/\
 129         MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTD | EN  | M4)) /*GPIO_126*/\
 130         MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M4)) /*GPIO_127*/\
 131         MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M4)) /*GPIO_128*/\
 132         MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M4)) /*GPIO_129*/
 133
 134 #define MUX_OVERO_SDIO2_TRANSCEIVER() \
 135         MUX_VAL(CP(MMC2_CLK),           (IEN  | PTU | EN  | M0)) /*MMC2_CLK*/\
 136         MUX_VAL(CP(MMC2_CMD),           (IEN  | PTU | EN  | M0)) /*MMC2_CMD*/\
 137         MUX_VAL(CP(MMC2_DAT0),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT0*/\
 138         MUX_VAL(CP(MMC2_DAT1),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT1*/\
 139         MUX_VAL(CP(MMC2_DAT2),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT2*/\
 140         MUX_VAL(CP(MMC2_DAT3),          (IEN  | PTU | EN  | M0)) /*MMC2_DAT3*/\
 141         MUX_VAL(CP(MMC2_DAT4),          (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT0*/\
 142         MUX_VAL(CP(MMC2_DAT5),          (IEN  | PTU | EN  | M1)) /*MMC2_DIR_DAT1*/\
 143         MUX_VAL(CP(MMC2_DAT6),          (IEN  | PTU | EN  | M1)) /*MMC2_DIR_CMD*/\
 144         MUX_VAL(CP(MMC2_DAT7),          (IEN  | PTU | EN  | M1)) /*MMC2_CLKIN*/\
 145         MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTU | EN  | M4)) /*GPIO_126*/\
 146         MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M4)) /*GPIO_127*/\
 147         MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M4)) /*GPIO_128*/\
 148         MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M4)) /*GPIO_129*/
 149
 150 #define MUX_USRP_E() \
 151         MUX_VAL(CP(MCSPI1_SOMI),        (IEN  | PTD | DIS | M4)) /*GPIO_173 */\
 152         MUX_VAL(CP(MCSPI1_CS1),         (IDIS | PTD | EN  | M4)) /*GPIO_175 */\
 153
 154 #define MUX_ALTO35() \
 155         MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTU | EN  | M4)) /*GPIO_10-BTN*/\
 156         MUX_VAL(CP(UART1_TX),           (IDIS | PTD | DIS | M4)) /*GPIO_148-RED LED*/\
 157         MUX_VAL(CP(UART1_CTS),          (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
 158         MUX_VAL(CP(UART1_RX),           (IDIS | PTD | DIS | M4)) /*GPIO_151-BLUE LED*/\
 159         MUX_VAL(CP(HDQ_SIO),            (IDIS | PTD | DIS | M4)) /*GPIO_170-GREEN LED*/\
 160         MUX_VAL(CP(MCSPI1_CS1),         (IDIS | PTD | EN  | M4)) /*GPIO_175*/\
 161
 162 #define MUX_ARBOR43C() \
 163         MUX_VAL(CP(CSI2_DX1),           (IDIS | PTD | DIS | M4)) /*GPIO_114-RED LED*/\
 164         MUX_VAL(CP(UART1_CTS),          (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
 165         MUX_VAL(CP(HDQ_SIO),            (IEN  | PTU | EN  | M4)) /*GPIO_170-BUTTON */\
 166         MUX_VAL(CP(SYS_CLKOUT2),        (IDIS | PTD | DIS | M4)) /*GPIO_186-BLUE LED*/\
 167         MUX_VAL(CP(JTAG_EMU1),          (IDIS | PTD | DIS | M4)) /*GPIO_31-CAP WAKE*/\
 168         MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTU | EN  | M4)) /*GPIO_10-CAP IRQ*/\
 169
 170 #endif