board/pcippc2/fpga_serial.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <common.h>
  26 #include <asm/io.h>
  27
  28 #include "fpga_serial.h"
  29 #include "hardware.h"
  30 #include "pcippc2.h"
  31
  32   /* 8 data, 1 stop, no parity
  33    */
  34 #define LCRVAL          0x03
  35   /* RTS/DTR
  36    */
  37 #define MCRVAL          0x03
  38   /* Clear & enable FIFOs
  39    */
  40 #define FCRVAL          0x07
  41
  42 static void fpga_serial_wait (void);
  43 static void fpga_serial_print (char c);
  44
  45 void fpga_serial_init (int baudrate)
  46 {
  47         int clock_divisor = 115200 / baudrate;
  48
  49         out8 (FPGA (INT, SERIAL_CONFIG), 0x24);
  50         iobarrier_rw ();
  51
  52         fpga_serial_wait ();
  53
  54         out8 (UART (IER), 0);
  55         out8 (UART (LCR), LCRVAL | 0x80);
  56         iobarrier_rw ();
  57         out8 (UART (DLL), clock_divisor & 0xff);
  58         out8 (UART (DLM), clock_divisor >> 8);
  59         iobarrier_rw ();
  60         out8 (UART (LCR), LCRVAL);
  61         iobarrier_rw ();
  62         out8 (UART (MCR), MCRVAL);
  63         out8 (UART (FCR), FCRVAL);
  64         iobarrier_rw ();
  65 }
  66
  67 void fpga_serial_putc (char c)
  68 {
  69         if (c) {
  70                 fpga_serial_print (c);
  71         }
  72 }
  73
  74 void fpga_serial_puts (const char *s)
  75 {
  76         while (*s) {
  77                 fpga_serial_print (*s++);
  78         }
  79 }
  80
  81 int fpga_serial_getc (void)
  82 {
  83         while ((in8 (UART (LSR)) & 0x01) == 0);
  84
  85         return in8 (UART (RBR));
  86 }
  87
  88 int fpga_serial_tstc (void)
  89 {
  90         return (in8 (UART (LSR)) & 0x01) != 0;
  91 }
  92
  93 void fpga_serial_setbrg (void)
  94 {
  95         DECLARE_GLOBAL_DATA_PTR;
  96
  97         int clock_divisor = 115200 / gd->baudrate;
  98
  99         fpga_serial_wait ();
 100
 101         out8 (UART (LCR), LCRVAL | 0x80);
 102         iobarrier_rw ();
 103         out8 (UART (DLL), clock_divisor & 0xff);
 104         out8 (UART (DLM), clock_divisor >> 8);
 105         iobarrier_rw ();
 106         out8 (UART (LCR), LCRVAL);
 107         iobarrier_rw ();
 108 }
 109
 110 static void fpga_serial_wait (void)
 111 {
 112         while ((in8 (UART (LSR)) & 0x40) == 0);
 113 }
 114
 115 static void fpga_serial_print (char c)
 116 {
 117         if (c == '\n') {
 118                 while ((in8 (UART (LSR)) & 0x20) == 0);
 119
 120                 out8 (UART (THR), '\r');
 121                 iobarrier_rw ();
 122         }
 123
 124         while ((in8 (UART (LSR)) & 0x20) == 0);
 125
 126         out8 (UART (THR), c);
 127         iobarrier_rw ();
 128
 129         if (c == '\n') {
 130                 fpga_serial_wait ();
 131         }
 132 }