]> git.ipfire.org Git - people/ms/u-boot.git/blob - board/pdm360ng/pdm360ng.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
board_f: Drop return value from initdram()
[people/ms/u-boot.git] / board / pdm360ng / pdm360ng.c
1 /*
2 * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
3 *
4 * (C) Copyright 2009-2010
5 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <asm/bitops.h>
12 #include <command.h>
13 #include <asm/io.h>
14 #include <asm/processor.h>
15 #include <asm/mpc512x.h>
16 #include <fdt_support.h>
17 #include <flash.h>
18 #ifdef CONFIG_MISC_INIT_R
19 #include <i2c.h>
20 #endif
21 #include <serial.h>
22 #include <jffs2/load_kernel.h>
23 #include <mtd_node.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 extern flash_info_t flash_info[];
28 ulong flash_get_size (phys_addr_t base, int banknum);
29
30 sdram_conf_t mddrc_config[] = {
31 {
32 (512 << 20), /* 512 MB RAM configuration */
33 {
34 CONFIG_SYS_MDDRC_SYS_CFG,
35 CONFIG_SYS_MDDRC_TIME_CFG0,
36 CONFIG_SYS_MDDRC_TIME_CFG1,
37 CONFIG_SYS_MDDRC_TIME_CFG2
38 }
39 },
40 {
41 (128 << 20), /* 128 MB RAM configuration */
42 {
43 CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
44 CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
45 CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
46 CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
47 }
48 },
49 };
50
51 int initdram(void)
52 {
53 int i;
54 u32 msize = 0;
55 u32 pdm360ng_init_seq[] = {
56 CONFIG_SYS_DDRCMD_NOP,
57 CONFIG_SYS_DDRCMD_NOP,
58 CONFIG_SYS_DDRCMD_NOP,
59 CONFIG_SYS_DDRCMD_NOP,
60 CONFIG_SYS_DDRCMD_NOP,
61 CONFIG_SYS_DDRCMD_NOP,
62 CONFIG_SYS_DDRCMD_NOP,
63 CONFIG_SYS_DDRCMD_NOP,
64 CONFIG_SYS_DDRCMD_NOP,
65 CONFIG_SYS_DDRCMD_NOP,
66 CONFIG_SYS_DDRCMD_PCHG_ALL,
67 CONFIG_SYS_DDRCMD_NOP,
68 CONFIG_SYS_DDRCMD_RFSH,
69 CONFIG_SYS_DDRCMD_NOP,
70 CONFIG_SYS_DDRCMD_RFSH,
71 CONFIG_SYS_DDRCMD_NOP,
72 CONFIG_SYS_MICRON_INIT_DEV_OP,
73 CONFIG_SYS_DDRCMD_NOP,
74 CONFIG_SYS_DDRCMD_EM2,
75 CONFIG_SYS_DDRCMD_NOP,
76 CONFIG_SYS_DDRCMD_PCHG_ALL,
77 CONFIG_SYS_DDRCMD_EM2,
78 CONFIG_SYS_DDRCMD_EM3,
79 CONFIG_SYS_DDRCMD_EN_DLL,
80 CONFIG_SYS_DDRCMD_RES_DLL,
81 CONFIG_SYS_DDRCMD_PCHG_ALL,
82 CONFIG_SYS_DDRCMD_RFSH,
83 CONFIG_SYS_DDRCMD_RFSH,
84 CONFIG_SYS_MICRON_INIT_DEV_OP,
85 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
86 CONFIG_SYS_DDRCMD_OCD_EXIT,
87 CONFIG_SYS_DDRCMD_PCHG_ALL,
88 CONFIG_SYS_DDRCMD_NOP
89 };
90
91 for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
92 msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
93 ARRAY_SIZE(pdm360ng_init_seq));
94 if (msize == mddrc_config[i].size)
95 break;
96 }
97
98 gd->ram_size = msize;
99
100 return 0;
101 }
102
103 static int set_lcd_brightness(char *);
104
105 int misc_init_r(void)
106 {
107 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
108
109 /*
110 * Re-configure flash setup using auto-detected info
111 */
112 if (flash_info[1].size > 0) {
113 out_be32(&im->sysconf.lpcs1aw,
114 CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
115 CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
116 flash_info[1].size));
117 sync_law(&im->sysconf.lpcs1aw);
118 /*
119 * Re-check to get correct base address
120 */
121 flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
122 } else {
123 /* Disable Bank 1 */
124 out_be32(&im->sysconf.lpcs1aw, 0x01000100);
125 sync_law(&im->sysconf.lpcs1aw);
126 }
127
128 out_be32(&im->sysconf.lpcs0aw,
129 CSAW_START(gd->bd->bi_flashstart) |
130 CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
131 sync_law(&im->sysconf.lpcs0aw);
132
133 /*
134 * Re-check to get correct base address
135 */
136 flash_get_size (gd->bd->bi_flashstart, 0);
137
138 /*
139 * Re-do flash protection upon new addresses
140 */
141 flash_protect (FLAG_PROTECT_CLEAR,
142 gd->bd->bi_flashstart, 0xffffffff,
143 &flash_info[0]);
144
145 /* Monitor protection ON by default */
146 flash_protect (FLAG_PROTECT_SET,
147 CONFIG_SYS_MONITOR_BASE,
148 CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
149 &flash_info[0]);
150
151 /* Environment protection ON by default */
152 flash_protect (FLAG_PROTECT_SET,
153 CONFIG_ENV_ADDR,
154 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
155 &flash_info[0]);
156
157 #ifdef CONFIG_ENV_ADDR_REDUND
158 /* Redundant environment protection ON by default */
159 flash_protect (FLAG_PROTECT_SET,
160 CONFIG_ENV_ADDR_REDUND,
161 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
162 &flash_info[0]);
163 #endif
164
165 #ifdef CONFIG_FSL_DIU_FB
166 set_lcd_brightness(0);
167 /* Switch LCD-Backlight and LVDS-Interface on */
168 setbits_be32(&im->gpio.gpdir, 0x01040000);
169 clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
170 #endif
171
172 #if defined(CONFIG_HARD_I2C)
173 if (!getenv("ethaddr")) {
174 uchar buf[6];
175 uchar ifm_oui[3] = { 0, 2, 1, };
176 int ret;
177
178 /* I2C-0 for on-board eeprom */
179 i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
180
181 /* Read ethaddr from EEPROM */
182 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
183 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
184 if (ret != 0) {
185 printf("Error: Unable to read MAC from I2C"
186 " EEPROM at address %02X:%02X\n",
187 CONFIG_SYS_I2C_EEPROM_ADDR,
188 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
189 return 1;
190 }
191
192 /* Owned by IFM ? */
193 if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
194 printf("Illegal MAC address in EEPROM: %pM\n", buf);
195 return 1;
196 }
197
198 eth_setenv_enetaddr("ethaddr", buf);
199 }
200 #endif /* defined(CONFIG_HARD_I2C) */
201
202 return 0;
203 }
204
205 static iopin_t ioregs_init[] = {
206 /* FUNC1=LPC_CS4 */
207 {
208 offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
209 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
210 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
211 },
212 /* FUNC3=GPIO10 */
213 {
214 offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
215 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
216 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
217 },
218 /* FUNC1=CAN3_TX */
219 {
220 offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
221 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
222 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
223 },
224 /* FUNC3=GPIO14 */
225 {
226 offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
227 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
228 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
229 },
230 /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
231 /* DIU_LD22-DIU_LD23 */
232 {
233 offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
234 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
235 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
236 },
237 /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
238 /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
239 {
240 offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
241 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
242 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
243 },
244 /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
245 /* VIU_DATA0-VIU_DATA2 */
246 {
247 offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
248 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
249 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
250 },
251 /* FUNC2=FEC_TXD_0 */
252 {
253 offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
254 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
255 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
256 },
257 /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
258 /* VIU_DATA3, VIU_DATA4 */
259 {
260 offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
261 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
262 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
263 },
264 /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
265 /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
266 /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
267 {
268 offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
269 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
270 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
271 },
272 /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
273 /* DIU_LD00-DIU_LD21 */
274 {
275 offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
276 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
277 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
278 },
279 /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
280 /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
281 {
282 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
283 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
284 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
285 },
286 /* FUNC2=CAN3_RX */
287 {
288 offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
289 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
290 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
291 },
292 /* Sets lowest slew on 2 CAN_TX Pins*/
293 {
294 offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
295 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
296 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
297 },
298 /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
299 /* CAN4_TX, CAN4_RX */
300 {
301 offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
302 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
303 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
304 },
305 /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
306 /* GPIO8, GPIO9 */
307 {
308 offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
309 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
310 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
311 },
312 /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
313 /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
314 {
315 offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
316 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
317 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
318 },
319 /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
320 /* FEC_RXD_3, FEC_RXD_2 */
321 {
322 offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
323 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
324 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
325 },
326 /* FUNC3=GPIO17 */
327 {
328 offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
329 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
330 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
331 },
332 /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
333 /* GPIO2, GPIO20, GPIO21 */
334 {
335 offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
336 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
337 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
338 },
339 /* FUNC2=VIU_PIX_CLK */
340 {
341 offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
342 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
343 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
344 },
345 /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
346 /* GPIO24, GPIO25 */
347 {
348 offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
349 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
350 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
351 },
352 /* FUNC1=NFC_CE2 */
353 {
354 offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
355 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
356 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
357 },
358 /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
359 /* VIU_DATA5-VIU_DATA9 */
360 {
361 offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
362 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
363 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
364 },
365 /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
366 /* LPC_TSIZ1-LPC_TSIZ2 */
367 {
368 offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
369 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
370 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
371 },
372 /* FUNC1=LPC_TS */
373 {
374 offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
375 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
376 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
377 },
378 /* FUNC3=GPIO16 */
379 {
380 offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
381 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
382 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
383 },
384 /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
385 /* GPIO18-GPIO19, GPT7/GPIO7 */
386 {
387 offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
388 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
389 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
390 },
391 /* FUNC3=GPIO0/GPT0 */
392 {
393 offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
394 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
395 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
396 },
397 /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
398 /* GPIO11, GPIO2, GPIO12, GPIO13 */
399 {
400 offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
401 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
402 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
403 },
404 /* FUNC2=DIU_DE */
405 {
406 offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
407 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
408 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
409 }
410 };
411
412 int checkboard (void)
413 {
414 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
415
416 puts("Board: PDM360NG\n");
417
418 /* initialize function mux & slew rate IO inter alia on IO Pins */
419
420 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
421
422 /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
423 setbits_be32(&im->io_ctrl.io_control_gp,
424 (1 << 0) | /* GP_MUX7->GPIO7 */
425 (1 << 5)); /* GP_MUX2->GPIO2 */
426
427 /* configure GPIO24 (VIU_CE), output/high */
428 setbits_be32(&im->gpio.gpdir, 0x80);
429 setbits_be32(&im->gpio.gpdat, 0x80);
430
431 return 0;
432 }
433
434 #ifdef CONFIG_OF_BOARD_SETUP
435 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
436 struct node_info nodes[] = {
437 { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
438 { "cfi-flash", MTD_DEV_TYPE_NOR, },
439 };
440 #endif
441
442 #if defined(CONFIG_VIDEO)
443 /*
444 * EDID block has been generated using Phoenix EDID Designer 1.3.
445 * This tool creates a text file containing:
446 *
447 * EDID BYTES:
448 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
449 * ------------------------------------------------
450 * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
451 * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
452 * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
453 * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
454 * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
455 * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
456 * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
457 * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
458 *
459 * Then this data has been manually converted to the char
460 * array below.
461 */
462 static unsigned char edid_buf[128] = {
463 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
464 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
465 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
466 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
467 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
468 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
469 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
470 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
471 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
472 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
473 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
474 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
475 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
476 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
477 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
478 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
479 };
480 #endif
481
482 int ft_board_setup(void *blob, bd_t *bd)
483 {
484 u32 val[8];
485 int rc, i = 0;
486
487 ft_cpu_setup(blob, bd);
488 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
489 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
490 #endif
491 #if defined(CONFIG_VIDEO)
492 fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
493 #endif
494
495 /* Fixup NOR FLASH mapping */
496 val[i++] = 0; /* chip select number */
497 val[i++] = 0; /* always 0 */
498 val[i++] = gd->bd->bi_flashstart;
499 val[i++] = gd->bd->bi_flashsize;
500
501 /* Fixup MRAM mapping */
502 val[i++] = 2; /* chip select number */
503 val[i++] = 0; /* always 0 */
504 val[i++] = CONFIG_SYS_MRAM_BASE;
505 val[i++] = CONFIG_SYS_MRAM_SIZE;
506
507 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
508 val, i * sizeof(u32), 1);
509 if (rc)
510 printf("Unable to update localbus ranges, err=%s\n",
511 fdt_strerror(rc));
512
513 /* Fixup reg property in NOR Flash node */
514 i = 0;
515 val[i++] = 0; /* always 0 */
516 val[i++] = 0; /* start at offset 0 */
517 val[i++] = flash_info[0].size; /* size of Bank 0 */
518
519 /* Second Bank available? */
520 if (flash_info[1].size > 0) {
521 val[i++] = 0; /* always 0 */
522 val[i++] = flash_info[0].size; /* offset of Bank 1 */
523 val[i++] = flash_info[1].size; /* size of Bank 1 */
524 }
525
526 rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
527 val, i * sizeof(u32), 1);
528 if (rc)
529 printf("Unable to update flash reg property, err=%s\n",
530 fdt_strerror(rc));
531
532 return 0;
533 }
534 #endif /* CONFIG_OF_BOARD_SETUP */
535
536 /*
537 * If argument is NULL, set the LCD brightness to the
538 * value from "brightness" environment variable. Set
539 * the LCD brightness to the value specified by the
540 * argument otherwise. Default brightness is zero.
541 */
542 #define MAX_BRIGHTNESS 99
543 static int set_lcd_brightness(char *brightness)
544 {
545 struct stdio_dev *cop_port;
546 char *env;
547 char cmd_buf[20];
548 int val = 0;
549 int cs = 0;
550 int len, i;
551
552 if (brightness) {
553 val = simple_strtol(brightness, NULL, 10);
554 } else {
555 env = getenv("brightness");
556 if (env)
557 val = simple_strtol(env, NULL, 10);
558 }
559
560 if (val < 0)
561 val = 0;
562
563 if (val > MAX_BRIGHTNESS)
564 val = MAX_BRIGHTNESS;
565
566 sprintf(cmd_buf, "$SB;%04d;", val);
567
568 len = strlen(cmd_buf);
569 for (i = 1; i <= len; i++)
570 cs += cmd_buf[i];
571
572 cs = (~cs + 1) & 0xff;
573 sprintf(cmd_buf + len, "%02X\n", cs);
574
575 /* IO Coprocessor communication */
576 cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
577 if (!cop_port) {
578 printf("Error: Can't open IO Coprocessor port.\n");
579 return -1;
580 }
581
582 debug("%s: cmd: %s", __func__, cmd_buf);
583 write_port(cop_port, cmd_buf);
584 /*
585 * Wait for transmission and maybe response data
586 * before closing the port.
587 */
588 udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
589 memset(cmd_buf, 0, sizeof(cmd_buf));
590 len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
591 if (len)
592 printf("Error: %s\n", cmd_buf);
593
594 close_port(4);
595
596 return 0;
597 }
598
599 static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
600 int argc, char * const argv[])
601 {
602 if (argc < 2)
603 return cmd_usage(cmdtp);
604
605 return set_lcd_brightness(argv[1]);
606 }
607
608 U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
609 "set LCD brightness",
610 "<brightness> - set LCD backlight level to <brightness>.\n"
611 );
"Das U-Boot" Source Tree