board/phytec/pcm058/pcm058.c

   1 /*
   2  * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Please note: there are two version of the board
   9  * one with NAND and the other with eMMC.
  10  * Both NAND and eMMC cannot be set because they share the
  11  * same pins (SD4)
  12  */
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/mx6-ddr.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/imx-common/iomux-v3.h>
  22 #include <asm/imx-common/boot_mode.h>
  23 #include <asm/imx-common/mxc_i2c.h>
  24 #include <asm/imx-common/spi.h>
  25 #include <asm/errno.h>
  26 #include <asm/gpio.h>
  27 #include <mmc.h>
  28 #include <i2c.h>
  29 #include <fsl_esdhc.h>
  30 #include <nand.h>
  31 #include <miiphy.h>
  32 #include <netdev.h>
  33 #include <asm/arch/sys_proto.h>
  34 #include <asm/sections.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  43         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48
  49 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  50                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  51
  52 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  54         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  55
  56 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  57
  58 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP  |     \
  59                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  60
  61 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  62                PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  63
  64 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
  65 #define USDHC1_CD_GPIO  IMX_GPIO_NR(6, 31)
  66 #define USER_LED        IMX_GPIO_NR(1, 4)
  67 #define IMX6Q_DRIVE_STRENGTH    0x30
  68
  69 int dram_init(void)
  70 {
  71         gd->ram_size = imx_ddr_size();
  72         return 0;
  73 }
  74
  75 void board_turn_off_led(void)
  76 {
  77         gpio_direction_output(USER_LED, 0);
  78 }
  79
  80 static iomux_v3_cfg_t const uart1_pads[] = {
  81         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  82         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  83 };
  84
  85 static iomux_v3_cfg_t const enet_pads[] = {
  86         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 100         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 101         MX6_PAD_SD2_DAT1__GPIO1_IO14    | MUX_PAD_CTRL(NO_PAD_CTRL),
 102 };
 103
 104 static iomux_v3_cfg_t const ecspi1_pads[] = {
 105         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 106         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 107         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 108         MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 109 };
 110
 111 /* NAND */
 112 static iomux_v3_cfg_t const nfc_pads[] = {
 113         MX6_PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NAND_PAD_CTRL),
 114         MX6_PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NAND_PAD_CTRL),
 115         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 116         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
 117         MX6_PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 118         MX6_PAD_NANDF_CS1__NAND_CE1_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 119         MX6_PAD_NANDF_CS2__NAND_CE2_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 120         MX6_PAD_NANDF_CS3__NAND_CE3_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 121         MX6_PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NAND_PAD_CTRL),
 122         MX6_PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NAND_PAD_CTRL),
 123         MX6_PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 124         MX6_PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 125         MX6_PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 126         MX6_PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 127         MX6_PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 128         MX6_PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 129         MX6_PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 130         MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 131         MX6_PAD_SD4_DAT0__NAND_DQS      | MUX_PAD_CTRL(NAND_PAD_CTRL),
 132 };
 133
 134
 135 /* GPIOS */
 136 static iomux_v3_cfg_t const gpios_pads[] = {
 137 };
 138
 139 static struct i2c_pads_info i2c_pad_info2 = {
 140         .scl = {
 141                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
 142                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
 143                 .gp = IMX_GPIO_NR(1, 5)
 144         },
 145         .sda = {
 146                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 147                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 148                 .gp = IMX_GPIO_NR(1, 6)
 149         }
 150 };
 151
 152 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 153         {.esdhc_base = USDHC1_BASE_ADDR,
 154         .max_bus_width = 4},
 155 #ifndef CONFIG_CMD_NAND
 156         {USDHC4_BASE_ADDR},
 157 #endif
 158 };
 159
 160 static iomux_v3_cfg_t const usdhc1_pads[] = {
 161         MX6_PAD_SD1_CLK__SD1_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD1_CMD__SD1_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD1_DAT0__SD1_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD1_DAT1__SD1_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD1_DAT2__SD1_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_SD1_DAT3__SD1_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 168 };
 169
 170 #ifndef CONFIG_CMD_NAND
 171 static iomux_v3_cfg_t const usdhc4_pads[] = {
 172         MX6_PAD_SD4_CLK__SD4_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 173         MX6_PAD_SD4_CMD__SD4_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 174         MX6_PAD_SD4_DAT0__SD4_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 175         MX6_PAD_SD4_DAT1__SD4_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 176         MX6_PAD_SD4_DAT2__SD4_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 177         MX6_PAD_SD4_DAT3__SD4_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 178         MX6_PAD_SD4_DAT4__SD4_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 179         MX6_PAD_SD4_DAT5__SD4_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 180         MX6_PAD_SD4_DAT6__SD4_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 181         MX6_PAD_SD4_DAT7__SD4_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 182 };
 183 #endif
 184
 185 int board_mmc_get_env_dev(int devno)
 186 {
 187         return devno - 1;
 188 }
 189
 190 int board_mmc_getcd(struct mmc *mmc)
 191 {
 192         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 193         int ret = 0;
 194
 195         switch (cfg->esdhc_base) {
 196         case USDHC1_BASE_ADDR:
 197                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 198                 break;
 199         case USDHC4_BASE_ADDR:
 200                 ret = 1; /* eMMC/uSDHC4 is always present */
 201                 break;
 202         }
 203
 204         return ret;
 205 }
 206
 207 int board_mmc_init(bd_t *bis)
 208 {
 209 #ifndef CONFIG_SPL_BUILD
 210         int ret;
 211         int i;
 212
 213         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 214                 switch (i) {
 215                 case 0:
 216                         imx_iomux_v3_setup_multiple_pads(
 217                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 218                         gpio_direction_input(USDHC1_CD_GPIO);
 219                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 220                         break;
 221 #ifndef CONFIG_CMD_NAND
 222                 case 1:
 223                         imx_iomux_v3_setup_multiple_pads(
 224                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 225                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 226                         break;
 227 #endif
 228                 default:
 229                         printf("Warning: you configured more USDHC controllers"
 230                                "(%d) then supported by the board (%d)\n",
 231                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 232                         return -EINVAL;
 233                 }
 234
 235                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 236                 if (ret)
 237                         return ret;
 238         }
 239
 240         return 0;
 241 #else
 242         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 243         unsigned reg = readl(&psrc->sbmr1) >> 11;
 244         /*
 245          * Upon reading BOOT_CFG register the following map is done:
 246          * Bit 11 and 12 of BOOT_CFG register can determine the current
 247          * mmc port
 248          * 0x1                  SD1
 249          * 0x2                  SD2
 250          * 0x3                  SD4
 251          */
 252
 253         switch (reg & 0x3) {
 254         case 0x0:
 255                 imx_iomux_v3_setup_multiple_pads(
 256                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 257                 gpio_direction_input(USDHC1_CD_GPIO);
 258                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 259                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 260                 usdhc_cfg[0].max_bus_width = 4;
 261                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 262                 break;
 263         }
 264         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 265 #endif
 266 }
 267
 268 static void setup_iomux_uart(void)
 269 {
 270         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 271 }
 272
 273 static void setup_iomux_enet(void)
 274 {
 275         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 276
 277         gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
 278         mdelay(10);
 279         gpio_set_value(ENET_PHY_RESET_GPIO, 1);
 280         mdelay(30);
 281 }
 282
 283 static void setup_spi(void)
 284 {
 285         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0");
 286         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 287
 288         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 289
 290         enable_spi_clk(true, 0);
 291 }
 292
 293 #ifdef CONFIG_CMD_NAND
 294 static void setup_gpmi_nand(void)
 295 {
 296         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 297
 298         /* config gpmi nand iomux */
 299         imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
 300
 301         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 302         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 303
 304         /* config gpmi and bch clock to 100 MHz */
 305         clrsetbits_le32(&mxc_ccm->cs2cdr,
 306                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 307                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 308                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 309                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 310                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 311                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 312
 313         /* enable ENFC_CLK_ROOT clock */
 314         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 315
 316         /* enable gpmi and bch clock gating */
 317         setbits_le32(&mxc_ccm->CCGR4,
 318                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 319                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 320                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 321                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 322                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 323
 324         /* enable apbh clock gating */
 325         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 326 }
 327 #endif
 328
 329 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 330 {
 331         if (bus != 0 || (cs != 0))
 332                 return -EINVAL;
 333
 334         return IMX_GPIO_NR(3, 19);
 335 }
 336
 337 int board_eth_init(bd_t *bis)
 338 {
 339         setup_iomux_enet();
 340
 341         return cpu_eth_init(bis);
 342 }
 343
 344 int board_early_init_f(void)
 345 {
 346         setup_iomux_uart();
 347
 348         return 0;
 349 }
 350
 351 int board_init(void)
 352 {
 353         /* address of boot parameters */
 354         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 355
 356 #ifdef CONFIG_SYS_I2C_MXC
 357         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 358 #endif
 359
 360 #ifdef CONFIG_MXC_SPI
 361         setup_spi();
 362 #endif
 363
 364 #ifdef CONFIG_CMD_NAND
 365         setup_gpmi_nand();
 366 #endif
 367         return 0;
 368 }
 369
 370
 371 #ifdef CONFIG_CMD_BMODE
 372 /*
 373  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 374  * see Table 8-11 and Table 5-9
 375  *  BOOT_CFG1[7] = 1 (boot from NAND)
 376  *  BOOT_CFG1[5] = 0 - raw NAND
 377  *  BOOT_CFG1[4] = 0 - default pad settings
 378  *  BOOT_CFG1[3:2] = 00 - devices = 1
 379  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 380  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 381  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 382  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 383  */
 384 static const struct boot_mode board_boot_modes[] = {
 385         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 386         {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
 387         {"mmc0",  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 388         {NULL, 0},
 389 };
 390 #endif
 391
 392 int board_late_init(void)
 393 {
 394 #ifdef CONFIG_CMD_BMODE
 395         add_board_boot_modes(board_boot_modes);
 396 #endif
 397
 398         return 0;
 399 }
 400
 401 #ifdef CONFIG_SPL_BUILD
 402 #include <spl.h>
 403 #include <libfdt.h>
 404
 405 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
 406         .dram_sdclk_0 = 0x00000030,
 407         .dram_sdclk_1 = 0x00000030,
 408         .dram_cas = 0x00000030,
 409         .dram_ras = 0x00000030,
 410         .dram_reset = 0x00000030,
 411         .dram_sdcke0 = 0x00000030,
 412         .dram_sdcke1 = 0x00000030,
 413         .dram_sdba2 = 0x00000000,
 414         .dram_sdodt0 = 0x00000030,
 415         .dram_sdodt1 = 0x00000030,
 416         .dram_sdqs0 = 0x00000030,
 417         .dram_sdqs1 = 0x00000030,
 418         .dram_sdqs2 = 0x00000030,
 419         .dram_sdqs3 = 0x00000030,
 420         .dram_sdqs4 = 0x00000030,
 421         .dram_sdqs5 = 0x00000030,
 422         .dram_sdqs6 = 0x00000030,
 423         .dram_sdqs7 = 0x00000030,
 424         .dram_dqm0 = 0x00000030,
 425         .dram_dqm1 = 0x00000030,
 426         .dram_dqm2 = 0x00000030,
 427         .dram_dqm3 = 0x00000030,
 428         .dram_dqm4 = 0x00000030,
 429         .dram_dqm5 = 0x00000030,
 430         .dram_dqm6 = 0x00000030,
 431         .dram_dqm7 = 0x00000030,
 432 };
 433
 434 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
 435         .grp_ddr_type =  0x000C0000,
 436         .grp_ddrmode_ctl =  0x00020000,
 437         .grp_ddrpke =  0x00000000,
 438         .grp_addds = IMX6Q_DRIVE_STRENGTH,
 439         .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
 440         .grp_ddrmode =  0x00020000,
 441         .grp_b0ds = IMX6Q_DRIVE_STRENGTH,
 442         .grp_b1ds = IMX6Q_DRIVE_STRENGTH,
 443         .grp_b2ds = IMX6Q_DRIVE_STRENGTH,
 444         .grp_b3ds = IMX6Q_DRIVE_STRENGTH,
 445         .grp_b4ds = IMX6Q_DRIVE_STRENGTH,
 446         .grp_b5ds = IMX6Q_DRIVE_STRENGTH,
 447         .grp_b6ds = IMX6Q_DRIVE_STRENGTH,
 448         .grp_b7ds = IMX6Q_DRIVE_STRENGTH,
 449 };
 450
 451 static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 452         .p0_mpwldectrl0 =  0x00140014,
 453         .p0_mpwldectrl1 =  0x000A0015,
 454         .p1_mpwldectrl0 =  0x000A001E,
 455         .p1_mpwldectrl1 =  0x000A0015,
 456         .p0_mpdgctrl0 =  0x43080314,
 457         .p0_mpdgctrl1 =  0x02680300,
 458         .p1_mpdgctrl0 =  0x430C0318,
 459         .p1_mpdgctrl1 =  0x03000254,
 460         .p0_mprddlctl =  0x3A323234,
 461         .p1_mprddlctl =  0x3E3C3242,
 462         .p0_mpwrdlctl =  0x2A2E3632,
 463         .p1_mpwrdlctl =  0x3C323E34,
 464 };
 465
 466 static struct mx6_ddr3_cfg mem_ddr = {
 467         .mem_speed = 1600,
 468         .density = 2,
 469         .width = 16,
 470         .banks = 8,
 471         .rowaddr = 14,
 472         .coladdr = 10,
 473         .pagesz = 2,
 474         .trcd = 1375,
 475         .trcmin = 4875,
 476         .trasmin = 3500,
 477         .SRT       = 1,
 478 };
 479
 480 static void ccgr_init(void)
 481 {
 482         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 483
 484         writel(0x00C03F3F, &ccm->CCGR0);
 485         writel(0x0030FC03, &ccm->CCGR1);
 486         writel(0x0FFFC000, &ccm->CCGR2);
 487         writel(0x3FF00000, &ccm->CCGR3);
 488         writel(0x00FFF300, &ccm->CCGR4);
 489         writel(0x0F0000C3, &ccm->CCGR5);
 490         writel(0x000003FF, &ccm->CCGR6);
 491 }
 492
 493 static void gpr_init(void)
 494 {
 495         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 496
 497         /* enable AXI cache for VDOA/VPU/IPU */
 498         writel(0xF00000CF, &iomux->gpr[4]);
 499         /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 500         writel(0x007F007F, &iomux->gpr[6]);
 501         writel(0x007F007F, &iomux->gpr[7]);
 502 }
 503
 504
 505 static void spl_dram_init(void)
 506 {
 507         struct mx6_ddr_sysinfo sysinfo = {
 508                 /* width of data bus:0=16,1=32,2=64 */
 509                 .dsize = 2,
 510                 /* config for full 4GB range so that get_mem_size() works */
 511                 .cs_density = 32, /* 32Gb per CS */
 512                 /* single chip select */
 513                 .ncs = 1,
 514                 .cs1_mirror = 0,
 515                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 516                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 517                 .walat = 1,     /* Write additional latency */
 518                 .ralat = 5,     /* Read additional latency */
 519                 .mif3_mode = 3, /* Command prediction working mode */
 520                 .bi_on = 1,     /* Bank interleaving enabled */
 521                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 522                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 523                 .ddr_type = DDR_TYPE_DDR3,
 524                 .refsel = 1,    /* Refresh cycles at 32KHz */
 525                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 526         };
 527
 528         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 529         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 530 }
 531
 532 void board_boot_order(u32 *spl_boot_list)
 533 {
 534         spl_boot_list[0] = spl_boot_device();
 535         printf("Boot device %x\n", spl_boot_list[0]);
 536         switch (spl_boot_list[0]) {
 537         case BOOT_DEVICE_SPI:
 538                 spl_boot_list[1] = BOOT_DEVICE_UART;
 539                 break;
 540         case BOOT_DEVICE_MMC1:
 541                 spl_boot_list[1] = BOOT_DEVICE_SPI;
 542                 spl_boot_list[2] = BOOT_DEVICE_UART;
 543                 break;
 544         default:
 545                 printf("Boot device %x\n", spl_boot_list[0]);
 546         }
 547 }
 548
 549 void board_init_f(ulong dummy)
 550 {
 551 #ifdef CONFIG_CMD_NAND
 552         /* Enable NAND */
 553         setup_gpmi_nand();
 554 #endif
 555
 556         /* setup clock gating */
 557         ccgr_init();
 558
 559         /* setup AIPS and disable watchdog */
 560         arch_cpu_init();
 561
 562         /* setup AXI */
 563         gpr_init();
 564
 565         board_early_init_f();
 566
 567         /* setup GP timer */
 568         timer_init();
 569
 570         setup_spi();
 571
 572         /* UART clocks enabled and gd valid - init serial console */
 573         preloader_console_init();
 574
 575         /* DDR initialization */
 576         spl_dram_init();
 577
 578         /* Clear the BSS. */
 579         memset(__bss_start, 0, __bss_end - __bss_start);
 580
 581         /* load/boot image from boot device */
 582         board_init_r(NULL, 0);
 583 }
 584 #endif