board/prodrive/alpr/alpr.c

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8
   9 #include <common.h>
  10 #include <libfdt.h>
  11 #include <fdt_support.h>
  12 #include <spd_sdram.h>
  13 #include <asm/ppc4xx-emac.h>
  14 #include <miiphy.h>
  15 #include <asm/processor.h>
  16 #include <asm/4xx_pci.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 extern int alpr_fpga_init(void);
  21
  22 int board_early_init_f (void)
  23 {
  24         /*-------------------------------------------------------------------------
  25          * Initialize EBC CONFIG
  26          *-------------------------------------------------------------------------*/
  27         mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
  28               EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
  29               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
  30               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
  31               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
  32
  33         /*--------------------------------------------------------------------
  34          * Setup the interrupt controller polarities, triggers, etc.
  35          *-------------------------------------------------------------------*/
  36         /*
  37          * Because of the interrupt handling rework to handle 440GX interrupts
  38          * with the common code, we needed to change names of the UIC registers.
  39          * Here the new relationship:
  40          *
  41          * U-Boot name  440GX name
  42          * -----------------------
  43          * UIC0         UICB0
  44          * UIC1         UIC0
  45          * UIC2         UIC1
  46          * UIC3         UIC2
  47          */
  48         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
  49         mtdcr (UIC1ER, 0x00000000);     /* disable all */
  50         mtdcr (UIC1CR, 0x00000009);     /* SMI & UIC1 crit are critical */
  51         mtdcr (UIC1PR, 0xfffffe03);     /* per manual */
  52         mtdcr (UIC1TR, 0x01c00000);     /* per manual */
  53         mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
  54         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
  55
  56         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
  57         mtdcr (UIC2ER, 0x00000000);     /* disable all */
  58         mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
  59         mtdcr (UIC2PR, 0xffffe0ff);     /* per ref-board manual */
  60         mtdcr (UIC2TR, 0x00ffc000);     /* per ref-board manual */
  61         mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
  62         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
  63
  64         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
  65         mtdcr (UIC3ER, 0x00000000);     /* disable all */
  66         mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
  67         mtdcr (UIC3PR, 0xffffffff);     /* per ref-board manual */
  68         mtdcr (UIC3TR, 0x00ff8c0f);     /* per ref-board manual */
  69         mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
  70         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
  71
  72         mtdcr (UIC0SR, 0xfc000000); /* clear all */
  73         mtdcr (UIC0ER, 0x00000000); /* disable all */
  74         mtdcr (UIC0CR, 0x00000000); /* all non-critical */
  75         mtdcr (UIC0PR, 0xfc000000); /* */
  76         mtdcr (UIC0TR, 0x00000000); /* */
  77         mtdcr (UIC0VR, 0x00000001); /* */
  78
  79         /* Setup shutdown/SSD empty interrupt as inputs */
  80         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
  81         out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
  82
  83         /* Setup GPIO/IRQ multiplexing */
  84         mtsdr(SDR0_PFC0, 0x01a33e00);
  85
  86         return 0;
  87 }
  88
  89 int last_stage_init(void)
  90 {
  91         unsigned short reg;
  92
  93         /*
  94          * Configure LED's of both Marvell 88E1111 PHY's
  95          *
  96          * This has to be done after the 4xx ethernet driver is loaded,
  97          * so "last_stage_init()" is the right place.
  98          */
  99         miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, &reg);
 100         reg |= 0x0001;
 101         miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
 102         miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, &reg);
 103         reg |= 0x0001;
 104         miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
 105
 106         return 0;
 107 }
 108
 109 static int board_rev(void)
 110 {
 111         /* Setup as input */
 112         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
 113         out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
 114
 115         return (in32(GPIO0_IR) >> 16) & 0x3;
 116 }
 117
 118 int checkboard (void)
 119 {
 120         char buf[64];
 121         int i = getenv_f("serial#", buf, sizeof(buf));
 122
 123         printf ("Board: ALPR");
 124         if (i > 0) {
 125                 puts(", serial# ");
 126                 puts(buf);
 127         }
 128         printf(" (Rev. %d)\n", board_rev());
 129
 130         return (0);
 131 }
 132
 133 #if defined(CONFIG_PCI)
 134 /*
 135  * Override weak pci_pre_init()
 136  */
 137 int pci_pre_init(struct pci_controller *hose)
 138 {
 139         if (__pci_pre_init(hose) == 0)
 140                 return 0;
 141
 142         /* FPGA Init */
 143         alpr_fpga_init();
 144
 145         return 1;
 146 }
 147
 148 /*************************************************************************
 149  * Override weak is_pci_host()
 150  *
 151  *      This routine is called to determine if a pci scan should be
 152  *      performed. With various hardware environments (especially cPCI and
 153  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 154  *      bit in the strap register, or generic host/adapter assumptions.
 155  *
 156  *      Rather than hard-code a bad assumption in the general 440 code, the
 157  *      440 pci code requires the board to decide at runtime.
 158  *
 159  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 160  *
 161  *
 162  ************************************************************************/
 163 static void wait_for_pci_ready(void)
 164 {
 165         /*
 166          * Configure EREADY as input
 167          */
 168         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY);
 169         udelay(1000);
 170
 171         for (;;) {
 172                 if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY)
 173                         return;
 174         }
 175
 176 }
 177
 178 int is_pci_host(struct pci_controller *hose)
 179 {
 180         wait_for_pci_ready();
 181         return 1;               /* return 1 for host controller */
 182 }
 183 #endif /* defined(CONFIG_PCI) */
 184
 185 /*************************************************************************
 186  *  pci_master_init
 187  *
 188  ************************************************************************/
 189 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 190 void pci_master_init(struct pci_controller *hose)
 191 {
 192         /*--------------------------------------------------------------------------+
 193           | PowerPC440 PCI Master configuration.
 194           | Map PLB/processor addresses to PCI memory space.
 195           |   PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
 196           |   Use byte reversed out routines to handle endianess.
 197           | Make this region non-prefetchable.
 198           +--------------------------------------------------------------------------*/
 199         out32r( PCIL0_POM0SA, 0 ); /* disable */
 200         out32r( PCIL0_POM1SA, 0 ); /* disable */
 201         out32r( PCIL0_POM2SA, 0 ); /* disable */
 202
 203         out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE);  /* PMM0 Local Address */
 204         out32r(PCIL0_POM0LAH, 0x00000003);      /* PMM0 Local Address */
 205         out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
 206         out32r(PCIL0_POM0PCIAH, 0x00000000);    /* PMM0 PCI High Address */
 207         out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
 208
 209         out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
 210         out32r(PCIL0_POM1LAH, 0x00000003);      /* PMM0 Local Address */
 211         out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
 212         out32r(PCIL0_POM1PCIAH, 0x00000000);    /* PMM0 PCI High Address */
 213         out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1);    /* 256MB + enable region */
 214 }
 215 #endif                          /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */