board/prodrive/p3p440/p3p440.c

   1 /*
   2  * (C) Copyright 2005
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/processor.h>
  28 #include <command.h>
  29
  30 #include "p3p440.h"
  31
  32 void set_led(int color)
  33 {
  34         switch (color) {
  35         case LED_OFF:
  36                 out32(GPIO0_OR,  in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED);
  37                 break;
  38
  39         case LED_GREEN:
  40                 out32(GPIO0_OR,  (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED);
  41                 break;
  42
  43         case LED_RED:
  44                 out32(GPIO0_OR,  (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN);
  45                 break;
  46
  47         case LED_ORANGE:
  48                 out32(GPIO0_OR,  in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED);
  49                 break;
  50         }
  51 }
  52
  53 static int is_monarch(void)
  54 {
  55         out32(GPIO0_OR,  in32(GPIO0_OR) & ~CFG_GPIO_RDY);
  56         udelay(1000);
  57
  58         if (in32(GPIO0_IR) & CFG_MONARCH_IO)
  59                 return 0;
  60         else
  61                 return 1;
  62 }
  63
  64 static void wait_for_pci_ready(void)
  65 {
  66         /*
  67          * Configure EREADY_IO as input
  68          */
  69         out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO);
  70         udelay(1000);
  71
  72         for (;;) {
  73                 if (in32(GPIO0_IR) & CFG_EREADY_IO)
  74                         return;
  75         }
  76
  77 }
  78
  79 int board_early_init_f(void)
  80 {
  81         uint reg;
  82
  83         /*--------------------------------------------------------------------
  84          * Setup the external bus controller/chip selects
  85          *-------------------------------------------------------------------*/
  86         mtdcr(ebccfga, xbcfg);
  87         reg = mfdcr(ebccfgd);
  88         mtdcr(ebccfgd, reg | 0x04000000);       /* Set ATC */
  89
  90         /*--------------------------------------------------------------------
  91          * Setup pin multiplexing (GPIO/IRQ...)
  92          *-------------------------------------------------------------------*/
  93         mtdcr(cpc0_gpio, 0x03F01F80);
  94
  95         out32(GPIO0_ODR, 0x00000000);   /* no open drain pins      */
  96         out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN);
  97         out32(GPIO0_OR,  CFG_GPIO_RDY);
  98
  99         /*--------------------------------------------------------------------
 100          * Setup the interrupt controller polarities, triggers, etc.
 101          *-------------------------------------------------------------------*/
 102         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 103         mtdcr(uic0er, 0x00000000);      /* disable all */
 104         mtdcr(uic0cr, 0x00000001);      /* UIC1 crit is critical */
 105         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
 106         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
 107         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
 108         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 109
 110         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 111         mtdcr(uic1er, 0x00000000);      /* disable all */
 112         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 113         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
 114         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
 115         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
 116         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 117
 118         return 0;
 119 }
 120
 121 int checkboard(void)
 122 {
 123         char *s = getenv("serial#");
 124
 125         printf("Board: P3P440");
 126         if (s != NULL) {
 127                 puts(", serial# ");
 128                 puts(s);
 129         }
 130
 131         if (is_monarch()) {
 132                 puts(", Monarch");
 133         } else {
 134                 puts(", None-Monarch");
 135         }
 136
 137         putc('\n');
 138
 139         return (0);
 140 }
 141
 142 int misc_init_r (void)
 143 {
 144         DECLARE_GLOBAL_DATA_PTR;
 145
 146         /*
 147          * Adjust flash start and offset to detected values
 148          */
 149         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 150         gd->bd->bi_flashoffset = 0;
 151
 152         /*
 153          * Check if only one FLASH bank is available
 154          */
 155         if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
 156                 mtebc(pb1cr, 0);                        /* disable cs */
 157                 mtebc(pb1ap, 0);
 158                 mtebc(pb2cr, 0);                        /* disable cs */
 159                 mtebc(pb2ap, 0);
 160                 mtebc(pb3cr, 0);                        /* disable cs */
 161                 mtebc(pb3ap, 0);
 162         }
 163
 164         return 0;
 165 }
 166
 167 /*************************************************************************
 168  *  pci_pre_init
 169  *
 170  *  This routine is called just prior to registering the hose and gives
 171  *  the board the opportunity to check things. Returning a value of zero
 172  *  indicates that things are bad & PCI initialization should be aborted.
 173  *
 174  *      Different boards may wish to customize the pci controller structure
 175  *      (add regions, override default access routines, etc) or perform
 176  *      certain pre-initialization actions.
 177  *
 178  ************************************************************************/
 179 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 180 int pci_pre_init(struct pci_controller *hose)
 181 {
 182         unsigned long strap;
 183
 184         /*--------------------------------------------------------------------------+
 185          *      The P3P440 board is always configured as the host & requires the
 186          *      PCI arbiter to be disabled because it's an PMC module.
 187          *--------------------------------------------------------------------------*/
 188         strap = mfdcr(cpc0_strp1);
 189         if (strap & 0x00100000) {
 190                 printf("PCI: CPC0_STRP1[PAE] set.\n");
 191                 return 0;
 192         }
 193
 194         return 1;
 195 }
 196 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 197
 198 /*************************************************************************
 199  *  pci_target_init
 200  *
 201  *      The bootstrap configuration provides default settings for the pci
 202  *      inbound map (PIM). But the bootstrap config choices are limited and
 203  *      may not be sufficient for a given board.
 204  *
 205  ************************************************************************/
 206 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 207 void pci_target_init(struct pci_controller *hose)
 208 {
 209         DECLARE_GLOBAL_DATA_PTR;
 210
 211         /*--------------------------------------------------------------------------+
 212          * Disable everything
 213          *--------------------------------------------------------------------------*/
 214         out32r(PCIX0_PIM0SA, 0);        /* disable */
 215         out32r(PCIX0_PIM1SA, 0);        /* disable */
 216         out32r(PCIX0_PIM2SA, 0);        /* disable */
 217         out32r(PCIX0_EROMBA, 0);        /* disable expansion rom */
 218
 219         /*--------------------------------------------------------------------------+
 220          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 221          * options to not support sizes such as 128/256 MB.
 222          *--------------------------------------------------------------------------*/
 223         out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
 224         out32r(PCIX0_PIM0LAH, 0);
 225         out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 226
 227         out32r(PCIX0_BAR0, 0);
 228
 229         /*--------------------------------------------------------------------------+
 230          * Program the board's subsystem id/vendor id
 231          *--------------------------------------------------------------------------*/
 232         out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
 233         out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
 234
 235         out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 236 }
 237 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 238
 239 /*************************************************************************
 240  *  is_pci_host
 241  *
 242  *      This routine is called to determine if a pci scan should be
 243  *      performed. With various hardware environments (especially cPCI and
 244  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 245  *      bit in the strap register, or generic host/adapter assumptions.
 246  *
 247  *      Rather than hard-code a bad assumption in the general 440 code, the
 248  *      440 pci code requires the board to decide at runtime.
 249  *
 250  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 251  *
 252  *
 253  ************************************************************************/
 254 #if defined(CONFIG_PCI)
 255 int is_pci_host(struct pci_controller *hose)
 256 {
 257         if (is_monarch()) {
 258                 wait_for_pci_ready();
 259                 return 1;               /* return 1 for host controller */
 260         } else {
 261                 return 0;               /* return 0 for adapter controller */
 262         }
 263 }
 264 #endif                          /* defined(CONFIG_PCI) */