board/pxa255_idp/lowlevel_init.S

   1 /*
   2  * Most of this taken from Redboot hal_platform_setup.h with cleanup
   3  *
   4  * NOTE: I haven't clean this up considerably, just enough to get it
   5  * running. See hal_platform_setup.h for the source. See
   6  * board/cradle/lowlevel_init.S for another PXA250 setup that is
   7  * much cleaner.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <version.h>
  30 #include <asm/arch/pxa-regs.h>
  31
  32 DRAM_SIZE:  .long   CFG_DRAM_SIZE
  33
  34 /* wait for coprocessor write complete */
  35         .macro CPWAIT reg
  36         mrc  p15,0,\reg,c2,c0,0
  37         mov  \reg,\reg
  38         sub  pc,pc,#4
  39         .endm
  40
  41 /*
  42  *      Memory setup
  43  */
  44 .globl lowlevel_init
  45 lowlevel_init:
  46
  47         mov      r10, lr
  48
  49 #ifdef DEBUG_BLINK_ENABLE
  50         /* 3rd blink */
  51         bl      blink
  52 #endif
  53
  54         /* Set up GPIO pins first ----------------------------------------- */
  55         ldr             r0,     =GPSR0
  56         ldr             r1,     =CFG_GPSR0_VAL
  57         str             r1,   [r0]
  58
  59         ldr             r0,     =GPSR1
  60         ldr             r1,     =CFG_GPSR1_VAL
  61         str             r1,   [r0]
  62
  63         ldr             r0,     =GPSR2
  64         ldr             r1,     =CFG_GPSR2_VAL
  65         str             r1,   [r0]
  66
  67         ldr             r0,     =GPCR0
  68         ldr             r1,     =CFG_GPCR0_VAL
  69         str             r1,   [r0]
  70
  71         ldr             r0,     =GPCR1
  72         ldr             r1,     =CFG_GPCR1_VAL
  73         str             r1,   [r0]
  74
  75         ldr             r0,     =GPCR2
  76         ldr             r1,     =CFG_GPCR2_VAL
  77         str             r1,   [r0]
  78
  79         ldr             r0,     =GPDR0
  80         ldr             r1,     =CFG_GPDR0_VAL
  81         str             r1,   [r0]
  82
  83         ldr             r0,     =GPDR1
  84         ldr             r1,     =CFG_GPDR1_VAL
  85         str             r1,   [r0]
  86
  87         ldr             r0,     =GPDR2
  88         ldr             r1,     =CFG_GPDR2_VAL
  89         str             r1,   [r0]
  90
  91         ldr             r0,     =GAFR0_L
  92         ldr             r1,     =CFG_GAFR0_L_VAL
  93         str             r1,   [r0]
  94
  95         ldr             r0,     =GAFR0_U
  96         ldr             r1,     =CFG_GAFR0_U_VAL
  97         str             r1,   [r0]
  98
  99         ldr             r0,     =GAFR1_L
 100         ldr             r1,     =CFG_GAFR1_L_VAL
 101         str             r1,   [r0]
 102
 103         ldr             r0,     =GAFR1_U
 104         ldr             r1,     =CFG_GAFR1_U_VAL
 105         str             r1,   [r0]
 106
 107         ldr             r0,     =GAFR2_L
 108         ldr             r1,     =CFG_GAFR2_L_VAL
 109         str             r1,   [r0]
 110
 111         ldr             r0,     =GAFR2_U
 112         ldr             r1,     =CFG_GAFR2_U_VAL
 113         str             r1,   [r0]
 114
 115         ldr     r0,     =PSSR           /* enable GPIO pins */
 116         ldr             r1,     =CFG_PSSR_VAL
 117         str             r1,   [r0]
 118
 119 #ifdef DEBUG_BLINK_ENABLE
 120         /* 4th debug blink */
 121         bl      blink
 122 #endif
 123
 124         /* ---------------------------------------------------------------- */
 125         /* Enable memory interface                                          */
 126         /*                                                                  */
 127         /* The sequence below is based on the recommended init steps        */
 128         /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
 129         /* Chapter 10.                                                      */
 130         /* ---------------------------------------------------------------- */
 131
 132         /* ---------------------------------------------------------------- */
 133         /* Step 1: Wait for at least 200 microsedonds to allow internal     */
 134         /*         clocks to settle. Only necessary after hard reset...     */
 135         /*         FIXME: can be optimized later                            */
 136         /* ---------------------------------------------------------------- */
 137
 138         ldr r3, =OSCR                   /* reset the OS Timer Count to zero */
 139         mov r2, #0
 140         str r2, [r3]
 141         ldr r4, =0x300                  /* really 0x2E1 is about 200usec,   */
 142                                         /* so 0x300 should be plenty        */
 143 1:
 144         ldr r2, [r3]
 145         cmp r4, r2
 146         bgt 1b
 147
 148 mem_init:
 149
 150         ldr     r1,  =MEMC_BASE         /* get memory controller base addr. */
 151
 152         /* ---------------------------------------------------------------- */
 153         /* Step 2a: Initialize Asynchronous static memory controller        */
 154         /* ---------------------------------------------------------------- */
 155
 156         /* MSC registers: timing, bus width, mem type                       */
 157
 158         /* MSC0: nCS(0,1)                                                   */
 159         ldr     r2,   =CFG_MSC0_VAL
 160         str     r2,   [r1, #MSC0_OFFSET]
 161         ldr     r2,   [r1, #MSC0_OFFSET]        /* read back to ensure      */
 162                                                 /* that data latches        */
 163         /* MSC1: nCS(2,3)                                                   */
 164         ldr     r2,  =CFG_MSC1_VAL
 165         str     r2,  [r1, #MSC1_OFFSET]
 166         ldr     r2,  [r1, #MSC1_OFFSET]
 167
 168         /* MSC2: nCS(4,5)                                                   */
 169         ldr     r2,  =CFG_MSC2_VAL
 170         str     r2,  [r1, #MSC2_OFFSET]
 171         ldr     r2,  [r1, #MSC2_OFFSET]
 172
 173         /* ---------------------------------------------------------------- */
 174         /* Step 2b: Initialize Card Interface                               */
 175         /* ---------------------------------------------------------------- */
 176
 177         /* MECR: Memory Expansion Card Register                             */
 178         ldr     r2,  =CFG_MECR_VAL
 179         str     r2,  [r1, #MECR_OFFSET]
 180         ldr     r2,     [r1, #MECR_OFFSET]
 181
 182         /* MCMEM0: Card Interface slot 0 timing                             */
 183         ldr     r2,  =CFG_MCMEM0_VAL
 184         str     r2,  [r1, #MCMEM0_OFFSET]
 185         ldr     r2,     [r1, #MCMEM0_OFFSET]
 186
 187         /* MCMEM1: Card Interface slot 1 timing                             */
 188         ldr     r2,  =CFG_MCMEM1_VAL
 189         str     r2,  [r1, #MCMEM1_OFFSET]
 190         ldr     r2,     [r1, #MCMEM1_OFFSET]
 191
 192         /* MCATT0: Card Interface Attribute Space Timing, slot 0            */
 193         ldr     r2,  =CFG_MCATT0_VAL
 194         str     r2,  [r1, #MCATT0_OFFSET]
 195         ldr     r2,     [r1, #MCATT0_OFFSET]
 196
 197         /* MCATT1: Card Interface Attribute Space Timing, slot 1            */
 198         ldr     r2,  =CFG_MCATT1_VAL
 199         str     r2,  [r1, #MCATT1_OFFSET]
 200         ldr     r2,     [r1, #MCATT1_OFFSET]
 201
 202         /* MCIO0: Card Interface I/O Space Timing, slot 0                   */
 203         ldr     r2,  =CFG_MCIO0_VAL
 204         str     r2,  [r1, #MCIO0_OFFSET]
 205         ldr     r2,     [r1, #MCIO0_OFFSET]
 206
 207         /* MCIO1: Card Interface I/O Space Timing, slot 1                   */
 208         ldr     r2,  =CFG_MCIO1_VAL
 209         str     r2,  [r1, #MCIO1_OFFSET]
 210         ldr     r2,     [r1, #MCIO1_OFFSET]
 211
 212 #ifdef DEBUG_BLINK_ENABLE
 213         /* 5th blink */
 214         bl      blink
 215 #endif
 216
 217         /* ---------------------------------------------------------------- */
 218         /* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
 219         /* ---------------------------------------------------------------- */
 220
 221         /* ---------------------------------------------------------------- */
 222         /* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
 223         /* ---------------------------------------------------------------- */
 224
 225         /* Before accessing MDREFR we need a valid DRI field, so we set     */
 226         /* this to power on defaults + DRI field.                           */
 227
 228         ldr     r3,     =CFG_MDREFR_VAL
 229         ldr     r2,     =0xFFF
 230         and     r3,     r3,  r2
 231         ldr     r4,     =0x03ca4000
 232         orr     r4,     r4,  r3
 233         str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 234         ldr     r4,  [r1, #MDREFR_OFFSET]
 235
 236         /* Note: preserve the mdrefr value in r4                            */
 237
 238         /* ---------------------------------------------------------------- */
 239         /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
 240         /* ---------------------------------------------------------------- */
 241
 242         /* Initialize SXCNFG register. Assert the enable bits               */
 243
 244         /* Write SXMRS to cause an MRS command to all enabled banks of      */
 245         /* synchronous static memory. Note that SXLCR need not be written   */
 246         /* at this time.                                                    */
 247
 248         /* FIXME: we use async mode for now                                 */
 249
 250         /* ---------------------------------------------------------------- */
 251         /* Step 4: Initialize SDRAM                                         */
 252         /* ---------------------------------------------------------------- */
 253
 254         /* set MDREFR according to user define with exception of a few bits */
 255
 256         ldr     r4,     =CFG_MDREFR_VAL
 257         orr     r4,     r4,     #(MDREFR_SLFRSH)
 258         bic     r4,     r4,     #(MDREFR_E1PIN|MDREFR_E0PIN)
 259         str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 260         ldr     r4,  [r1, #MDREFR_OFFSET]
 261
 262         /* Step 4b: de-assert MDREFR:SLFRSH.                                */
 263
 264         bic     r4,     r4,     #(MDREFR_SLFRSH)
 265         str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 266         ldr     r4,  [r1, #MDREFR_OFFSET]
 267
 268         /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
 269
 270         ldr     r4,     =CFG_MDREFR_VAL
 271         str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 272         ldr     r4,     [r1, #MDREFR_OFFSET]
 273
 274
 275         /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 276         /*          configure but not enable each SDRAM partition pair.     */
 277
 278         ldr     r4,     =CFG_MDCNFG_VAL
 279         bic     r4,     r4,     #(MDCNFG_DE0|MDCNFG_DE1)
 280
 281         str     r4,     [r1, #MDCNFG_OFFSET]    /* write back MDCNFG        */
 282         ldr     r4,     [r1, #MDCNFG_OFFSET]
 283
 284         /* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
 285         /*          100..200 µsec.                                          */
 286
 287         ldr r3, =OSCR                   /* reset the OS Timer Count to zero */
 288         mov r2, #0
 289             str r2, [r3]
 290         ldr r4, =0x300                  /* really 0x2E1 is about 200usec,   */
 291                                         /* so 0x300 should be plenty        */
 292 1:
 293             ldr r2, [r3]
 294             cmp r4, r2
 295             bgt 1b
 296
 297         /* Step 4f: Trigger a number (usually 8) refresh cycles by          */
 298         /*          attempting non-burst read or write accesses to disabled */
 299         /*          SDRAM, as commonly specified in the power up sequence   */
 300         /*          documented in SDRAM data sheets. The address(es) used   */
 301         /*          for this purpose must not be cacheable.                 */
 302
 303         ldr     r3,     =CFG_DRAM_BASE
 304         str     r2,     [r3]
 305         str     r2,     [r3]
 306         str     r2,     [r3]
 307         str     r2,     [r3]
 308         str     r2,     [r3]
 309         str     r2,     [r3]
 310         str     r2,     [r3]
 311         str     r2,     [r3]
 312
 313         /* Step 4g: Write MDCNFG with enable bits asserted                  */
 314         /*          (MDCNFG:DEx set to 1).                                  */
 315
 316         ldr     r3,  [r1, #MDCNFG_OFFSET]
 317         orr     r3,     r3,     #(MDCNFG_DE0|MDCNFG_DE1)
 318         str     r3,  [r1, #MDCNFG_OFFSET]
 319
 320         /* Step 4h: Write MDMRS.                                            */
 321
 322         ldr     r2,  =CFG_MDMRS_VAL
 323         str     r2,  [r1, #MDMRS_OFFSET]
 324
 325         /* We are finished with Intel's memory controller initialisation    */
 326 #if 0
 327         /* FIXME turn on serial ports */
 328         /* look into moving this to board_init() */
 329         ldr     r2, =(PXA_CS5_PHYS + 0x03C0002c)
 330         mov     r3, #0x13
 331         str     r3, [r2]
 332 #endif
 333
 334 #ifdef DEBUG_BLINK_ENABLE
 335         /* 6th blink */
 336         bl      blink
 337 #endif
 338
 339         /* ---------------------------------------------------------------- */
 340         /* Disable (mask) all interrupts at interrupt controller            */
 341         /* ---------------------------------------------------------------- */
 342
 343 initirqs:
 344
 345         mov     r1, #0          /* clear int. level register (IRQ, not FIQ) */
 346         ldr     r2,  =ICLR
 347         str     r1,  [r2]
 348
 349         ldr     r2,  =ICMR      /* mask all interrupts at the controller    */
 350         str     r1,  [r2]
 351
 352         /* ---------------------------------------------------------------- */
 353         /* Clock initialisation                                             */
 354         /* ---------------------------------------------------------------- */
 355
 356 initclks:
 357
 358         /* Disable the peripheral clocks, and set the core clock frequency  */
 359         /* (hard-coding at 398.12MHz for now).                              */
 360
 361         /* Turn Off ALL on-chip peripheral clocks for re-configuration      */
 362         /* Note: See label 'ENABLECLKS' for the re-enabling                 */
 363 #if 0
 364         ldr     r1,  =CKEN
 365         mov     r2,  #0
 366         str     r2,  [r1]
 367
 368         /* default value in case no valid rotary switch setting is found    */
 369         ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
 370
 371         /* ... and write the core clock config register                     */
 372         ldr     r1,  =CCCR
 373         str     r2,  [r1]
 374
 375 #endif
 376
 377 #ifdef RTC
 378         /* enable the 32Khz oscillator for RTC and PowerManager             */
 379
 380         ldr     r1,  =OSCC
 381         mov     r2,  #OSCC_OON
 382         str     r2,  [r1]
 383
 384         /* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
 385         /* has settled.                                                     */
 386 60:
 387         ldr     r2, [r1]
 388         ands    r2, r2, #1
 389         beq     60b
 390 #endif
 391
 392         /* ---------------------------------------------------------------- */
 393         /*                                                                  */
 394         /* ---------------------------------------------------------------- */
 395
 396         /* Save SDRAM size */
 397         ldr     r1, =DRAM_SIZE
 398         str     r8, [r1]
 399
 400         /* Interrupt init: Mask all interrupts                              */
 401         ldr     r0, =ICMR /* enable no sources */
 402         mov r1, #0
 403         str r1, [r0]
 404
 405         /* FIXME */
 406
 407 #define NODEBUG
 408 #ifdef NODEBUG
 409         /*Disable software and data breakpoints */
 410         mov     r0,#0
 411         mcr     p15,0,r0,c14,c8,0  /* ibcr0 */
 412         mcr     p15,0,r0,c14,c9,0  /* ibcr1 */
 413         mcr     p15,0,r0,c14,c4,0  /* dbcon */
 414
 415         /*Enable all debug functionality */
 416         mov     r0,#0x80000000
 417         mcr     p14,0,r0,c10,c0,0  /* dcsr */
 418 #endif
 419
 420         /* ---------------------------------------------------------------- */
 421         /* End memsetup                                                     */
 422         /* ---------------------------------------------------------------- */
 423
 424 #ifdef DEBUG_BLINK_ENABLE
 425         /* 7th blink */
 426         bl      blink
 427 #endif
 428
 429 endlowlevel_init:
 430
 431         mov     pc, r10
 432
 433
 434 #ifdef DEBUG_BLINK_ENABLE
 435
 436 /* debug LED code */
 437
 438 /* delay about 200ms */
 439 delay:
 440
 441         /* reset OSCR to 0 */
 442         ldr     r8, =OSCR
 443         mov     r9, #0
 444         str     r9, [r8]
 445
 446         /* make sure new value has stuck */
 447 1:
 448         ldr     r8, =OSCR
 449         ldr     r9, [r8]
 450         mov     r8, #0x10000
 451         cmp     r9, r8
 452         bgt     1b
 453
 454         /* now, wait for delay to expire */
 455 1:
 456         ldr     r8, =OSCR
 457         ldr     r9, [r8]
 458         mov     r8, #0xd4000
 459         cmp     r8, r9
 460         bgt     1b
 461
 462         mov     pc, lr
 463
 464 /* blink code -- trashes r7, r8, r9 */
 465
 466 .globl blink
 467 blink:
 468
 469         mov     r7, lr
 470
 471         /* set GPIO10 as outout */
 472         ldr     r8,  =GPDR0
 473         ldr     r9,  [r8]
 474         orr     r9,  r9, #(1<<10)
 475         str     r9,  [r8]
 476
 477         /* turn LED off */
 478         mov     r9,  #(1<<10)
 479         ldr     r8,  =GPCR0
 480         str     r9, [r8]
 481         bl      delay
 482
 483         /* turn LED on */
 484         mov     r9,  #(1<<10)
 485         ldr     r8,  =GPSR0
 486         str     r9, [r8]
 487         bl      delay
 488
 489         /* turn LED off */
 490         mov     r9,  #(1<<10)
 491         ldr     r8,  =GPCR0
 492         str     r9, [r8]
 493
 494         mov     pc, r7
 495
 496 #endif