board/renesas/ap325rxa/ap325rxa.c

   1 /*
   2  * Copyright (C) 2008 Renesas Solutions Corp.
   3  * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <netdev.h>
  10 #include <asm/io.h>
  11 #include <asm/processor.h>
  12
  13 /* PRI control register */
  14 #define PRPRICR5        0xFF800048 /* LMB */
  15 #define PRPRICR5_D      0x2a
  16
  17 /* FPGA control */
  18 #define FPGA_NAND_CTL   0xB410020C
  19 #define FPGA_NAND_RST   0x0008
  20 #define FPGA_NAND_INIT  0x0000
  21 #define FPGA_NAND_RST_WAIT      10000
  22
  23 /* I/O port data */
  24 #define PACR_D  0x0000
  25 #define PBCR_D  0x0000
  26 #define PCCR_D  0x1000
  27 #define PDCR_D  0x0000
  28 #define PECR_D  0x0410
  29 #define PFCR_D  0xffff
  30 #define PGCR_D  0x0000
  31 #define PHCR_D  0x5011
  32 #define PJCR_D  0x4400
  33 #define PKCR_D  0x7c00
  34 #define PLCR_D  0x0000
  35 #define PMCR_D  0x0000
  36 #define PNCR_D  0x0000
  37 #define PQCR_D  0x0000
  38 #define PRCR_D  0x0000
  39 #define PSCR_D  0x0000
  40 #define PTCR_D  0x0010
  41 #define PUCR_D  0x0fff
  42 #define PVCR_D  0xffff
  43 #define PWCR_D  0x0000
  44 #define PXCR_D  0x7500
  45 #define PYCR_D  0x0000
  46 #define PZCR_D  0x5540
  47
  48 /* Pin Function Controler data */
  49 #define PSELA_D 0x1410
  50 #define PSELB_D 0x0140
  51 #define PSELC_D 0x0000
  52 #define PSELD_D 0x0400
  53
  54 /* I/O Buffer Hi-Z data */
  55 #define HIZCRA_D        0x0000
  56 #define HIZCRB_D        0x1000
  57 #define HIZCRC_D        0x0000
  58 #define HIZCRD_D        0x0000
  59
  60 /* Module select reg data */
  61 #define MSELCRA_D       0x0014
  62 #define MSELCRB_D       0x0018
  63
  64 /* Module Stop reg Data */
  65 #define MSTPCR2_D       0xFFD9F280
  66
  67 /* CPLD loader */
  68 extern void init_cpld(void);
  69
  70 int checkboard(void)
  71 {
  72         puts("BOARD: AP325RXA\n");
  73         return 0;
  74 }
  75
  76 int board_init(void)
  77 {
  78         /* Pin Function Controler Init */
  79         outw(PSELA_D, PSELA);
  80         outw(PSELB_D, PSELB);
  81         outw(PSELC_D, PSELC);
  82         outw(PSELD_D, PSELD);
  83
  84         /* I/O Buffer Hi-Z Init */
  85         outw(HIZCRA_D, HIZCRA);
  86         outw(HIZCRB_D, HIZCRB);
  87         outw(HIZCRC_D, HIZCRC);
  88         outw(HIZCRD_D, HIZCRD);
  89
  90         /* Module select reg Init */
  91         outw(MSELCRA_D, MSELCRA);
  92         outw(MSELCRB_D, MSELCRB);
  93
  94         /* Module Stop reg Init */
  95         outl(MSTPCR2_D, MSTPCR2);
  96
  97         /* I/O ports */
  98         outw(PACR_D, PACR);
  99         outw(PBCR_D, PBCR);
 100         outw(PCCR_D, PCCR);
 101         outw(PDCR_D, PDCR);
 102         outw(PECR_D, PECR);
 103         outw(PFCR_D, PFCR);
 104         outw(PGCR_D, PGCR);
 105         outw(PHCR_D, PHCR);
 106         outw(PJCR_D, PJCR);
 107         outw(PKCR_D, PKCR);
 108         outw(PLCR_D, PLCR);
 109         outw(PMCR_D, PMCR);
 110         outw(PNCR_D, PNCR);
 111         outw(PQCR_D, PQCR);
 112         outw(PRCR_D, PRCR);
 113         outw(PSCR_D, PSCR);
 114         outw(PTCR_D, PTCR);
 115         outw(PUCR_D, PUCR);
 116         outw(PVCR_D, PVCR);
 117         outw(PWCR_D, PWCR);
 118         outw(PXCR_D, PXCR);
 119         outw(PYCR_D, PYCR);
 120         outw(PZCR_D, PZCR);
 121
 122         /* PRI control register Init */
 123         outl(PRPRICR5_D, PRPRICR5);
 124
 125         /* cpld init */
 126         init_cpld();
 127
 128         return 0;
 129 }
 130
 131 void led_set_state(unsigned short value)
 132 {
 133 }
 134
 135 void ide_set_reset(int idereset)
 136 {
 137         outw(FPGA_NAND_RST, FPGA_NAND_CTL);     /* NAND RESET */
 138         udelay(FPGA_NAND_RST_WAIT);
 139         outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
 140 }
 141
 142 int board_eth_init(bd_t *bis)
 143 {
 144         int rc = 0;
 145 #ifdef CONFIG_SMC911X
 146         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 147 #endif
 148         return rc;
 149 }