board/renesas/porter/porter.c

   1 /*
   2  * board/renesas/porter/porter.c
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corporation
   5  * Copyright (C) 2015 Cogent Embedded, Inc.
   6  *
   7  * SPDX-License-Identifier: GPL-2.0
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <dm.h>
  13 #include <dm/platform_data/serial_sh.h>
  14 #include <asm/processor.h>
  15 #include <asm/mach-types.h>
  16 #include <asm/io.h>
  17 #include <asm/errno.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/gpio.h>
  20 #include <asm/arch/rmobile.h>
  21 #include <asm/arch/rcar-mstp.h>
  22 #include <asm/arch/sh_sdhi.h>
  23 #include <netdev.h>
  24 #include <miiphy.h>
  25 #include <i2c.h>
  26 #include <div64.h>
  27 #include "qos.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define CLK2MHZ(clk)    (clk / 1000 / 1000)
  32 void s_init(void)
  33 {
  34         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  35         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  36         u32 stc;
  37
  38         /* Watchdog init */
  39         writel(0xA5A5A500, &rwdt->rwtcsra);
  40         writel(0xA5A5A500, &swdt->swtcsra);
  41
  42         /* CPU frequency setting. Set to 1.5GHz */
  43         stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
  44         clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  45
  46         /* QoS */
  47         qos_init();
  48 }
  49
  50 #define TMU0_MSTP125    (1 << 25)
  51 #define SDHI0_MSTP314   (1 << 14)
  52 #define SDHI2_MSTP311   (1 << 11)
  53 #define SCIF0_MSTP721   (1 << 21)
  54 #define ETHER_MSTP813   (1 << 13)
  55
  56 #define SD2CKCR         0xE615026C
  57 #define SD_97500KHZ     0x7
  58
  59 int board_early_init_f(void)
  60 {
  61         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  62
  63         /* SCIF0 */
  64         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
  65
  66         /* ETHER */
  67         mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
  68
  69         /* SDHI  */
  70         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP311);
  71
  72         /*
  73          * SD0 clock is set to 97.5MHz by default.
  74          * Set SD2 to the 97.5MHz as well.
  75          */
  76         writel(SD_97500KHZ, SD2CKCR);
  77
  78         return 0;
  79 }
  80
  81 /* LSI pin pull-up control */
  82 #define PUPR5           0xe6060114
  83 #define PUPR5_ETH       0x3FFC0000
  84 #define PUPR5_ETH_MAGIC (1 << 27)
  85 int board_init(void)
  86 {
  87         /* adress of boot parameters */
  88         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  89
  90         /* Init PFC controller */
  91         r8a7791_pinmux_init();
  92
  93         /* Ether Enable */
  94         gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
  95         gpio_request(GPIO_FN_ETH_RX_ER, NULL);
  96         gpio_request(GPIO_FN_ETH_RXD0, NULL);
  97         gpio_request(GPIO_FN_ETH_RXD1, NULL);
  98         gpio_request(GPIO_FN_ETH_LINK, NULL);
  99         gpio_request(GPIO_FN_ETH_REFCLK, NULL);
 100         gpio_request(GPIO_FN_ETH_MDIO, NULL);
 101         gpio_request(GPIO_FN_ETH_TXD1, NULL);
 102         gpio_request(GPIO_FN_ETH_TX_EN, NULL);
 103         gpio_request(GPIO_FN_ETH_TXD0, NULL);
 104         gpio_request(GPIO_FN_ETH_MDC, NULL);
 105         gpio_request(GPIO_FN_IRQ0, NULL);
 106
 107         mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
 108         gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
 109         mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
 110
 111         gpio_direction_output(GPIO_GP_5_22, 0);
 112         mdelay(20);
 113         gpio_set_value(GPIO_GP_5_22, 1);
 114         udelay(1);
 115
 116         return 0;
 117 }
 118
 119 #define CXR24 0xEE7003C0 /* MAC address high register */
 120 #define CXR25 0xEE7003C8 /* MAC address low register */
 121 int board_eth_init(bd_t *bis)
 122 {
 123 #ifdef CONFIG_SH_ETHER
 124         int ret = -ENODEV;
 125         u32 val;
 126         unsigned char enetaddr[6];
 127
 128         ret = sh_eth_initialize(bis);
 129         if (!eth_getenv_enetaddr("ethaddr", enetaddr))
 130                 return ret;
 131
 132         /* Set Mac address */
 133         val = enetaddr[0] << 24 | enetaddr[1] << 16 |
 134                 enetaddr[2] << 8 | enetaddr[3];
 135         writel(val, CXR24);
 136
 137         val = enetaddr[4] << 8 | enetaddr[5];
 138         writel(val, CXR25);
 139
 140         return ret;
 141 #else
 142         return 0;
 143 #endif
 144 }
 145
 146 int board_mmc_init(bd_t *bis)
 147 {
 148         int ret = -ENODEV;
 149
 150 #ifdef CONFIG_SH_SDHI
 151         gpio_request(GPIO_FN_SD0_DATA0, NULL);
 152         gpio_request(GPIO_FN_SD0_DATA1, NULL);
 153         gpio_request(GPIO_FN_SD0_DATA2, NULL);
 154         gpio_request(GPIO_FN_SD0_DATA3, NULL);
 155         gpio_request(GPIO_FN_SD0_CLK, NULL);
 156         gpio_request(GPIO_FN_SD0_CMD, NULL);
 157         gpio_request(GPIO_FN_SD0_CD, NULL);
 158         gpio_request(GPIO_FN_SD2_DATA0, NULL);
 159         gpio_request(GPIO_FN_SD2_DATA1, NULL);
 160         gpio_request(GPIO_FN_SD2_DATA2, NULL);
 161         gpio_request(GPIO_FN_SD2_DATA3, NULL);
 162         gpio_request(GPIO_FN_SD2_CLK, NULL);
 163         gpio_request(GPIO_FN_SD2_CMD, NULL);
 164         gpio_request(GPIO_FN_SD2_CD, NULL);
 165
 166         /* SDHI 0 */
 167         gpio_request(GPIO_GP_2_12, NULL);
 168         gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */
 169
 170         ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
 171                            SH_SDHI_QUIRK_16BIT_BUF);
 172         if (ret)
 173                 return ret;
 174
 175         /* SDHI 2 */
 176         gpio_request(GPIO_GP_2_26, NULL);
 177         gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */
 178
 179         ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0);
 180 #endif
 181         return ret;
 182 }
 183
 184 int dram_init(void)
 185 {
 186         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 187
 188         return 0;
 189 }
 190
 191 /* porter has KSZ8041RNLI */
 192 #define PHY_CONTROL1            0x1E
 193 #define PHY_LED_MODE            0xC0000
 194 #define PHY_LED_MODE_ACK        0x4000
 195 int board_phy_config(struct phy_device *phydev)
 196 {
 197         int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
 198         ret &= ~PHY_LED_MODE;
 199         ret |= PHY_LED_MODE_ACK;
 200         ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
 201
 202         return 0;
 203 }
 204
 205 const struct rmobile_sysinfo sysinfo = {
 206         CONFIG_RMOBILE_BOARD_STRING
 207 };
 208
 209 void reset_cpu(ulong addr)
 210 {
 211         u8 val;
 212
 213         i2c_set_bus_num(2); /* PowerIC connected to ch2 */
 214         i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 215         val |= 0x02;
 216         i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 217 }
 218
 219 static const struct sh_serial_platdata serial_platdata = {
 220         .base = SCIF0_BASE,
 221         .type = PORT_SCIF,
 222         .clk = CONFIG_P_CLK_FREQ,
 223 };
 224
 225 U_BOOT_DEVICE(porter_serials) = {
 226         .name = "serial_sh",
 227         .platdata = &serial_platdata,
 228 };