board/renesas/rsk7203/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2008 Nobuhiro Iwamatsu
   3  * Copyright (C) 2008 Renesas Solutions Corp.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20 #include <config.h>
  21 #include <version.h>
  22
  23 #include <asm/processor.h>
  24
  25         .global lowlevel_init
  26
  27         .text
  28         .align  2
  29
  30 lowlevel_init:
  31         /* Cache setting */
  32         mov.l CCR1_A ,r1
  33         mov.l CCR1_D ,r0
  34         mov.l r0,@r1
  35
  36         /* ConfigurePortPins */
  37         mov.l PECRL3_A, r1
  38         mov.l PECRL3_D, r0
  39         mov.w r0,@r1
  40
  41         mov.l PCCRL4_A, r1
  42         mov.l PCCRL4_D0, r0
  43         mov.w r0,@r1
  44
  45         mov.l PECRL4_A, r1
  46         mov.l PECRL4_D0, r0
  47         mov.w r0,@r1
  48
  49         mov.l PEIORL_A, r1
  50         mov.l PEIORL_D0, r0
  51         mov.w r0,@r1
  52
  53         mov.l PCIORL_A, r1
  54         mov.l PCIORL_D, r0
  55         mov.w r0,@r1
  56
  57         mov.l PFCRH2_A, r1
  58         mov.l PFCRH2_D, r0
  59         mov.w r0,@r1
  60
  61         mov.l PFCRH3_A, r1
  62         mov.l PFCRH3_D, r0
  63         mov.w r0,@r1
  64
  65         mov.l PFCRH1_A, r1
  66         mov.l PFCRH1_D, r0
  67         mov.w r0,@r1
  68
  69         mov.l PFIORH_A, r1
  70         mov.l PFIORH_D, r0
  71         mov.w r0,@r1
  72
  73         mov.l PECRL1_A, r1
  74         mov.l PECRL1_D0, r0
  75         mov.w r0,@r1
  76
  77         mov.l PEIORL_A, r1
  78         mov.l PEIORL_D1, r0
  79         mov.w r0,@r1
  80
  81         /* Configure Operating Frequency */
  82         mov.l WTCSR_A ,r1
  83         mov.l WTCSR_D0 ,r0
  84         mov.w r0,@r1
  85
  86         mov.l WTCSR_A ,r1
  87         mov.l WTCSR_D1 ,r0
  88         mov.w r0,@r1
  89
  90         mov.l WTCNT_A ,r1
  91         mov.l WTCNT_D ,r0
  92         mov.w r0,@r1
  93
  94         /* Set clock mode*/
  95         mov.l FRQCR_A,r1
  96         mov.l FRQCR_D,r0
  97         mov.w r0,@r1
  98
  99         /* Configure Bus And Memory */
 100 init_bsc_cs0:
 101         mov.l   PCCRL4_A,r1
 102         mov.l   PCCRL4_D1,r0
 103         mov.w   r0,@r1
 104
 105         mov.l   PECRL1_A,r1
 106         mov.l   PECRL1_D1,r0
 107         mov.w   r0,@r1
 108
 109         mov.l CMNCR_A,r1
 110         mov.l CMNCR_D,r0
 111         mov.l r0,@r1
 112
 113         mov.l SC0BCR_A,r1
 114         mov.l SC0BCR_D,r0
 115         mov.l r0,@r1
 116
 117         mov.l CS0WCR_A,r1
 118         mov.l CS0WCR_D,r0
 119         mov.l r0,@r1
 120
 121 init_bsc_cs1:
 122         mov.l   PECRL4_A,r1
 123         mov.l   PECRL4_D1,r0
 124         mov.w   r0,@r1
 125
 126         mov.l CS1WCR_A,r1
 127         mov.l CS1WCR_D,r0
 128         mov.l r0,@r1
 129
 130 init_sdram:
 131         mov.l   PCCRL2_A,r1
 132         mov.l   PCCRL2_D,r0
 133         mov.w   r0,@r1
 134
 135         mov.l   PCCRL4_A,r1
 136         mov.l   PCCRL4_D2,r0
 137         mov.w   r0,@r1
 138
 139         mov.l   PCCRL1_A,r1
 140         mov.l   PCCRL1_D,r0
 141         mov.w   r0,@r1
 142
 143         mov.l   PCCRL3_A,r1
 144         mov.l   PCCRL3_D,r0
 145         mov.w   r0,@r1
 146
 147         mov.l CS3BCR_A,r1
 148         mov.l CS3BCR_D,r0
 149         mov.l r0,@r1
 150
 151         mov.l CS3WCR_A,r1
 152         mov.l CS3WCR_D,r0
 153         mov.l r0,@r1
 154
 155         mov.l SDCR_A,r1
 156         mov.l SDCR_D,r0
 157         mov.l r0,@r1
 158
 159         mov.l RTCOR_A,r1
 160         mov.l RTCOR_D,r0
 161         mov.l r0,@r1
 162
 163         mov.l RTCSR_A,r1
 164         mov.l RTCSR_D,r0
 165         mov.l r0,@r1
 166
 167         /* wait 200us */
 168         mov.l   REPEAT_D,r3
 169         mov     #0,r2
 170 repeat0:
 171         add     #1,r2
 172         cmp/hs  r3,r2
 173         bf      repeat0
 174         nop
 175
 176         mov.l SDRAM_MODE, r1
 177         mov   #0,r0
 178         mov.l r0, @r1
 179
 180         nop
 181         rts
 182
 183         .align 4
 184
 185 CCR1_A:         .long CCR1
 186 CCR1_D:         .long 0x0000090B
 187 PCCRL4_A:       .long 0xFFFE3910
 188 PCCRL4_D0:      .long 0x00000000
 189 PECRL4_A:       .long 0xFFFE3A10
 190 PECRL4_D0:      .long 0x00000000
 191 PECRL3_A:       .long 0xFFFE3A12
 192 PECRL3_D:       .long 0x00000000
 193 PEIORL_A:       .long 0xFFFE3A06
 194 PEIORL_D0:      .long 0x00001C00
 195 PEIORL_D1:      .long 0x00001C02
 196 PCIORL_A:       .long 0xFFFE3906
 197 PCIORL_D:       .long 0x00004000
 198 PFCRH2_A:       .long 0xFFFE3A8C
 199 PFCRH2_D:       .long 0x00000000
 200 PFCRH3_A:       .long 0xFFFE3A8A
 201 PFCRH3_D:       .long 0x00000000
 202 PFCRH1_A:       .long 0xFFFE3A8E
 203 PFCRH1_D:       .long 0x00000000
 204 PFIORH_A:       .long 0xFFFE3A84
 205 PFIORH_D:       .long 0x00000729
 206 PECRL1_A:       .long 0xFFFE3A16
 207 PECRL1_D0:      .long 0x00000033
 208
 209
 210 WTCSR_A:        .long 0xFFFE0000
 211 WTCSR_D0:       .long 0x0000A518
 212 WTCSR_D1:       .long 0x0000A51D
 213 WTCNT_A:        .long 0xFFFE0002
 214 WTCNT_D:        .long 0x00005A84
 215 FRQCR_A:        .long 0xFFFE0010
 216 FRQCR_D:        .long 0x00000104
 217
 218 PCCRL4_D1:      .long 0x00000010
 219 PECRL1_D1:      .long 0x00000133
 220
 221 CMNCR_A:        .long 0xFFFC0000
 222 CMNCR_D:        .long 0x00001810
 223 SC0BCR_A:       .long 0xFFFC0004
 224 SC0BCR_D:       .long 0x10000400
 225 CS0WCR_A:       .long 0xFFFC0028
 226 CS0WCR_D:       .long 0x00000B41
 227 PECRL4_D1:      .long 0x00000100
 228 CS1WCR_A:       .long 0xFFFC002C
 229 CS1WCR_D:       .long 0x00000B01
 230 PCCRL4_D2:      .long 0x00000011
 231 PCCRL3_A:       .long 0xFFFE3912
 232 PCCRL3_D:       .long 0x00000011
 233 PCCRL2_A:       .long 0xFFFE3914
 234 PCCRL2_D:       .long 0x00001111
 235 PCCRL1_A:       .long 0xFFFE3916
 236 PCCRL1_D:       .long 0x00001010
 237 PDCRL4_A:       .long 0xFFFE3990
 238 PDCRL4_D:       .long 0x00000011
 239 PDCRL3_A:       .long 0xFFFE3992
 240 PDCRL3_D:       .long 0x00000011
 241 PDCRL2_A:       .long 0xFFFE3994
 242 PDCRL2_D:       .long 0x00001111
 243 PDCRL1_A:       .long 0xFFFE3996
 244 PDCRL1_D:       .long 0x00001000
 245 CS3BCR_A:       .long 0xFFFC0010
 246 CS3BCR_D:       .long 0x00004400
 247 CS3WCR_A:       .long 0xFFFC0034
 248 CS3WCR_D:       .long 0x00002892
 249 SDCR_A:         .long 0xFFFC004C
 250 SDCR_D:         .long 0x00000809
 251 RTCOR_A:        .long 0xFFFC0058
 252 RTCOR_D:        .long 0xA55A0041
 253 RTCSR_A:        .long 0xFFFC0050
 254 RTCSR_D:        .long 0xa55a0010
 255
 256 STBCR3_A:       .long 0xFFFE0408
 257 STBCR3_D:       .long 0x00000000
 258 STBCR4_A:       .long 0xFFFE040C
 259 STBCR4_D:       .long 0x00000008
 260 STBCR5_A:       .long 0xFFFE0410
 261 STBCR5_D:       .long 0x00000000
 262 STBCR6_A:       .long 0xFFFE0414
 263 STBCR6_D:       .long 0x00000002
 264 SDRAM_MODE:     .long 0xFFFC5040
 265 REPEAT_D:       .long 0x00009C40