board/renesas/salvator-x/salvator-x.c

   1 /*
   2  * board/renesas/salvator-x/salvator-x.c
   3  *     This file is Salvator-X/Salvator-XS board support.
   4  *
   5  * Copyright (C) 2015-2017 Renesas Electronics Corporation
   6  * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
   7  *
   8  * SPDX-License-Identifier: GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <malloc.h>
  13 #include <netdev.h>
  14 #include <dm.h>
  15 #include <dm/platform_data/serial_sh.h>
  16 #include <asm/processor.h>
  17 #include <asm/mach-types.h>
  18 #include <asm/io.h>
  19 #include <linux/errno.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/rmobile.h>
  24 #include <asm/arch/rcar-mstp.h>
  25 #include <asm/arch/sh_sdhi.h>
  26 #include <i2c.h>
  27 #include <mmc.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define CPGWPCR 0xE6150904
  32 #define CPGWPR  0xE615090C
  33
  34 #define CLK2MHZ(clk)    (clk / 1000 / 1000)
  35 void s_init(void)
  36 {
  37         struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  38         struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  39
  40         /* Watchdog init */
  41         writel(0xA5A5A500, &rwdt->rwtcsra);
  42         writel(0xA5A5A500, &swdt->swtcsra);
  43
  44         writel(0xA5A50000, CPGWPCR);
  45         writel(0xFFFFFFFF, CPGWPR);
  46 }
  47
  48 #define GSX_MSTP112             BIT(12) /* 3DG */
  49 #define TMU0_MSTP125            BIT(25) /* secure */
  50 #define TMU1_MSTP124            BIT(24) /* non-secure */
  51 #define SCIF2_MSTP310           BIT(10) /* SCIF2 */
  52 #define ETHERAVB_MSTP812        BIT(12)
  53 #define DVFS_MSTP926            BIT(26)
  54 #define SD0_MSTP314             BIT(14)
  55 #define SD1_MSTP313             BIT(13)
  56 #define SD2_MSTP312             BIT(12) /* either MMC0 */
  57 #define SD3_MSTP311             BIT(11) /* either MMC1 */
  58
  59 #define SD0CKCR                 0xE6150074
  60 #define SD1CKCR                 0xE6150078
  61 #define SD2CKCR                 0xE6150268
  62 #define SD3CKCR                 0xE615026C
  63
  64 int board_early_init_f(void)
  65 {
  66         /* TMU0,1 */            /* which use ? */
  67         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
  68         /* SCIF2 */
  69         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
  70         /* EHTERAVB */
  71         mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
  72         /* eMMC */
  73         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
  74         /* SDHI0, 3 */
  75         mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
  76
  77         writel(0, SD0CKCR);
  78         writel(0, SD1CKCR);
  79         writel(0, SD2CKCR);
  80         writel(0, SD3CKCR);
  81
  82 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
  83         /* DVFS for reset */
  84         mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
  85 #endif
  86         return 0;
  87 }
  88
  89 /* SYSC */
  90 /* R/- 32 Power status register 2(3DG) */
  91 #define SYSC_PWRSR2     0xE6180100
  92 /* -/W 32 Power resume control register 2 (3DG) */
  93 #define SYSC_PWRONCR2   0xE618010C
  94
  95 int board_init(void)
  96 {
  97         /* adress of boot parameters */
  98         gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
  99
 100         /* Init PFC controller */
 101 #if defined(CONFIG_R8A7795)
 102         r8a7795_pinmux_init();
 103 #elif defined(CONFIG_R8A7796)
 104         r8a7796_pinmux_init();
 105 #endif
 106
 107 #if defined(CONFIG_R8A7795)
 108         /* GSX: force power and clock supply */
 109         writel(0x0000001F, SYSC_PWRONCR2);
 110         while (readl(SYSC_PWRSR2) != 0x000003E0)
 111                 mdelay(20);
 112
 113         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
 114 #endif
 115
 116         /* USB1 pull-up */
 117         setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 118
 119 #ifdef CONFIG_RAVB
 120         /* EtherAVB Enable */
 121         /* GPSR2 */
 122         gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
 123         gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
 124         gpio_request(GPIO_GFN_AVB_LINK, NULL);
 125         gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
 126         gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
 127         gpio_request(GPIO_GFN_AVB_MDC, NULL);
 128
 129         /* IPSR0 */
 130         gpio_request(GPIO_IFN_AVB_MDC, NULL);
 131         gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
 132         gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
 133         gpio_request(GPIO_IFN_AVB_LINK, NULL);
 134         gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
 135         gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
 136         /* IPSR1 */
 137         gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
 138         /* IPSR2 */
 139         gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
 140         /* IPSR3 */
 141         gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
 142
 143 #if defined(CONFIG_R8A7795)
 144         /* USB2_OVC */
 145         gpio_request(GPIO_GP_6_15, NULL);
 146         gpio_direction_input(GPIO_GP_6_15);
 147
 148         /* USB2_PWEN */
 149         gpio_request(GPIO_GP_6_14, NULL);
 150         gpio_direction_output(GPIO_GP_6_14, 1);
 151         gpio_set_value(GPIO_GP_6_14, 1);
 152 #endif
 153         /* AVB_PHY_RST */
 154         gpio_request(GPIO_GP_2_10, NULL);
 155         gpio_direction_output(GPIO_GP_2_10, 0);
 156         mdelay(20);
 157         gpio_set_value(GPIO_GP_2_10, 1);
 158         udelay(1);
 159 #endif
 160
 161         return 0;
 162 }
 163
 164 static struct eth_pdata salvator_x_ravb_platdata = {
 165         .iobase         = 0xE6800000,
 166         .phy_interface  = 0,
 167         .max_speed      = 1000,
 168 };
 169
 170 U_BOOT_DEVICE(salvator_x_ravb) = {
 171         .name           = "ravb",
 172         .platdata       = &salvator_x_ravb_platdata,
 173 };
 174
 175 #ifdef CONFIG_SH_SDHI
 176 int board_mmc_init(bd_t *bis)
 177 {
 178         int ret = -ENODEV;
 179
 180         /* SDHI0 */
 181         gpio_request(GPIO_GFN_SD0_DAT0, NULL);
 182         gpio_request(GPIO_GFN_SD0_DAT1, NULL);
 183         gpio_request(GPIO_GFN_SD0_DAT2, NULL);
 184         gpio_request(GPIO_GFN_SD0_DAT3, NULL);
 185         gpio_request(GPIO_GFN_SD0_CLK, NULL);
 186         gpio_request(GPIO_GFN_SD0_CMD, NULL);
 187         gpio_request(GPIO_GFN_SD0_CD, NULL);
 188         gpio_request(GPIO_GFN_SD0_WP, NULL);
 189
 190         gpio_request(GPIO_GP_5_2, NULL);
 191         gpio_request(GPIO_GP_5_1, NULL);
 192         gpio_direction_output(GPIO_GP_5_2, 1);  /* power on */
 193         gpio_direction_output(GPIO_GP_5_1, 1);  /* 1: 3.3V, 0: 1.8V */
 194
 195         ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
 196                            SH_SDHI_QUIRK_64BIT_BUF);
 197         if (ret)
 198                 return ret;
 199
 200         /* SDHI1/SDHI2 eMMC */
 201         gpio_request(GPIO_GFN_SD1_DAT0, NULL);
 202         gpio_request(GPIO_GFN_SD1_DAT1, NULL);
 203         gpio_request(GPIO_GFN_SD1_DAT2, NULL);
 204         gpio_request(GPIO_GFN_SD1_DAT3, NULL);
 205         gpio_request(GPIO_GFN_SD2_DAT0, NULL);
 206         gpio_request(GPIO_GFN_SD2_DAT1, NULL);
 207         gpio_request(GPIO_GFN_SD2_DAT2, NULL);
 208         gpio_request(GPIO_GFN_SD2_DAT3, NULL);
 209         gpio_request(GPIO_GFN_SD2_CLK, NULL);
 210 #if defined(CONFIG_R8A7795)
 211         gpio_request(GPIO_GFN_SD2_CMD, NULL);
 212 #elif defined(CONFIG_R8A7796)
 213         gpio_request(GPIO_FN_SD2_CMD, NULL);
 214 #else
 215 #error Only R8A7795 and R87796 is supported
 216 #endif
 217         gpio_request(GPIO_GP_5_3, NULL);
 218         gpio_request(GPIO_GP_5_9, NULL);
 219         gpio_direction_output(GPIO_GP_5_3, 0);  /* 1: 3.3V, 0: 1.8V */
 220         gpio_direction_output(GPIO_GP_5_9, 0);  /* 1: 3.3V, 0: 1.8V */
 221
 222         ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
 223                            SH_SDHI_QUIRK_64BIT_BUF);
 224         if (ret)
 225                 return ret;
 226
 227 #if defined(CONFIG_R8A7795)
 228         /* SDHI3 */
 229         gpio_request(GPIO_GFN_SD3_DAT0, NULL);  /* GP_4_9 */
 230         gpio_request(GPIO_GFN_SD3_DAT1, NULL);  /* GP_4_10 */
 231         gpio_request(GPIO_GFN_SD3_DAT2, NULL);  /* GP_4_11 */
 232         gpio_request(GPIO_GFN_SD3_DAT3, NULL);  /* GP_4_12 */
 233         gpio_request(GPIO_GFN_SD3_CLK, NULL);   /* GP_4_7 */
 234         gpio_request(GPIO_GFN_SD3_CMD, NULL);   /* GP_4_8 */
 235 #elif defined(CONFIG_R8A7796)
 236         gpio_request(GPIO_FN_SD3_DAT0, NULL);   /* GP_4_9 */
 237         gpio_request(GPIO_FN_SD3_DAT1, NULL);   /* GP_4_10 */
 238         gpio_request(GPIO_FN_SD3_DAT2, NULL);   /* GP_4_11 */
 239         gpio_request(GPIO_FN_SD3_DAT3, NULL);   /* GP_4_12 */
 240         gpio_request(GPIO_FN_SD3_CLK, NULL);    /* GP_4_7 */
 241         gpio_request(GPIO_FN_SD3_CMD, NULL);    /* GP_4_8 */
 242 #else
 243 #error Only R8A7795 and R87796 is supported
 244 #endif
 245         /* IPSR10 */
 246         gpio_request(GPIO_FN_SD3_CD, NULL);
 247         gpio_request(GPIO_FN_SD3_WP, NULL);
 248
 249         gpio_request(GPIO_GP_3_15, NULL);
 250         gpio_request(GPIO_GP_3_14, NULL);
 251         gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
 252         gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
 253
 254         ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
 255                            SH_SDHI_QUIRK_64BIT_BUF);
 256         return ret;
 257 }
 258 #endif
 259
 260 int dram_init(void)
 261 {
 262         gd->ram_size = PHYS_SDRAM_1_SIZE;
 263 #if (CONFIG_NR_DRAM_BANKS >= 2)
 264         gd->ram_size += PHYS_SDRAM_2_SIZE;
 265 #endif
 266 #if (CONFIG_NR_DRAM_BANKS >= 3)
 267         gd->ram_size += PHYS_SDRAM_3_SIZE;
 268 #endif
 269 #if (CONFIG_NR_DRAM_BANKS >= 4)
 270         gd->ram_size += PHYS_SDRAM_4_SIZE;
 271 #endif
 272
 273         return 0;
 274 }
 275
 276 int dram_init_banksize(void)
 277 {
 278         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 279         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 280 #if (CONFIG_NR_DRAM_BANKS >= 2)
 281         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 282         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 283 #endif
 284 #if (CONFIG_NR_DRAM_BANKS >= 3)
 285         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 286         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
 287 #endif
 288 #if (CONFIG_NR_DRAM_BANKS >= 4)
 289         gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 290         gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
 291 #endif
 292         return 0;
 293 }
 294
 295 const struct rmobile_sysinfo sysinfo = {
 296         CONFIG_RCAR_BOARD_STRING
 297 };
 298
 299 #define RST_BASE        0xE6160000
 300 #define RST_CA57RESCNT  (RST_BASE + 0x40)
 301 #define RST_CA53RESCNT  (RST_BASE + 0x44)
 302 #define RST_RSTOUTCR    (RST_BASE + 0x58)
 303 #define RST_CODE        0xA5A5000F
 304
 305 void reset_cpu(ulong addr)
 306 {
 307 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
 308         i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
 309 #else
 310         /* only CA57 ? */
 311         writel(RST_CODE, RST_CA57RESCNT);
 312 #endif
 313 }
 314
 315 static const struct sh_serial_platdata serial_platdata = {
 316         .base = SCIF2_BASE,
 317         .type = PORT_SCIF,
 318         .clk = CONFIG_SH_SCIF_CLK_FREQ,
 319         .clk_mode = INT_CLK,
 320 };
 321
 322 U_BOOT_DEVICE(salvator_x_scif2) = {
 323         .name = "serial_sh",
 324         .platdata = &serial_platdata,
 325 };