board/renesas/sh7752evb/sh7752evb.c

   1 /*
   2  * Copyright (C) 2012  Renesas Solutions Corp.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <malloc.h>
   9 #include <asm/processor.h>
  10 #include <asm/io.h>
  11 #include <asm/mmc.h>
  12 #include <spi_flash.h>
  13
  14 int checkboard(void)
  15 {
  16         puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
  17
  18         return 0;
  19 }
  20
  21 static void init_gpio(void)
  22 {
  23         struct gpio_regs *gpio = GPIO_BASE;
  24         struct sermux_regs *sermux = SERMUX_BASE;
  25
  26         /* GPIO */
  27         writew(0x0000, &gpio->pacr);    /* GETHER */
  28         writew(0x0001, &gpio->pbcr);    /* INTC */
  29         writew(0x0000, &gpio->pccr);    /* PWMU, INTC */
  30         writew(0xeaff, &gpio->pecr);    /* GPIO */
  31         writew(0x0000, &gpio->pfcr);    /* WDT */
  32         writew(0x0000, &gpio->phcr);    /* SPI1 */
  33         writew(0x0000, &gpio->picr);    /* SDHI */
  34         writew(0x0003, &gpio->pkcr);    /* SerMux */
  35         writew(0x0000, &gpio->plcr);    /* SerMux */
  36         writew(0x0000, &gpio->pmcr);    /* RIIC */
  37         writew(0x0000, &gpio->pncr);    /* USB, SGPIO */
  38         writew(0x0000, &gpio->pocr);    /* SGPIO */
  39         writew(0xd555, &gpio->pqcr);    /* GPIO */
  40         writew(0x0000, &gpio->prcr);    /* RIIC */
  41         writew(0x0000, &gpio->pscr);    /* RIIC */
  42         writeb(0x00, &gpio->pudr);
  43         writew(0x5555, &gpio->pucr);    /* Debug LED */
  44         writew(0x0000, &gpio->pvcr);    /* RSPI */
  45         writew(0x0000, &gpio->pwcr);    /* EVC */
  46         writew(0x0000, &gpio->pxcr);    /* LBSC */
  47         writew(0x0000, &gpio->pycr);    /* LBSC */
  48         writew(0x0000, &gpio->pzcr);    /* eMMC */
  49         writew(0xfe00, &gpio->psel0);
  50         writew(0xff00, &gpio->psel3);
  51         writew(0x771f, &gpio->psel4);
  52         writew(0x00ff, &gpio->psel6);
  53         writew(0xfc00, &gpio->psel7);
  54
  55         writeb(0x10, &sermux->smr0);    /* SMR0: SerMux mode 0 */
  56 }
  57
  58 static void init_usb_phy(void)
  59 {
  60         struct usb_common_regs *common0 = USB0_COMMON_BASE;
  61         struct usb_common_regs *common1 = USB1_COMMON_BASE;
  62         struct usb0_phy_regs *phy = USB0_PHY_BASE;
  63         struct usb1_port_regs *port = USB1_PORT_BASE;
  64         struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  65
  66         writew(0x0100, &phy->reset);            /* set reset */
  67         /* port0 = USB0, port1 = USB1 */
  68         writew(0x0002, &phy->portsel);
  69         writel(0x0001, &port->port1sel);        /* port1 = Host */
  70         writew(0x0111, &phy->reset);            /* clear reset */
  71
  72         writew(0x4000, &common0->suspmode);
  73         writew(0x4000, &common1->suspmode);
  74
  75 #if defined(__LITTLE_ENDIAN)
  76         writel(0x00000000, &align->ehcidatac);
  77         writel(0x00000000, &align->ohcidatac);
  78 #endif
  79 }
  80
  81 static void init_gether_mdio(void)
  82 {
  83         struct gpio_regs *gpio = GPIO_BASE;
  84
  85         writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
  86         writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
  87 }
  88
  89 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  90 {
  91         struct ether_mac_regs *ether;
  92         unsigned char mac[6];
  93         unsigned long val;
  94
  95         eth_parse_enetaddr(mac_string, mac);
  96
  97         if (!channel)
  98                 ether = GETHER0_MAC_BASE;
  99         else
 100                 ether = GETHER1_MAC_BASE;
 101
 102         val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 103         writel(val, &ether->mahr);
 104         val = (mac[4] << 8) | mac[5];
 105         writel(val, &ether->malr);
 106 }
 107
 108 /*****************************************************************
 109  * This PMB must be set on this timing. The lowlevel_init is run on
 110  * Area 0(phys 0x00000000), so we have to map it.
 111  *
 112  * The new PMB table is following:
 113  * ent  virt            phys            v       sz      c       wt
 114  * 0    0xa0000000      0x40000000      1       128M    0       1
 115  * 1    0xa8000000      0x48000000      1       128M    0       1
 116  * 2    0xb0000000      0x50000000      1       128M    0       1
 117  * 3    0xb8000000      0x58000000      1       128M    0       1
 118  * 4    0x80000000      0x40000000      1       128M    1       1
 119  * 5    0x88000000      0x48000000      1       128M    1       1
 120  * 6    0x90000000      0x50000000      1       128M    1       1
 121  * 7    0x98000000      0x58000000      1       128M    1       1
 122  */
 123 static void set_pmb_on_board_init(void)
 124 {
 125         struct mmu_regs *mmu = MMU_BASE;
 126
 127         /* clear ITLB */
 128         writel(0x00000004, &mmu->mmucr);
 129
 130         /* delete PMB for SPIBOOT */
 131         writel(0, PMB_ADDR_BASE(0));
 132         writel(0, PMB_DATA_BASE(0));
 133
 134         /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
 135         /*                      ppn  ub v s1 s0  c  wt */
 136         writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
 137         writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
 138         writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
 139         writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
 140         writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
 141         writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
 142         writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
 143         writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
 144         writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
 145         writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
 146         writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
 147         writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
 148 }
 149
 150 int board_init(void)
 151 {
 152         init_gpio();
 153         set_pmb_on_board_init();
 154
 155         init_usb_phy();
 156         init_gether_mdio();
 157
 158         return 0;
 159 }
 160
 161 int dram_init(void)
 162 {
 163         DECLARE_GLOBAL_DATA_PTR;
 164
 165         gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
 166         gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 167         printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 168
 169         return 0;
 170 }
 171
 172 int board_mmc_init(bd_t *bis)
 173 {
 174         struct gpio_regs *gpio = GPIO_BASE;
 175
 176         writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
 177         writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
 178         udelay(1);
 179         writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
 180         udelay(200);
 181
 182         return mmcif_mmc_init();
 183 }
 184
 185 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
 186 {
 187         struct spi_flash *spi;
 188         int ret;
 189
 190         spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
 191         if (spi == NULL) {
 192                 printf("%s: spi_flash probe failed.\n", __func__);
 193                 return 1;
 194         }
 195
 196         ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
 197         if (ret) {
 198                 printf("%s: spi_flash read failed.\n", __func__);
 199                 spi_flash_free(spi);
 200                 return 1;
 201         }
 202         spi_flash_free(spi);
 203
 204         return 0;
 205 }
 206
 207 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
 208 {
 209         memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
 210                 SH7752EVB_ETHERNET_MAC_SIZE);
 211         mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
 212
 213         return 0;
 214 }
 215
 216 static void init_ethernet_mac(void)
 217 {
 218         char mac_string[64];
 219         char env_string[64];
 220         int i;
 221         unsigned char *buf;
 222
 223         buf = malloc(256);
 224         if (!buf) {
 225                 printf("%s: malloc failed.\n", __func__);
 226                 return;
 227         }
 228         get_sh_eth_mac_raw(buf, 256);
 229
 230         /* Gigabit Ethernet */
 231         for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
 232                 get_sh_eth_mac(i, mac_string, buf);
 233                 if (i == 0)
 234                         setenv("ethaddr", mac_string);
 235                 else {
 236                         sprintf(env_string, "eth%daddr", i);
 237                         setenv(env_string, mac_string);
 238                 }
 239                 set_mac_to_sh_giga_eth_register(i, mac_string);
 240         }
 241
 242         free(buf);
 243 }
 244
 245 int board_late_init(void)
 246 {
 247         init_ethernet_mac();
 248
 249         return 0;
 250 }
 251
 252 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 253 {
 254         int i, ret;
 255         char mac_string[256];
 256         struct spi_flash *spi;
 257         unsigned char *buf;
 258
 259         if (argc != 3) {
 260                 buf = malloc(256);
 261                 if (!buf) {
 262                         printf("%s: malloc failed.\n", __func__);
 263                         return 1;
 264                 }
 265
 266                 get_sh_eth_mac_raw(buf, 256);
 267
 268                 /* print current MAC address */
 269                 for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
 270                         get_sh_eth_mac(i, mac_string, buf);
 271                         printf("GETHERC ch%d = %s\n", i, mac_string);
 272                 }
 273                 free(buf);
 274                 return 0;
 275         }
 276
 277         /* new setting */
 278         memset(mac_string, 0xff, sizeof(mac_string));
 279         sprintf(mac_string, "%s\t%s",
 280                 argv[1], argv[2]);
 281
 282         /* write MAC data to SPI rom */
 283         spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
 284         if (!spi) {
 285                 printf("%s: spi_flash probe failed.\n", __func__);
 286                 return 1;
 287         }
 288
 289         ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
 290                                 SH7752EVB_SPI_SECTOR_SIZE);
 291         if (ret) {
 292                 printf("%s: spi_flash erase failed.\n", __func__);
 293                 return 1;
 294         }
 295
 296         ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
 297                                 sizeof(mac_string), mac_string);
 298         if (ret) {
 299                 printf("%s: spi_flash write failed.\n", __func__);
 300                 spi_flash_free(spi);
 301                 return 1;
 302         }
 303         spi_flash_free(spi);
 304
 305         puts("The writing of the MAC address to SPI ROM was completed.\n");
 306
 307         return 0;
 308 }
 309
 310 U_BOOT_CMD(
 311         write_mac,      3,      1,      do_write_mac,
 312         "write MAC address for GETHERC",
 313         "[GETHERC ch0] [GETHERC ch1]\n"
 314 );