board/renesas/sh7785lcr/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19 #include <config.h>
  20 #include <version.h>
  21 #include <asm/processor.h>
  22
  23 .macro  write32, addr, data
  24         mov.l \addr ,r1
  25         mov.l \data ,r0
  26         mov.l r0, @r1
  27 .endm
  28
  29 .macro  write16, addr, data
  30         mov.l \addr ,r1
  31         mov.l \data ,r0
  32         mov.w r0, @r1
  33 .endm
  34
  35 .macro  write8, addr, data
  36         mov.l \addr ,r1
  37         mov.l \data ,r0
  38         mov.b r0, @r1
  39 .endm
  40
  41 .macro  wait_timer, time
  42         mov.l   \time ,r3
  43 1:
  44         nop
  45         tst     r3, r3
  46         bf/s    1b
  47         dt      r3
  48 .endm
  49
  50 #include <asm/processor.h>
  51
  52         .global lowlevel_init
  53
  54         .text
  55         .align  2
  56
  57 lowlevel_init:
  58         wait_timer      WAIT_200US
  59         wait_timer      WAIT_200US
  60
  61         /*------- LBSC -------*/
  62         write32 MMSELR_A,       MMSELR_D
  63
  64         /*------- DBSC2 -------*/
  65         write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
  66         write32 DBSC2_DBTR0_A,  DBSC2_DBTR0_D
  67         write32 DBSC2_DBTR1_A,  DBSC2_DBTR1_D
  68         write32 DBSC2_DBTR2_A,  DBSC2_DBTR2_D
  69         write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
  70         write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
  71         wait_timer      WAIT_200US
  72
  73         write32 DBSC2_DBDICODTOCD_A,    DBSC2_DBDICODTOCD_D
  74         write32 DBSC2_DBCMDCNT_A,       DBSC2_DBCMDCNT_D_CKE_H
  75         wait_timer      WAIT_200US
  76         write32 DBSC2_DBCMDCNT_A,       DBSC2_DBCMDCNT_D_PALL
  77         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_EMRS2
  78         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_EMRS3
  79         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_EMRS1_1
  80         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_MRS_1
  81         write32 DBSC2_DBCMDCNT_A,       DBSC2_DBCMDCNT_D_PALL
  82         write32 DBSC2_DBCMDCNT_A,       DBSC2_DBCMDCNT_D_REF
  83         write32 DBSC2_DBCMDCNT_A,       DBSC2_DBCMDCNT_D_REF
  84         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_MRS_2
  85         wait_timer      WAIT_200US
  86
  87         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_EMRS1_2
  88         write32 DBSC2_DBMRCNT_A,        DBSC2_DBMRCNT_D_EMRS1_1
  89
  90         write32 DBSC2_DBEN_A,           DBSC2_DBEN_D
  91         write32 DBSC2_DBRFCNT1_A,       DBSC2_DBRFCNT1_D
  92         write32 DBSC2_DBRFCNT2_A,       DBSC2_DBRFCNT2_D
  93         write32 DBSC2_DBRFCNT0_A,       DBSC2_DBRFCNT0_D
  94         wait_timer      WAIT_200US
  95
  96         /*------- GPIO -------*/
  97         write16 PACR_A, PACR_D
  98         write16 PBCR_A, PBCR_D
  99         write16 PCCR_A, PCCR_D
 100         write16 PDCR_A, PDCR_D
 101         write16 PECR_A, PECR_D
 102         write16 PFCR_A, PFCR_D
 103         write16 PGCR_A, PGCR_D
 104         write16 PHCR_A, PHCR_D
 105         write16 PJCR_A, PJCR_D
 106         write16 PKCR_A, PKCR_D
 107         write16 PLCR_A, PLCR_D
 108         write16 PMCR_A, PMCR_D
 109         write16 PNCR_A, PNCR_D
 110         write16 PPCR_A, PPCR_D
 111         write16 PQCR_A, PQCR_D
 112         write16 PRCR_A, PRCR_D
 113
 114         write8  PEPUPR_A,       PEPUPR_D
 115         write8  PHPUPR_A,       PHPUPR_D
 116         write8  PJPUPR_A,       PJPUPR_D
 117         write8  PKPUPR_A,       PKPUPR_D
 118         write8  PLPUPR_A,       PLPUPR_D
 119         write8  PMPUPR_A,       PMPUPR_D
 120         write8  PNPUPR_A,       PNPUPR_D
 121         write16 PPUPR1_A,       PPUPR1_D
 122         write16 PPUPR2_A,       PPUPR2_D
 123         write16 P1MSELR_A,      P1MSELR_D
 124         write16 P2MSELR_A,      P2MSELR_D
 125
 126         /*------- LBSC -------*/
 127         write32 BCR_A,          BCR_D
 128         write32 CS0BCR_A,       CS0BCR_D
 129         write32 CS0WCR_A,       CS0WCR_D
 130         write32 CS1BCR_A,       CS1BCR_D
 131         write32 CS1WCR_A,       CS1WCR_D
 132         write32 CS4BCR_A,       CS4BCR_D
 133         write32 CS4WCR_A,       CS4WCR_D
 134
 135         mov.l   PASCR_A, r0
 136         mov.l   @r0, r2
 137         mov.l   PASCR_32BIT_MODE, r1
 138         tst     r1, r2
 139         bt      lbsc_29bit
 140
 141         write32 CS2BCR_A,       CS_USB_BCR_D
 142         write32 CS2WCR_A,       CS_USB_WCR_D
 143         write32 CS3BCR_A,       CS_SD_BCR_D
 144         write32 CS3WCR_A,       CS_SD_WCR_D
 145         write32 CS5BCR_A,       CS_I2C_BCR_D
 146         write32 CS5WCR_A,       CS_I2C_WCR_D
 147         write32 CS6BCR_A,       CS0BCR_D
 148         write32 CS6WCR_A,       CS0WCR_D
 149         bra     lbsc_end
 150          nop
 151
 152 lbsc_29bit:
 153         write32 CS5BCR_A,       CS_USB_BCR_D
 154         write32 CS5WCR_A,       CS_USB_WCR_D
 155         write32 CS6BCR_A,       CS_SD_BCR_D
 156         write32 CS6WCR_A,       CS_SD_WCR_D
 157
 158 lbsc_end:
 159
 160         write32 CCR_A,  CCR_D
 161
 162         rts
 163         nop
 164
 165         .align 4
 166
 167 /*------- LBSC -------*/
 168 MMSELR_A:       .long   0xfc400020
 169 MMSELR_D:       .long   0xa5a50002
 170
 171 /*------- DBSC2 -------*/
 172 #define DBSC2_BASE      0xfe800000
 173 DBSC2_DBSTATE_A:        .long   DBSC2_BASE + 0x0c
 174 DBSC2_DBEN_A:           .long   DBSC2_BASE + 0x10
 175 DBSC2_DBCMDCNT_A:       .long   DBSC2_BASE + 0x14
 176 DBSC2_DBCONF_A:         .long   DBSC2_BASE + 0x20
 177 DBSC2_DBTR0_A:          .long   DBSC2_BASE + 0x30
 178 DBSC2_DBTR1_A:          .long   DBSC2_BASE + 0x34
 179 DBSC2_DBTR2_A:          .long   DBSC2_BASE + 0x38
 180 DBSC2_DBRFCNT0_A:       .long   DBSC2_BASE + 0x40
 181 DBSC2_DBRFCNT1_A:       .long   DBSC2_BASE + 0x44
 182 DBSC2_DBRFCNT2_A:       .long   DBSC2_BASE + 0x48
 183 DBSC2_DBRFSTS_A:        .long   DBSC2_BASE + 0x4c
 184 DBSC2_DBFREQ_A:         .long   DBSC2_BASE + 0x50
 185 DBSC2_DBDICODTOCD_A:    .long   DBSC2_BASE + 0x54
 186 DBSC2_DBMRCNT_A:        .long   DBSC2_BASE + 0x60
 187 DDR_DUMMY_ACCESS_A:     .long   0x40000000
 188
 189 DBSC2_DBCONF_D:         .long   0x00630002
 190 DBSC2_DBTR0_D:          .long   0x050b1f04
 191 DBSC2_DBTR1_D:          .long   0x00040204
 192 DBSC2_DBTR2_D:          .long   0x02100308
 193 DBSC2_DBFREQ_D1:        .long   0x00000000
 194 DBSC2_DBFREQ_D2:        .long   0x00000100
 195 DBSC2_DBDICODTOCD_D:    .long   0x000f0907
 196
 197 DBSC2_DBCMDCNT_D_CKE_H: .long   0x00000003
 198 DBSC2_DBCMDCNT_D_PALL:  .long   0x00000002
 199 DBSC2_DBCMDCNT_D_REF:   .long   0x00000004
 200
 201 DBSC2_DBMRCNT_D_EMRS2:  .long   0x00020000
 202 DBSC2_DBMRCNT_D_EMRS3:  .long   0x00030000
 203 DBSC2_DBMRCNT_D_EMRS1_1:        .long   0x00010006
 204 DBSC2_DBMRCNT_D_EMRS1_2:        .long   0x00010386
 205 DBSC2_DBMRCNT_D_MRS_1:  .long   0x00000952
 206 DBSC2_DBMRCNT_D_MRS_2:  .long   0x00000852
 207
 208 DBSC2_DBEN_D:           .long   0x00000001
 209
 210 DBSC2_DBPDCNT0_D3:      .long   0x00000080
 211 DBSC2_DBRFCNT1_D:       .long   0x00000926
 212 DBSC2_DBRFCNT2_D:       .long   0x00fe00fe
 213 DBSC2_DBRFCNT0_D:       .long   0x00010000
 214
 215 WAIT_200US:     .long   33333
 216
 217 /*------- GPIO -------*/
 218 #define GPIO_BASE       0xffe70000
 219 PACR_A:         .long   GPIO_BASE + 0x00
 220 PBCR_A:         .long   GPIO_BASE + 0x02
 221 PCCR_A:         .long   GPIO_BASE + 0x04
 222 PDCR_A:         .long   GPIO_BASE + 0x06
 223 PECR_A:         .long   GPIO_BASE + 0x08
 224 PFCR_A:         .long   GPIO_BASE + 0x0a
 225 PGCR_A:         .long   GPIO_BASE + 0x0c
 226 PHCR_A:         .long   GPIO_BASE + 0x0e
 227 PJCR_A:         .long   GPIO_BASE + 0x10
 228 PKCR_A:         .long   GPIO_BASE + 0x12
 229 PLCR_A:         .long   GPIO_BASE + 0x14
 230 PMCR_A:         .long   GPIO_BASE + 0x16
 231 PNCR_A:         .long   GPIO_BASE + 0x18
 232 PPCR_A:         .long   GPIO_BASE + 0x1a
 233 PQCR_A:         .long   GPIO_BASE + 0x1c
 234 PRCR_A:         .long   GPIO_BASE + 0x1e
 235 PEPUPR_A:       .long   GPIO_BASE + 0x48
 236 PHPUPR_A:       .long   GPIO_BASE + 0x4e
 237 PJPUPR_A:       .long   GPIO_BASE + 0x50
 238 PKPUPR_A:       .long   GPIO_BASE + 0x52
 239 PLPUPR_A:       .long   GPIO_BASE + 0x54
 240 PMPUPR_A:       .long   GPIO_BASE + 0x56
 241 PNPUPR_A:       .long   GPIO_BASE + 0x58
 242 PPUPR1_A:       .long   GPIO_BASE + 0x60
 243 PPUPR2_A:       .long   GPIO_BASE + 0x62
 244 P1MSELR_A:      .long   GPIO_BASE + 0x80
 245 P2MSELR_A:      .long   GPIO_BASE + 0x82
 246
 247 PACR_D:         .long   0x0000
 248 PBCR_D:         .long   0x0000
 249 PCCR_D:         .long   0x0000
 250 PDCR_D:         .long   0x0000
 251 PECR_D:         .long   0x0000
 252 PFCR_D:         .long   0x0000
 253 PGCR_D:         .long   0x0000
 254 PHCR_D:         .long   0x00c0
 255 PJCR_D:         .long   0xc3fc
 256 PKCR_D:         .long   0x03ff
 257 PLCR_D:         .long   0x0000
 258 PMCR_D:         .long   0xffff
 259 PNCR_D:         .long   0xf0c3
 260 PPCR_D:         .long   0x0000
 261 PQCR_D:         .long   0x0000
 262 PRCR_D:         .long   0x0000
 263
 264 PEPUPR_D:       .long   0xff
 265 PHPUPR_D:       .long   0x00
 266 PJPUPR_D:       .long   0x00
 267 PKPUPR_D:       .long   0x00
 268 PLPUPR_D:       .long   0x00
 269 PMPUPR_D:       .long   0xfc
 270 PNPUPR_D:       .long   0x00
 271 PPUPR1_D:       .long   0xffbf
 272 PPUPR2_D:       .long   0xff00
 273 P1MSELR_D:      .long   0x3780
 274 P2MSELR_D:      .long   0x0000
 275
 276 /*------- LBSC -------*/
 277 PASCR_A:                .long   0xff000070
 278 PASCR_32BIT_MODE:       .long   0x80000000      /* check booting mode */
 279
 280 BCR_A:          .long   BCR
 281 CS0BCR_A:       .long   CS0BCR
 282 CS0WCR_A:       .long   CS0WCR
 283 CS1BCR_A:       .long   CS1BCR
 284 CS1WCR_A:       .long   CS1WCR
 285 CS2BCR_A:       .long   CS2BCR
 286 CS2WCR_A:       .long   CS2WCR
 287 CS3BCR_A:       .long   CS3BCR
 288 CS3WCR_A:       .long   CS3WCR
 289 CS4BCR_A:       .long   CS4BCR
 290 CS4WCR_A:       .long   CS4WCR
 291 CS5BCR_A:       .long   CS5BCR
 292 CS5WCR_A:       .long   CS5WCR
 293 CS6BCR_A:       .long   CS6BCR
 294 CS6WCR_A:       .long   CS6WCR
 295
 296 BCR_D:          .long   0x80000003
 297 CS0BCR_D:       .long   0x22222340
 298 CS0WCR_D:       .long   0x00111118
 299 CS1BCR_D:       .long   0x11111100
 300 CS1WCR_D:       .long   0x33333303
 301 CS4BCR_D:       .long   0x11111300
 302 CS4WCR_D:       .long   0x00101012
 303
 304 /* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
 305 CS_USB_BCR_D:   .long   0x11111200
 306 CS_USB_WCR_D:   .long   0x00020004
 307
 308 /* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
 309 CS_SD_BCR_D:    .long   0x00000300
 310 CS_SD_WCR_D:    .long   0x00030108
 311
 312 /* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
 313 CS_I2C_BCR_D:   .long   0x11111100
 314 CS_I2C_WCR_D:   .long   0x00000003
 315
 316 CCR_A:          .long   0xff00001c
 317 CCR_D:          .long   0x0000090b