board/sacsng/sacsng.c

   1 /*
   2  * (C) Copyright 2002
   3  * Custom IDEAS, Inc. <www.cideas.com>
   4  * Gerald Van Baren <vanbaren@cideas.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <asm/u-boot.h>
  26 #include <common.h>
  27 #include <ioports.h>
  28 #include <mpc8260.h>
  29 #include <i2c.h>
  30 #include <spi.h>
  31
  32 #ifdef CONFIG_SHOW_BOOT_PROGRESS
  33 #include <status_led.h>
  34 #endif
  35
  36 #include "clkinit.h"
  37 #include "ioconfig.h" /* I/O configuration table */
  38
  39 /*
  40  * PBI Page Based Interleaving
  41  *   PSDMR_PBI page based interleaving
  42  *   0         bank based interleaving
  43  * External Address Multiplexing (EAMUX) adds a clock to address cycles
  44  *   (this can help with marginal board layouts)
  45  *   PSDMR_EAMUX  adds a clock
  46  *   0            no extra clock
  47  * Buffer Command (BUFCMD) adds a clock to command cycles.
  48  *   PSDMR_BUFCMD adds a clock
  49  *   0            no extra clock
  50  */
  51 #define CONFIG_PBI              PSDMR_PBI
  52 #define PESSIMISTIC_SDRAM       0
  53 #define EAMUX                   0       /* EST requires EAMUX */
  54 #define BUFCMD                  0
  55
  56 /*
  57  * ADC/DAC Defines:
  58  */
  59 #define INITIAL_SAMPLE_RATE 10016     /* Initial Daq sample rate */
  60 #define INITIAL_RIGHT_JUST  0         /* Initial DAC right justification */
  61 #define INITIAL_MCLK_DIVIDE 0         /* Initial MCLK Divide */
  62 #define INITIAL_SAMPLE_64X  1         /* Initial  64x clocking mode */
  63 #define INITIAL_SAMPLE_128X 0         /* Initial 128x clocking mode */
  64
  65 /*
  66  * ADC Defines:
  67  */
  68 #define I2C_ADC_1_ADDR 0x0E           /* I2C Address of the ADC #1 */
  69 #define I2C_ADC_2_ADDR 0x0F           /* I2C Address of the ADC #2 */
  70
  71 #define ADC_SDATA1_MASK 0x00020000    /* PA14 - CH12SDATA_PU   */
  72 #define ADC_SDATA2_MASK 0x00010000    /* PA15 - CH34SDATA_PU   */
  73
  74 #define ADC_VREF_CAP   100            /* VREF capacitor in uF */
  75 #define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
  76 #define ADC_SDATA_DELAY    100        /* ADC SDATA release delay in usec */
  77 #define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
  78                                       /* Wait at least 4100 LRCLK's */
  79
  80 #define ADC_REG1_FRAME_START    0x80  /* Frame start */
  81 #define ADC_REG1_GROUND_CAL     0x40  /* Ground calibration enable */
  82 #define ADC_REG1_ANA_MOD_PDOWN  0x20  /* Analog modulator section in power down */
  83 #define ADC_REG1_DIG_MOD_PDOWN  0x10  /* Digital modulator section in power down */
  84
  85 #define ADC_REG2_128x           0x80  /* Oversample at 128x */
  86 #define ADC_REG2_CAL            0x40  /* System calibration enable */
  87 #define ADC_REG2_CHANGE_SIGN    0x20  /* Change sign enable */
  88 #define ADC_REG2_LR_DISABLE     0x10  /* Left/Right output disable */
  89 #define ADC_REG2_HIGH_PASS_DIS  0x08  /* High pass filter disable */
  90 #define ADC_REG2_SLAVE_MODE     0x04  /* Slave mode */
  91 #define ADC_REG2_DFS            0x02  /* Digital format select */
  92 #define ADC_REG2_MUTE           0x01  /* Mute */
  93
  94 #define ADC_REG7_ADDR_ENABLE    0x80  /* Address enable */
  95 #define ADC_REG7_PEAK_ENABLE    0x40  /* Peak enable */
  96 #define ADC_REG7_PEAK_UPDATE    0x20  /* Peak update */
  97 #define ADC_REG7_PEAK_FORMAT    0x10  /* Peak display format */
  98 #define ADC_REG7_DIG_FILT_PDOWN 0x04  /* Digital filter power down enable */
  99 #define ADC_REG7_FIR2_IN_EN     0x02  /* External FIR2 input enable */
 100 #define ADC_REG7_PSYCHO_EN      0x01  /* External pyscho filter input enable */
 101
 102 /*
 103  * DAC Defines:
 104  */
 105
 106 #define I2C_DAC_ADDR 0x11             /* I2C Address of the DAC */
 107
 108 #define DAC_RST_MASK 0x00008000       /* PA16 - DAC_RST*  */
 109 #define DAC_RESET_DELAY    100        /* DAC reset delay in usec */
 110 #define DAC_INITIAL_DELAY 5000        /* DAC initialization delay in usec */
 111
 112 #define DAC_REG1_AMUTE   0x80         /* Auto-mute */
 113
 114 #define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit  */
 115 #define DAC_REG1_I2S_24_BIT       (1 << 4) /* Fmt 1: I2S up to 24 bit       */
 116 #define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */
 117 #define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */
 118 #define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */
 119 #define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */
 120
 121 #define DAC_REG1_DEM_NO           (0 << 2) /* No      De-emphasis  */
 122 #define DAC_REG1_DEM_44KHZ        (1 << 2) /* 44.1KHz De-emphasis  */
 123 #define DAC_REG1_DEM_48KHZ        (2 << 2) /* 48KHz   De-emphasis  */
 124 #define DAC_REG1_DEM_32KHZ        (3 << 2) /* 32KHz   De-emphasis  */
 125
 126 #define DAC_REG1_SINGLE 0             /*   4- 50KHz sample rate  */
 127 #define DAC_REG1_DOUBLE 1             /*  50-100KHz sample rate  */
 128 #define DAC_REG1_QUAD   2             /* 100-200KHz sample rate  */
 129 #define DAC_REG1_DSD    3             /* Direct Stream Data, DSD */
 130
 131 #define DAC_REG5_INVERT_A   0x80      /* Invert channel A */
 132 #define DAC_REG5_INVERT_B   0x40      /* Invert channel B */
 133 #define DAC_REG5_I2C_MODE   0x20      /* Control port (I2C) mode */
 134 #define DAC_REG5_POWER_DOWN 0x10      /* Power down mode */
 135 #define DAC_REG5_MUTEC_A_B  0x08      /* Mutec A=B */
 136 #define DAC_REG5_FREEZE     0x04      /* Freeze */
 137 #define DAC_REG5_MCLK_DIV   0x02      /* MCLK divide by 2 */
 138 #define DAC_REG5_RESERVED   0x01      /* Reserved */
 139
 140 /* ------------------------------------------------------------------------- */
 141
 142 /*
 143  * Check Board Identity:
 144  */
 145
 146 int checkboard(void)
 147 {
 148     printf ("SACSng\n");
 149
 150     return 0;
 151 }
 152
 153 /* ------------------------------------------------------------------------- */
 154
 155 long int initdram(int board_type)
 156 {
 157     volatile immap_t *immap  = (immap_t *)CFG_IMMR;
 158     volatile memctl8260_t *memctl = &immap->im_memctl;
 159     volatile uchar c = 0;
 160     volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
 161     uint  psdmr = CFG_PSDMR;
 162     int   i;
 163     uint   psrt = 14;                                   /* for no SPD */
 164     uint   chipselects = 1;                             /* for no SPD */
 165     uint   sdram_size = CFG_SDRAM0_SIZE * 1024 * 1024;  /* for no SPD */
 166     uint   or = CFG_OR2_PRELIM;                         /* for no SPD */
 167 #ifdef SDRAM_SPD_ADDR
 168     uint   data_width;
 169     uint   rows;
 170     uint   banks;
 171     uint   cols;
 172     uint   caslatency;
 173     uint   width;
 174     uint   rowst;
 175     uint   sdam;
 176     uint   bsma;
 177     uint   sda10;
 178     u_char spd_size;
 179     u_char data;
 180     u_char cksum;
 181     int    j;
 182 #endif
 183
 184 #ifdef SDRAM_SPD_ADDR
 185     /* Keep the compiler from complaining about potentially uninitialized vars */
 186     data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
 187
 188     /*
 189      * Read the SDRAM SPD EEPROM via I2C.
 190      */
 191     i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
 192     spd_size = data;
 193     cksum    = data;
 194     for(j = 1; j < 64; j++) {   /* read only the checksummed bytes */
 195         /* note: the I2C address autoincrements when alen == 0 */
 196         i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
 197              if(j ==  5) chipselects = data & 0x0F;
 198         else if(j ==  6) data_width  = data;
 199         else if(j ==  7) data_width |= data << 8;
 200         else if(j ==  3) rows        = data & 0x0F;
 201         else if(j ==  4) cols        = data & 0x0F;
 202         else if(j == 12) {
 203             /*
 204              * Refresh rate: this assumes the prescaler is set to
 205              * approximately 1uSec per tick.
 206              */
 207             switch(data & 0x7F) {
 208                 default:
 209                 case 0:  psrt =  14 ; /*  15.625uS */  break;
 210                 case 1:  psrt =   2;  /*   3.9uS   */  break;
 211                 case 2:  psrt =   6;  /*   7.8uS   */  break;
 212                 case 3:  psrt =  29;  /*  31.3uS   */  break;
 213                 case 4:  psrt =  60;  /*  62.5uS   */  break;
 214                 case 5:  psrt = 120;  /* 125uS     */  break;
 215             }
 216         }
 217         else if(j == 17) banks       = data;
 218         else if(j == 18) {
 219             caslatency = 3; /* default CL */
 220 #if(PESSIMISTIC_SDRAM)
 221                  if((data & 0x04) != 0) caslatency = 3;
 222             else if((data & 0x02) != 0) caslatency = 2;
 223             else if((data & 0x01) != 0) caslatency = 1;
 224 #else
 225                  if((data & 0x01) != 0) caslatency = 1;
 226             else if((data & 0x02) != 0) caslatency = 2;
 227             else if((data & 0x04) != 0) caslatency = 3;
 228 #endif
 229             else {
 230                 printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
 231                         data);
 232             }
 233         }
 234         else if(j == 63) {
 235             if(data != cksum) {
 236                 printf ("WARNING: Configuration data checksum failure:"
 237                         " is 0x%02x, calculated 0x%02x\n",
 238                         data, cksum);
 239             }
 240         }
 241         cksum += data;
 242     }
 243
 244     /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
 245     if(caslatency < 2) {
 246         printf("CL was %d, forcing to 2\n", caslatency);
 247         caslatency = 2;
 248     }
 249     if(rows > 14) {
 250         printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
 251         rows = 14;
 252     }
 253     if(cols > 11) {
 254         printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
 255         cols = 11;
 256     }
 257
 258     if((data_width != 64) && (data_width != 72))
 259     {
 260         printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
 261             data_width);
 262     }
 263     width = 3;          /* 2^3 = 8 bytes = 64 bits wide */
 264     /*
 265      * Convert banks into log2(banks)
 266      */
 267     if     (banks == 2) banks = 1;
 268     else if(banks == 4) banks = 2;
 269     else if(banks == 8) banks = 3;
 270
 271     sdram_size = 1 << (rows + cols + banks + width);
 272
 273 #if(CONFIG_PBI == 0)    /* bank-based interleaving */
 274     rowst = ((32 - 6) - (rows + cols + width)) * 2;
 275 #else
 276     rowst = 32 - (rows + banks + cols + width);
 277 #endif
 278
 279     or = ~(sdram_size - 1)    | /* SDAM address mask    */
 280           ((banks-1) << 13)   | /* banks per device     */
 281           (rowst << 9)        | /* rowst                */
 282           ((rows - 9) << 6);    /* numr                 */
 283
 284     memctl->memc_or2 = or;
 285
 286     /*
 287      * SDAM specifies the number of columns that are multiplexed
 288      * (reference AN2165/D), defined to be (columns - 6) for page
 289      * interleave, (columns - 8) for bank interleave.
 290      *
 291      * BSMA is 14 - max(rows, cols).  The bank select lines come
 292      * into play above the highest "address" line going into the
 293      * the SDRAM.
 294      */
 295 #if(CONFIG_PBI == 0)    /* bank-based interleaving */
 296     sdam = cols - 8;
 297     bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
 298     sda10 = sdam + 2;
 299 #else
 300     sdam = cols - 6;
 301     bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
 302     sda10 = sdam;
 303 #endif
 304 #if(PESSIMISTIC_SDRAM)
 305     psdmr = (CONFIG_PBI              |\
 306              PSDMR_RFEN              |\
 307              PSDMR_RFRC_16_CLK       |\
 308              PSDMR_PRETOACT_8W       |\
 309              PSDMR_ACTTORW_8W        |\
 310              PSDMR_WRC_4C            |\
 311              PSDMR_EAMUX             |\
 312              PSDMR_BUFCMD)           |\
 313              caslatency              |\
 314              ((caslatency - 1) << 6) |  /* LDOTOPRE is CL - 1 */ \
 315              (sdam << 24)            |\
 316              (bsma << 21)            |\
 317              (sda10 << 18);
 318 #else
 319     psdmr = (CONFIG_PBI              |\
 320              PSDMR_RFEN              |\
 321              PSDMR_RFRC_7_CLK        |\
 322              PSDMR_PRETOACT_3W       |  /* 1 for 7E parts (fast PC-133) */ \
 323              PSDMR_ACTTORW_2W        |  /* 1 for 7E parts (fast PC-133) */ \
 324              PSDMR_WRC_1C            |  /* 1 clock + 7nSec */
 325              EAMUX                   |\
 326              BUFCMD)                 |\
 327              caslatency              |\
 328              ((caslatency - 1) << 6) |  /* LDOTOPRE is CL - 1 */ \
 329              (sdam << 24)            |\
 330              (bsma << 21)            |\
 331              (sda10 << 18);
 332 #endif
 333 #endif
 334
 335     /*
 336      * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 337      *
 338      * "At system reset, initialization software must set up the
 339      *  programmable parameters in the memory controller banks registers
 340      *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 341      *  system software should execute the following initialization sequence
 342      *  for each SDRAM device.
 343      *
 344      *  1. Issue a PRECHARGE-ALL-BANKS command
 345      *  2. Issue eight CBR REFRESH commands
 346      *  3. Issue a MODE-SET command to initialize the mode register
 347      *
 348      * Quote from Micron MT48LC8M16A2 data sheet:
 349      *
 350      *  "...the SDRAM requires a 100uS delay prior to issuing any
 351      *  command other than a COMMAND INHIBIT or NOP.  Starting at some
 352      *  point during this 100uS period and continuing at least through
 353      *  the end of this period, COMMAND INHIBIT or NOP commands should
 354      *  be applied."
 355      *
 356      *  "Once the 100uS delay has been satisfied with at least one COMMAND
 357      *  INHIBIT or NOP command having been applied, a /PRECHARGE command/
 358      *  should be applied.  All banks must then be precharged, thereby
 359      *  placing the device in the all banks idle state."
 360      *
 361      *  "Once in the idle state, /two/ AUTO REFRESH cycles must be
 362      *  performed.  After the AUTO REFRESH cycles are complete, the
 363      *  SDRAM is ready for mode register programming."
 364      *
 365      *  (/emphasis/ mine, gvb)
 366      *
 367      *  The way I interpret this, Micron start up sequence is:
 368      *  1. Issue a PRECHARGE-BANK command (initial precharge)
 369      *  2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
 370      *  3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
 371      *  4. Issue a MODE-SET command to initialize the mode register
 372      *
 373      *  --------
 374      *
 375      *  The initial commands are executed by setting P/LSDMR[OP] and
 376      *  accessing the SDRAM with a single-byte transaction."
 377      *
 378      * The appropriate BRx/ORx registers have already been set when we
 379      * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
 380      */
 381
 382     memctl->memc_mptpr = CFG_MPTPR;
 383     memctl->memc_psrt  = psrt;
 384
 385     memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 386     *ramaddr = c;
 387
 388     memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
 389     for (i = 0; i < 8; i++)
 390         *ramaddr = c;
 391
 392     memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
 393     *ramaddr = c;
 394
 395     memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 396     *ramaddr = c;
 397
 398     /*
 399      * Do it a second time for the second set of chips if the DIMM has
 400      * two chip selects (double sided).
 401      */
 402     if(chipselects > 1) {
 403         ramaddr += sdram_size;
 404
 405         memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
 406         memctl->memc_or3 = or;
 407
 408         memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 409         *ramaddr = c;
 410
 411         memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
 412         for (i = 0; i < 8; i++)
 413             *ramaddr = c;
 414
 415         memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
 416         *ramaddr = c;
 417
 418         memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 419         *ramaddr = c;
 420     }
 421
 422     /* return total ram size */
 423     return (sdram_size * chipselects);
 424 }
 425
 426 /*-----------------------------------------------------------------------
 427  * Board Control Functions
 428  */
 429 void board_poweroff (void)
 430 {
 431     while (1);          /* hang forever */
 432 }
 433
 434
 435 #ifdef CONFIG_MISC_INIT_R
 436 /* ------------------------------------------------------------------------- */
 437 int misc_init_r(void)
 438 {
 439     /*
 440      * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
 441      */
 442     volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
 443     volatile ioport_t *iop  = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
 444
 445     int  reg;          /* I2C register value */
 446     char *ep;          /* Environment pointer */
 447     char str_buf[12] ; /* sprintf output buffer */
 448     int  sample_rate;  /* ADC/DAC sample rate */
 449     int  sample_64x;   /* Use  64/4 clocking for the ADC/DAC */
 450     int  sample_128x;  /* Use 128/4 clocking for the ADC/DAC */
 451     int  right_just;   /* Is the data to the DAC right justified? */
 452     int  mclk_divide;  /* MCLK Divide */
 453
 454     /*
 455      * SACSng custom initialization:
 456      *    Start the ADC and DAC clocks, since the Crystal parts do not
 457      *    work on the I2C bus until the clocks are running.
 458      */
 459
 460     sample_rate = INITIAL_SAMPLE_RATE;
 461     if ((ep = getenv("DaqSampleRate")) != NULL) {
 462         sample_rate = simple_strtol(ep, NULL, 10);
 463     }
 464
 465     sample_64x  = INITIAL_SAMPLE_64X;
 466     sample_128x = INITIAL_SAMPLE_128X;
 467     if ((ep = getenv("Daq64xSampling")) != NULL) {
 468         sample_64x = simple_strtol(ep, NULL, 10);
 469         if (sample_64x) {
 470             sample_128x = 0;
 471         }
 472         else {
 473             sample_128x = 1;
 474         }
 475     }
 476     else {
 477         if ((ep = getenv("Daq128xSampling")) != NULL) {
 478             sample_128x = simple_strtol(ep, NULL, 10);
 479             if (sample_128x) {
 480                 sample_64x = 0;
 481             }
 482             else {
 483                 sample_64x = 1;
 484             }
 485         }
 486     }
 487
 488     /*
 489      * Stop the clocks and wait for at least 1 LRCLK period
 490      * to make sure the clocking has really stopped.
 491      */
 492     Daq_Stop_Clocks();
 493     udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
 494
 495     /*
 496      * Initialize the clocks with the new rates
 497      */
 498     Daq_Init_Clocks(sample_rate, sample_64x);
 499     sample_rate = Daq_Get_SampleRate();
 500
 501     /*
 502      * Start the clocks and wait for at least 1 LRCLK period
 503      * to make sure the clocking has become stable.
 504      */
 505     Daq_Start_Clocks(sample_rate);
 506     udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
 507
 508     sprintf(str_buf, "%d", sample_rate);
 509     setenv("DaqSampleRate", str_buf);
 510
 511     if (sample_64x) {
 512         setenv("Daq64xSampling",  "1");
 513         setenv("Daq128xSampling", NULL);
 514     }
 515     else {
 516         setenv("Daq64xSampling",  NULL);
 517         setenv("Daq128xSampling", "1");
 518     }
 519
 520     /* Display the ADC/DAC clocking information */
 521     Daq_Display_Clocks();
 522
 523     /*
 524      * Determine the DAC data justification
 525      */
 526
 527     right_just = INITIAL_RIGHT_JUST;
 528     if ((ep = getenv("DaqDACRightJustified")) != NULL) {
 529         right_just = simple_strtol(ep, NULL, 10);
 530     }
 531
 532     sprintf(str_buf, "%d", right_just);
 533     setenv("DaqDACRightJustified", str_buf);
 534
 535     /*
 536      * Determine the DAC MCLK Divide
 537      */
 538
 539     mclk_divide = INITIAL_MCLK_DIVIDE;
 540     if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
 541         mclk_divide = simple_strtol(ep, NULL, 10);
 542     }
 543
 544     sprintf(str_buf, "%d", mclk_divide);
 545     setenv("DaqDACMClockDivide", str_buf);
 546
 547     /*
 548      * Initializing the I2C address in the Crystal A/Ds:
 549      *
 550      * 1) Wait for VREF cap to settle (10uSec per uF)
 551      * 2) Release pullup on SDATA
 552      * 3) Write the I2C address to register 6
 553      * 4) Enable address matching by setting the MSB in register 7
 554      */
 555
 556     printf("Initializing the ADC...\n");
 557     udelay(ADC_INITIAL_DELAY);          /* 10uSec per uF of VREF cap */
 558
 559     iopa->pdat &= ~ADC_SDATA1_MASK;     /* release SDATA1 */
 560     udelay(ADC_SDATA_DELAY);            /* arbitrary settling time */
 561
 562     i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR);  /* set address */
 563     i2c_reg_write(I2C_ADC_1_ADDR, 0x07,         /* turn on ADDREN */
 564                   ADC_REG7_ADDR_ENABLE);
 565
 566     i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
 567                   (sample_64x ? 0 : ADC_REG2_128x) |
 568                   ADC_REG2_HIGH_PASS_DIS |
 569                   ADC_REG2_SLAVE_MODE);
 570
 571     reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
 572     if(reg != I2C_ADC_1_ADDR)
 573         printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
 574                reg, I2C_ADC_1_ADDR);
 575
 576     iopa->pdat &= ~ADC_SDATA2_MASK;     /* release SDATA2 */
 577     udelay(ADC_SDATA_DELAY);            /* arbitrary settling time */
 578
 579     i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR);  /* set address (do not set ADDREN yet) */
 580
 581     i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
 582                   (sample_64x ? 0 : ADC_REG2_128x) |
 583                   ADC_REG2_HIGH_PASS_DIS |
 584                   ADC_REG2_SLAVE_MODE);
 585
 586     reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
 587     if(reg != I2C_ADC_2_ADDR)
 588         printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
 589                reg, I2C_ADC_2_ADDR);
 590
 591     i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
 592                   ADC_REG1_FRAME_START |
 593                   ADC_REG1_GROUND_CAL);
 594
 595     i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
 596                   (sample_64x ? 0 : ADC_REG2_128x) |
 597                   ADC_REG2_CAL |
 598                   ADC_REG2_HIGH_PASS_DIS |
 599                   ADC_REG2_SLAVE_MODE);
 600
 601     udelay(ADC_CAL_DELAY);              /* a minimum of 4100 LRCLKs */
 602     i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00);  /* remove GNDCAL */
 603
 604     /*
 605      * Now that we have synchronized the ADC's, enable address
 606      * selection on the second ADC as well as the first.
 607      */
 608     i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
 609
 610     /*
 611      * Initialize the Crystal DAC
 612      *
 613      * Two of the config lines are used for I2C so we have to set them
 614      * to the proper initialization state without inadvertantly
 615      * sending an I2C "start" sequence.  When we bring the I2C back to
 616      * the normal state, we send an I2C "stop" sequence.
 617      */
 618     printf("Initializing the DAC...\n");
 619
 620     /*
 621      * Bring the I2C clock and data lines low for initialization
 622      */
 623     I2C_SCL(0);
 624     I2C_DELAY;
 625     I2C_SDA(0);
 626     I2C_ACTIVE;
 627     I2C_DELAY;
 628
 629     /* Reset the DAC */
 630     iopa->pdat &= ~DAC_RST_MASK;
 631     udelay(DAC_RESET_DELAY);
 632
 633     /* Release the DAC reset */
 634     iopa->pdat |=  DAC_RST_MASK;
 635     udelay(DAC_INITIAL_DELAY);
 636
 637     /*
 638      * Cause the DAC to:
 639      *     Enable control port (I2C mode)
 640      *     Going into power down
 641      */
 642     i2c_reg_write(I2C_DAC_ADDR, 0x05,
 643                   DAC_REG5_I2C_MODE |
 644                   DAC_REG5_POWER_DOWN);
 645
 646     /*
 647      * Cause the DAC to:
 648      *     Enable control port (I2C mode)
 649      *     Going into power down
 650      *         . MCLK divide by 1
 651      *         . MCLK divide by 2
 652      */
 653     i2c_reg_write(I2C_DAC_ADDR, 0x05,
 654                   DAC_REG5_I2C_MODE |
 655                   DAC_REG5_POWER_DOWN |
 656                   (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
 657
 658     /*
 659      * Cause the DAC to:
 660      *     Auto-mute disabled
 661      *         . Format 0, left  justified 24 bits
 662      *         . Format 3, right justified 24 bits
 663      *     No de-emphasis
 664      *         . Single speed mode
 665      *         . Double speed mode
 666      */
 667     i2c_reg_write(I2C_DAC_ADDR, 0x01,
 668                   (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
 669                                 DAC_REG1_LEFT_JUST_24_BIT) |
 670                   DAC_REG1_DEM_NO |
 671                   (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
 672
 673     sprintf(str_buf, "%d",
 674             sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
 675     setenv("DaqDACFunctionalMode", str_buf);
 676
 677     /*
 678      * Cause the DAC to:
 679      *     Enable control port (I2C mode)
 680      *     Remove power down
 681      *         . MCLK divide by 1
 682      *         . MCLK divide by 2
 683      */
 684     i2c_reg_write(I2C_DAC_ADDR, 0x05,
 685                   DAC_REG5_I2C_MODE |
 686                   (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
 687
 688     /*
 689      * Create a I2C stop condition:
 690      *     low->high on data while clock is high.
 691      */
 692     I2C_SCL(1);
 693     I2C_DELAY;
 694     I2C_SDA(1);
 695     I2C_DELAY;
 696     I2C_TRISTATE;
 697
 698     printf("\n");
 699
 700 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 701     /*
 702      * Turn off the RED fail LED now that we are up and running.
 703      */
 704     status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
 705 #endif
 706
 707     return 0;
 708 }
 709
 710 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 711 /*
 712  * Show boot status: flash the LED if something goes wrong, indicating
 713  * that last thing that worked and thus, by implication, what is broken.
 714  *
 715  * This stores the last OK value in RAM so this will not work properly
 716  * before RAM is initialized.  Since it is being used for indicating
 717  * boot status (i.e. after RAM is initialized), that is OK.
 718  */
 719 static void flash_code(uchar number, uchar modulo, uchar digits)
 720 {
 721     int   j;
 722
 723     /*
 724      * Recursively do upper digits.
 725      */
 726     if(digits > 1) {
 727         flash_code(number / modulo, modulo, digits - 1);
 728     }
 729
 730     number = number % modulo;
 731
 732     /*
 733      * Zero is indicated by one long flash (dash).
 734      */
 735     if(number == 0) {
 736         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
 737         udelay(1000000);
 738         status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
 739         udelay(200000);
 740     } else {
 741         /*
 742          * Non-zero is indicated by short flashes, one per count.
 743          */
 744         for(j = 0; j < number; j++) {
 745             status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
 746             udelay(100000);
 747             status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
 748             udelay(200000);
 749         }
 750     }
 751     /*
 752      * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
 753      */
 754     udelay(700000);
 755 }
 756
 757 static int last_boot_progress;
 758
 759 void show_boot_progress (int status)
 760 {
 761     if(status != -1) {
 762         last_boot_progress = status;
 763     } else {
 764         /*
 765          * Houston, we have a problem.  Blink the last OK status which
 766          * indicates where things failed.
 767          */
 768         status_led_set(STATUS_LED_RED, STATUS_LED_ON);
 769         flash_code(last_boot_progress, 5, 3);
 770         udelay(1000000);
 771         status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
 772     }
 773 }
 774 #endif /* CONFIG_SHOW_BOOT_PROGRESS */
 775
 776
 777 /*
 778  * The following are used to control the SPI chip selects for the SPI command.
 779  */
 780 #if (CONFIG_COMMANDS & CFG_CMD_SPI)
 781
 782 #define SPI_ADC_CS_MASK 0x00000800
 783 #define SPI_DAC_CS_MASK 0x00001000
 784
 785 void spi_adc_chipsel(int cs)
 786 {
 787     volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
 788
 789     if(cs)
 790         iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */
 791     else
 792         iopd->pdat |=  SPI_ADC_CS_MASK; /* deactivate the chip select */
 793 }
 794
 795 void spi_dac_chipsel(int cs)
 796 {
 797     volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
 798
 799     if(cs)
 800         iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */
 801     else
 802         iopd->pdat |=  SPI_DAC_CS_MASK; /* deactivate the chip select */
 803 }
 804
 805 /*
 806  * The SPI command uses this table of functions for controlling the SPI
 807  * chip selects: it calls the appropriate function to control the SPI
 808  * chip selects.
 809  */
 810 spi_chipsel_type spi_chipsel[] = {
 811         spi_adc_chipsel,
 812         spi_dac_chipsel
 813 };
 814 int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
 815
 816 #endif /* CFG_CMD_SPI */
 817
 818 #endif /* CONFIG_MISC_INIT_R */
 819
 820 #ifdef CONFIG_POST
 821 /*
 822  * Returns 1 if keys pressed to start the power-on long-running tests
 823  * Called from board_init_f().
 824  */
 825 int post_hotkeys_pressed(void)
 826 {
 827         return 0;       /* No hotkeys supported */
 828 }
 829
 830 #endif