board/samsung/smdk2410/lowlevel_init.S

   1 /*
   2  * Memory Setup stuff - taken from blob memsetup.S
   3  *
   4  * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
   5  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
   6  *
   7  * Modified for the Samsung SMDK2410 by
   8  * (C) Copyright 2002
   9  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14
  15 #include <config.h>
  16 #include <version.h>
  17
  18
  19 /* some parameters for the board */
  20
  21 /*
  22  *
  23  * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
  24  *
  25  * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
  26  *
  27  */
  28
  29 #define BWSCON  0x48000000
  30
  31 /* BWSCON */
  32 #define DW8                     (0x0)
  33 #define DW16                    (0x1)
  34 #define DW32                    (0x2)
  35 #define WAIT                    (0x1<<2)
  36 #define UBLB                    (0x1<<3)
  37
  38 #define B1_BWSCON               (DW32)
  39 #define B2_BWSCON               (DW16)
  40 #define B3_BWSCON               (DW16 + WAIT + UBLB)
  41 #define B4_BWSCON               (DW16)
  42 #define B5_BWSCON               (DW16)
  43 #define B6_BWSCON               (DW32)
  44 #define B7_BWSCON               (DW32)
  45
  46 /* BANK0CON */
  47 #define B0_Tacs                 0x0     /*  0clk */
  48 #define B0_Tcos                 0x0     /*  0clk */
  49 #define B0_Tacc                 0x7     /* 14clk */
  50 #define B0_Tcoh                 0x0     /*  0clk */
  51 #define B0_Tah                  0x0     /*  0clk */
  52 #define B0_Tacp                 0x0
  53 #define B0_PMC                  0x0     /* normal */
  54
  55 /* BANK1CON */
  56 #define B1_Tacs                 0x0     /*  0clk */
  57 #define B1_Tcos                 0x0     /*  0clk */
  58 #define B1_Tacc                 0x7     /* 14clk */
  59 #define B1_Tcoh                 0x0     /*  0clk */
  60 #define B1_Tah                  0x0     /*  0clk */
  61 #define B1_Tacp                 0x0
  62 #define B1_PMC                  0x0
  63
  64 #define B2_Tacs                 0x0
  65 #define B2_Tcos                 0x0
  66 #define B2_Tacc                 0x7
  67 #define B2_Tcoh                 0x0
  68 #define B2_Tah                  0x0
  69 #define B2_Tacp                 0x0
  70 #define B2_PMC                  0x0
  71
  72 #define B3_Tacs                 0x0     /*  0clk */
  73 #define B3_Tcos                 0x3     /*  4clk */
  74 #define B3_Tacc                 0x7     /* 14clk */
  75 #define B3_Tcoh                 0x1     /*  1clk */
  76 #define B3_Tah                  0x0     /*  0clk */
  77 #define B3_Tacp                 0x3     /*  6clk */
  78 #define B3_PMC                  0x0     /* normal */
  79
  80 #define B4_Tacs                 0x0     /*  0clk */
  81 #define B4_Tcos                 0x0     /*  0clk */
  82 #define B4_Tacc                 0x7     /* 14clk */
  83 #define B4_Tcoh                 0x0     /*  0clk */
  84 #define B4_Tah                  0x0     /*  0clk */
  85 #define B4_Tacp                 0x0
  86 #define B4_PMC                  0x0     /* normal */
  87
  88 #define B5_Tacs                 0x0     /*  0clk */
  89 #define B5_Tcos                 0x0     /*  0clk */
  90 #define B5_Tacc                 0x7     /* 14clk */
  91 #define B5_Tcoh                 0x0     /*  0clk */
  92 #define B5_Tah                  0x0     /*  0clk */
  93 #define B5_Tacp                 0x0
  94 #define B5_PMC                  0x0     /* normal */
  95
  96 #define B6_MT                   0x3     /* SDRAM */
  97 #define B6_Trcd                 0x1
  98 #define B6_SCAN                 0x1     /* 9bit */
  99
 100 #define B7_MT                   0x3     /* SDRAM */
 101 #define B7_Trcd                 0x1     /* 3clk */
 102 #define B7_SCAN                 0x1     /* 9bit */
 103
 104 /* REFRESH parameter */
 105 #define REFEN                   0x1     /* Refresh enable */
 106 #define TREFMD                  0x0     /* CBR(CAS before RAS)/Auto refresh */
 107 #define Trp                     0x0     /* 2clk */
 108 #define Trc                     0x3     /* 7clk */
 109 #define Tchr                    0x2     /* 3clk */
 110 #define REFCNT                  1113    /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
 111 /**************************************/
 112
 113 _TEXT_BASE:
 114         .word   CONFIG_SYS_TEXT_BASE
 115
 116 .globl lowlevel_init
 117 lowlevel_init:
 118         /* memory control configuration */
 119         /* make r0 relative the current location so that it */
 120         /* reads SMRDATA out of FLASH rather than memory ! */
 121         ldr     r0, =SMRDATA
 122         ldr     r1, _TEXT_BASE
 123         sub     r0, r0, r1
 124         ldr     r1, =BWSCON     /* Bus Width Status Controller */
 125         add     r2, r0, #13*4
 126 0:
 127         ldr     r3, [r0], #4
 128         str     r3, [r1], #4
 129         cmp     r2, r0
 130         bne     0b
 131
 132         /* everything is fine now */
 133         mov     pc, lr
 134
 135         .ltorg
 136 /* the literal pools origin */
 137
 138 SMRDATA:
 139     .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
 140     .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
 141     .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
 142     .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
 143     .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
 144     .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
 145     .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
 146     .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
 147     .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
 148     .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
 149     .word 0x32
 150     .word 0x30
 151     .word 0x30