board/samsung/smdk5250/smdk5250.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <asm/io.h>
  10 #include <errno.h>
  11 #include <i2c.h>
  12 #include <lcd.h>
  13 #include <netdev.h>
  14 #include <spi.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/dwmmc.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/mmc.h>
  19 #include <asm/arch/pinmux.h>
  20 #include <asm/arch/power.h>
  21 #include <asm/arch/sromc.h>
  22 #include <asm/arch/dp_info.h>
  23 #include <power/pmic.h>
  24 #include <power/max77686_pmic.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #ifdef CONFIG_USB_EHCI_EXYNOS
  29 int board_usb_vbus_init(void)
  30 {
  31         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  32                                                 samsung_get_base_gpio_part1();
  33
  34         /* Enable VBUS power switch */
  35         s5p_gpio_direction_output(&gpio1->x2, 6, 1);
  36
  37         /* VBUS turn ON time */
  38         mdelay(3);
  39
  40         return 0;
  41 }
  42 #endif
  43
  44 #ifdef CONFIG_SOUND_MAX98095
  45 static void  board_enable_audio_codec(void)
  46 {
  47         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  48                                                 samsung_get_base_gpio_part1();
  49
  50         /* Enable MAX98095 Codec */
  51         s5p_gpio_direction_output(&gpio1->x1, 7, 1);
  52         s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
  53 }
  54 #endif
  55
  56 int board_init(void)
  57 {
  58         gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
  59
  60 #ifdef CONFIG_EXYNOS_SPI
  61         spi_init();
  62 #endif
  63 #ifdef CONFIG_USB_EHCI_EXYNOS
  64         board_usb_vbus_init();
  65 #endif
  66 #ifdef CONFIG_SOUND_MAX98095
  67         board_enable_audio_codec();
  68 #endif
  69         return 0;
  70 }
  71
  72 int dram_init(void)
  73 {
  74         int i;
  75         u32 addr;
  76
  77         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  78                 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
  79                 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
  80         }
  81         return 0;
  82 }
  83
  84 #if defined(CONFIG_POWER)
  85 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
  86 {
  87         u32 val;
  88         int ret = 0;
  89
  90         ret = pmic_reg_read(p, reg, &val);
  91         if (ret) {
  92                 debug("%s: PMIC %d register read failed\n", __func__, reg);
  93                 return -1;
  94         }
  95         val |= regval;
  96         ret = pmic_reg_write(p, reg, val);
  97         if (ret) {
  98                 debug("%s: PMIC %d register write failed\n", __func__, reg);
  99                 return -1;
 100         }
 101         return 0;
 102 }
 103
 104 int power_init_board(void)
 105 {
 106         struct pmic *p;
 107
 108         set_ps_hold_ctrl();
 109
 110         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 111
 112         if (pmic_init(I2C_PMIC))
 113                 return -1;
 114
 115         p = pmic_get("MAX77686_PMIC");
 116         if (!p)
 117                 return -ENODEV;
 118
 119         if (pmic_probe(p))
 120                 return -1;
 121
 122         if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
 123                 return -1;
 124
 125         if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
 126                                 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
 127                 return -1;
 128
 129         /* VDD_MIF */
 130         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
 131                                                 MAX77686_BUCK1OUT_1_05V)) {
 132                 debug("%s: PMIC %d register write failed\n", __func__,
 133                                                 MAX77686_REG_PMIC_BUCK1OUT);
 134                 return -1;
 135         }
 136
 137         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
 138                                                 MAX77686_BUCK1CTRL_EN))
 139                 return -1;
 140
 141         /* VDD_ARM */
 142         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
 143                                         MAX77686_BUCK2DVS1_1_3V)) {
 144                 debug("%s: PMIC %d register write failed\n", __func__,
 145                                                 MAX77686_REG_PMIC_BUCK2DVS1);
 146                 return -1;
 147         }
 148
 149         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
 150                                         MAX77686_BUCK2CTRL_ON))
 151                 return -1;
 152
 153         /* VDD_INT */
 154         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
 155                                         MAX77686_BUCK3DVS1_1_0125V)) {
 156                 debug("%s: PMIC %d register write failed\n", __func__,
 157                                                 MAX77686_REG_PMIC_BUCK3DVS1);
 158                 return -1;
 159         }
 160
 161         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
 162                                         MAX77686_BUCK3CTRL_ON))
 163                 return -1;
 164
 165         /* VDD_G3D */
 166         if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
 167                                         MAX77686_BUCK4DVS1_1_2V)) {
 168                 debug("%s: PMIC %d register write failed\n", __func__,
 169                                                 MAX77686_REG_PMIC_BUCK4DVS1);
 170                 return -1;
 171         }
 172
 173         if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
 174                                         MAX77686_BUCK3CTRL_ON))
 175                 return -1;
 176
 177         /* VDD_LDO2 */
 178         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
 179                                 MAX77686_LD02CTRL1_1_5V | EN_LDO))
 180                 return -1;
 181
 182         /* VDD_LDO3 */
 183         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
 184                                 MAX77686_LD03CTRL1_1_8V | EN_LDO))
 185                 return -1;
 186
 187         /* VDD_LDO5 */
 188         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
 189                                 MAX77686_LD05CTRL1_1_8V | EN_LDO))
 190                 return -1;
 191
 192         /* VDD_LDO10 */
 193         if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
 194                                 MAX77686_LD10CTRL1_1_8V | EN_LDO))
 195                 return -1;
 196
 197         return 0;
 198 }
 199 #endif
 200
 201 void dram_init_banksize(void)
 202 {
 203         int i;
 204         u32 addr, size;
 205         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 206                 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
 207                 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
 208                 gd->bd->bi_dram[i].start = addr;
 209                 gd->bd->bi_dram[i].size = size;
 210         }
 211 }
 212
 213 int board_eth_init(bd_t *bis)
 214 {
 215 #ifdef CONFIG_SMC911X
 216         u32 smc_bw_conf, smc_bc_conf;
 217         struct fdt_sromc config;
 218         fdt_addr_t base_addr;
 219
 220         /* Non-FDT configuration - bank number and timing parameters*/
 221         config.bank = CONFIG_ENV_SROM_BANK;
 222         config.width = 2;
 223
 224         config.timing[FDT_SROM_TACS] = 0x01;
 225         config.timing[FDT_SROM_TCOS] = 0x01;
 226         config.timing[FDT_SROM_TACC] = 0x06;
 227         config.timing[FDT_SROM_TCOH] = 0x01;
 228         config.timing[FDT_SROM_TAH] = 0x0C;
 229         config.timing[FDT_SROM_TACP] = 0x09;
 230         config.timing[FDT_SROM_PMC] = 0x01;
 231         base_addr = CONFIG_SMC911X_BASE;
 232
 233         /* Ethernet needs data bus width of 16 bits */
 234         if (config.width != 2) {
 235                 debug("%s: Unsupported bus width %d\n", __func__,
 236                         config.width);
 237                 return -1;
 238         }
 239         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
 240                         | SROMC_BYTE_ENABLE(config.bank);
 241
 242         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
 243                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
 244                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
 245                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
 246                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
 247                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
 248                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
 249
 250         /* Select and configure the SROMC bank */
 251         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
 252         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
 253         return smc911x_initialize(0, base_addr);
 254 #endif
 255         return 0;
 256 }
 257
 258 #ifdef CONFIG_DISPLAY_BOARDINFO
 259 int checkboard(void)
 260 {
 261         printf("\nBoard: SMDK5250\n");
 262         return 0;
 263 }
 264 #endif
 265
 266 #ifdef CONFIG_GENERIC_MMC
 267 int board_mmc_init(bd_t *bis)
 268 {
 269         int err, ret = 0, index, bus_width;
 270         u32 base;
 271
 272         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 273         if (err)
 274                 debug("SDMMC0 not configured\n");
 275         ret |= err;
 276
 277         /*EMMC: dwmmc Channel-0 with 8 bit bus width */
 278         index = 0;
 279         base =  samsung_get_base_mmc() + (0x10000 * index);
 280         bus_width = 8;
 281         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 282         if (err)
 283                 debug("dwmmc Channel-0 init failed\n");
 284         ret |= err;
 285
 286         err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
 287         if (err)
 288                 debug("SDMMC2 not configured\n");
 289         ret |= err;
 290
 291         /*SD: dwmmc Channel-2 with 4 bit bus width */
 292         index = 2;
 293         base = samsung_get_base_mmc() + (0x10000 * index);
 294         bus_width = 4;
 295         err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
 296         if (err)
 297                 debug("dwmmc Channel-2 init failed\n");
 298         ret |= err;
 299
 300         return ret;
 301 }
 302 #endif
 303
 304 static int board_uart_init(void)
 305 {
 306         int err, uart_id, ret = 0;
 307
 308         for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
 309                 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
 310                 if (err) {
 311                         debug("UART%d not configured\n",
 312                               (uart_id - PERIPH_ID_UART0));
 313                         ret |= err;
 314                 }
 315         }
 316         return ret;
 317 }
 318
 319 void board_i2c_init(const void *blob)
 320 {
 321         int i;
 322
 323         for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
 324                 exynos_pinmux_config((PERIPH_ID_I2C0 + i),
 325                                      PINMUX_FLAG_NONE);
 326         }
 327 }
 328
 329 #ifdef CONFIG_BOARD_EARLY_INIT_F
 330 int board_early_init_f(void)
 331 {
 332         int err;
 333         err = board_uart_init();
 334         if (err) {
 335                 debug("UART init failed\n");
 336                 return err;
 337         }
 338 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 339         board_i2c_init(NULL);
 340 #endif
 341         return err;
 342 }
 343 #endif
 344
 345 #ifdef CONFIG_LCD
 346 void exynos_cfg_lcd_gpio(void)
 347 {
 348         struct exynos5_gpio_part1 *gpio1 =
 349                 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 350
 351         /* For Backlight */
 352         s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
 353         s5p_gpio_set_value(&gpio1->b2, 0, 1);
 354
 355         /* LCD power on */
 356         s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
 357         s5p_gpio_set_value(&gpio1->x1, 5, 1);
 358
 359         /* Set Hotplug detect for DP */
 360         s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
 361 }
 362
 363 void exynos_set_dp_phy(unsigned int onoff)
 364 {
 365         set_dp_phy_ctrl(onoff);
 366 }
 367
 368 vidinfo_t panel_info = {
 369         .vl_freq        = 60,
 370         .vl_col         = 2560,
 371         .vl_row         = 1600,
 372         .vl_width       = 2560,
 373         .vl_height      = 1600,
 374         .vl_clkp        = CONFIG_SYS_LOW,
 375         .vl_hsp         = CONFIG_SYS_LOW,
 376         .vl_vsp         = CONFIG_SYS_LOW,
 377         .vl_dp          = CONFIG_SYS_LOW,
 378         .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
 379
 380         /* wDP panel timing infomation */
 381         .vl_hspw        = 32,
 382         .vl_hbpd        = 80,
 383         .vl_hfpd        = 48,
 384
 385         .vl_vspw        = 6,
 386         .vl_vbpd        = 37,
 387         .vl_vfpd        = 3,
 388         .vl_cmd_allow_len = 0xf,
 389
 390         .win_id         = 3,
 391         .dual_lcd_enabled = 0,
 392
 393         .init_delay     = 0,
 394         .power_on_delay = 0,
 395         .reset_delay    = 0,
 396         .interface_mode = FIMD_RGB_INTERFACE,
 397         .dp_enabled     = 1,
 398 };
 399
 400 static struct edp_device_info edp_info = {
 401         .disp_info = {
 402                 .h_res = 2560,
 403                 .h_sync_width = 32,
 404                 .h_back_porch = 80,
 405                 .h_front_porch = 48,
 406                 .v_res = 1600,
 407                 .v_sync_width  = 6,
 408                 .v_back_porch = 37,
 409                 .v_front_porch = 3,
 410                 .v_sync_rate = 60,
 411         },
 412         .lt_info = {
 413                 .lt_status = DP_LT_NONE,
 414         },
 415         .video_info = {
 416                 .master_mode = 0,
 417                 .bist_mode = DP_DISABLE,
 418                 .bist_pattern = NO_PATTERN,
 419                 .h_sync_polarity = 0,
 420                 .v_sync_polarity = 0,
 421                 .interlaced = 0,
 422                 .color_space = COLOR_RGB,
 423                 .dynamic_range = VESA,
 424                 .ycbcr_coeff = COLOR_YCBCR601,
 425                 .color_depth = COLOR_8,
 426         },
 427 };
 428
 429 static struct exynos_dp_platform_data dp_platform_data = {
 430         .edp_dev_info   = &edp_info,
 431 };
 432
 433 void init_panel_info(vidinfo_t *vid)
 434 {
 435         vid->rgb_mode   = MODE_RGB_P;
 436         exynos_set_dp_platform_data(&dp_platform_data);
 437 }
 438 #endif