]> git.ipfire.org Git - people/ms/u-boot.git/blob - board/samsung/trats/trats.c
projects / people / ms / u-boot.git / blob
? search:


7200c2ee0b1e2a51075f2c53335e8780bf399be3
[people/ms/u-boot.git] / board / samsung / trats / trats.c
1 /*
2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Donghwa Lee <dh09.lee@samsung.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <lcd.h>
12 #include <asm/io.h>
13 #include <asm/gpio.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/pinmux.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/mipi_dsim.h>
18 #include <asm/arch/watchdog.h>
19 #include <asm/arch/power.h>
20 #include <power/pmic.h>
21 #include <usb/dwc2_udc.h>
22 #include <power/max8997_pmic.h>
23 #include <power/max8997_muic.h>
24 #include <power/battery.h>
25 #include <power/max17042_fg.h>
26 #include <libtizen.h>
27 #include <usb.h>
28 #include <usb_mass_storage.h>
29
30 #include "setup.h"
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 unsigned int board_rev;
35
36 #ifdef CONFIG_REVISION_TAG
37 u32 get_board_rev(void)
38 {
39 return board_rev;
40 }
41 #endif
42
43 static void check_hw_revision(void);
44 struct dwc2_plat_otg_data s5pc210_otg_data;
45
46 int exynos_init(void)
47 {
48 check_hw_revision();
49 printf("HW Revision:\t0x%x\n", board_rev);
50
51 return 0;
52 }
53
54 void i2c_init_board(void)
55 {
56 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
57 int err;
58
59 /* I2C_5 -> PMIC */
60 err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
61 if (err) {
62 debug("I2C%d not configured\n", (I2C_5));
63 return;
64 }
65
66 /* I2C_8 -> FG */
67 gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk");
68 gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
69 gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
70 gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
71 #endif
72 }
73
74 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
75 static void trats_low_power_mode(void)
76 {
77 struct exynos4_clock *clk =
78 (struct exynos4_clock *)samsung_get_base_clock();
79 struct exynos4_power *pwr =
80 (struct exynos4_power *)samsung_get_base_power();
81
82 /* Power down CORE1 */
83 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
84 writel(0x0, &pwr->arm_core1_configuration);
85
86 /* Change the APLL frequency */
87 /* ENABLE (1 enable) | LOCKED (1 locked) */
88 /* [31] | [29] */
89 /* FSEL | MDIV | PDIV | SDIV */
90 /* [27] | [25:16] | [13:8] | [2:0] */
91 writel(0xa0c80604, &clk->apll_con0);
92
93 /* Change CPU0 clock divider */
94 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
95 /* [30:28] | [26:24] | [22:20] | [18:16] */
96 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
97 /* [14:12] | [10:8] | [6:4] | [2:0] */
98 writel(0x00000100, &clk->div_cpu0);
99
100 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
101 while (readl(&clk->div_stat_cpu0) & 0x1111111)
102 continue;
103
104 /* Change clock divider ratio for DMC */
105 /* DMCP_RATIO | DMCD_RATIO */
106 /* [22:20] | [18:16] */
107 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
108 /* [14:12] | [10:8] | [6:4] | [2:0] */
109 writel(0x13113117, &clk->div_dmc0);
110
111 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
112 while (readl(&clk->div_stat_dmc0) & 0x11111111)
113 continue;
114
115 /* Turn off unnecessary power domains */
116 writel(0x0, &pwr->xxti_configuration); /* XXTI */
117 writel(0x0, &pwr->cam_configuration); /* CAM */
118 writel(0x0, &pwr->tv_configuration); /* TV */
119 writel(0x0, &pwr->mfc_configuration); /* MFC */
120 writel(0x0, &pwr->g3d_configuration); /* G3D */
121 writel(0x0, &pwr->gps_configuration); /* GPS */
122 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
123
124 /* Turn off unnecessary clocks */
125 writel(0x0, &clk->gate_ip_cam); /* CAM */
126 writel(0x0, &clk->gate_ip_tv); /* TV */
127 writel(0x0, &clk->gate_ip_mfc); /* MFC */
128 writel(0x0, &clk->gate_ip_g3d); /* G3D */
129 writel(0x0, &clk->gate_ip_image); /* IMAGE */
130 writel(0x0, &clk->gate_ip_gps); /* GPS */
131 }
132
133 static int pmic_init_max8997(void)
134 {
135 struct pmic *p = pmic_get("MAX8997_PMIC");
136 int i = 0, ret = 0;
137 u32 val;
138
139 if (pmic_probe(p))
140 return -1;
141
142 /* BUCK1 VARM: 1.2V */
143 val = (1200000 - 650000) / 25000;
144 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
145 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
146 ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
147
148 /* BUCK2 VINT: 1.1V */
149 val = (1100000 - 650000) / 25000;
150 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
151 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
152 ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
153
154
155 /* BUCK3 G3D: 1.1V - OFF */
156 ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
157 val &= ~ENBUCK;
158 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
159
160 val = (1100000 - 750000) / 50000;
161 ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
162
163 /* BUCK4 CAMISP: 1.2V - OFF */
164 ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
165 val &= ~ENBUCK;
166 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
167
168 val = (1200000 - 650000) / 25000;
169 ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
170
171 /* BUCK5 VMEM: 1.2V */
172 val = (1200000 - 650000) / 25000;
173 for (i = 0; i < 8; i++)
174 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
175
176 val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
177 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
178
179 /* BUCK6 CAM AF: 2.8V */
180 /* No Voltage Setting Register */
181 /* GNSLCT 3.0X */
182 val = GNSLCT;
183 ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
184
185 /* BUCK7 VCC_SUB: 2.0V */
186 val = (2000000 - 750000) / 50000;
187 ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
188
189 /* LDO1 VADC: 3.3V */
190 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
191 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
192
193 /* LDO1 Disable active discharging */
194 ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
195 val &= ~LDO_ADE;
196 ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
197
198 /* LDO2 VALIVE: 1.1V */
199 val = max8997_reg_ldo(1100000) | EN_LDO;
200 ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
201
202 /* LDO3 VUSB/MIPI: 1.1V */
203 val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */
204 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
205
206 /* LDO4 VMIPI: 1.8V */
207 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
208 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
209
210 /* LDO5 VHSIC: 1.2V */
211 val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */
212 ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
213
214 /* LDO6 VCC_1.8V_PDA: 1.8V */
215 val = max8997_reg_ldo(1800000) | EN_LDO;
216 ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
217
218 /* LDO7 CAM_ISP: 1.8V */
219 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
220 ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
221
222 /* LDO8 VDAC/VUSB: 3.3V */
223 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
224 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
225
226 /* LDO9 VCC_2.8V_PDA: 2.8V */
227 val = max8997_reg_ldo(2800000) | EN_LDO;
228 ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
229
230 /* LDO10 VPLL: 1.1V */
231 val = max8997_reg_ldo(1100000) | EN_LDO;
232 ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
233
234 /* LDO11 TOUCH: 2.8V */
235 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
236 ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
237
238 /* LDO12 VTCAM: 1.8V */
239 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
240 ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
241
242 /* LDO13 VCC_3.0_LCD: 3.0V */
243 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
244 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
245
246 /* LDO14 MOTOR: 3.0V */
247 val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
248 ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
249
250 /* LDO15 LED_A: 2.8V */
251 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
252 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
253
254 /* LDO16 CAM_SENSOR: 1.8V */
255 val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
256 ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
257
258 /* LDO17 VTF: 2.8V */
259 val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
260 ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
261
262 /* LDO18 TOUCH_LED 3.3V */
263 val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
264 ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
265
266 /* LDO21 VDDQ: 1.2V */
267 val = max8997_reg_ldo(1200000) | EN_LDO;
268 ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
269
270 /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
271 val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
272 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
273 ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
274
275 if (ret) {
276 puts("MAX8997 PMIC setting error!\n");
277 return -1;
278 }
279
280 return 0;
281 }
282 #endif
283
284 int exynos_power_init(void)
285 {
286 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
287 int chrg, ret;
288 struct power_battery *pb;
289 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
290
291 /*
292 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
293 * to logical I2C adapter 0
294 *
295 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
296 * to logical I2C adapter 1
297 */
298 ret = pmic_init(I2C_5);
299 ret |= pmic_init_max8997();
300 ret |= power_fg_init(I2C_9);
301 ret |= power_muic_init(I2C_5);
302 ret |= power_bat_init(0);
303 if (ret)
304 return ret;
305
306 p_fg = pmic_get("MAX17042_FG");
307 if (!p_fg) {
308 puts("MAX17042_FG: Not found\n");
309 return -ENODEV;
310 }
311
312 p_chrg = pmic_get("MAX8997_PMIC");
313 if (!p_chrg) {
314 puts("MAX8997_PMIC: Not found\n");
315 return -ENODEV;
316 }
317
318 p_muic = pmic_get("MAX8997_MUIC");
319 if (!p_muic) {
320 puts("MAX8997_MUIC: Not found\n");
321 return -ENODEV;
322 }
323
324 p_bat = pmic_get("BAT_TRATS");
325 if (!p_bat) {
326 puts("BAT_TRATS: Not found\n");
327 return -ENODEV;
328 }
329
330 p_fg->parent = p_bat;
331 p_chrg->parent = p_bat;
332 p_muic->parent = p_bat;
333
334 p_bat->low_power_mode = trats_low_power_mode;
335 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
336
337 pb = p_bat->pbat;
338 chrg = p_muic->chrg->chrg_type(p_muic);
339 debug("CHARGER TYPE: %d\n", chrg);
340
341 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
342 puts("No battery detected\n");
343 return 0;
344 }
345
346 p_fg->fg->fg_battery_check(p_fg, p_bat);
347
348 if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
349 puts("CHARGE Battery !\n");
350 #endif
351
352 return 0;
353 }
354
355 static unsigned int get_hw_revision(void)
356 {
357 int hwrev = 0;
358 char str[10];
359 int i;
360
361 /* hw_rev[3:0] == GPE1[3:0] */
362 for (i = 0; i < 4; i++) {
363 int pin = i + EXYNOS4_GPIO_E10;
364
365 sprintf(str, "hw_rev%d", i);
366 gpio_request(pin, str);
367 gpio_cfg_pin(pin, S5P_GPIO_INPUT);
368 gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
369 }
370
371 udelay(1);
372
373 for (i = 0; i < 4; i++)
374 hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
375
376 debug("hwrev 0x%x\n", hwrev);
377
378 return hwrev;
379 }
380
381 static void check_hw_revision(void)
382 {
383 int hwrev;
384
385 hwrev = get_hw_revision();
386
387 board_rev |= hwrev;
388 }
389
390
391 #ifdef CONFIG_USB_GADGET
392 static int s5pc210_phy_control(int on)
393 {
394 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
395 int ret = 0;
396 u32 val = 0;
397 struct pmic *p = pmic_get("MAX8997_PMIC");
398 if (!p)
399 return -ENODEV;
400
401 if (pmic_probe(p))
402 return -1;
403
404 if (on) {
405 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
406 ENSAFEOUT1, LDO_ON);
407 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
408 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
409
410 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
411 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
412 } else {
413 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
414 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
415
416 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
417 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
418 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
419 ENSAFEOUT1, LDO_OFF);
420 }
421
422 if (ret) {
423 puts("MAX8997 LDO setting error!\n");
424 return -1;
425 }
426 #endif
427
428 return 0;
429 }
430
431 struct dwc2_plat_otg_data s5pc210_otg_data = {
432 .phy_control = s5pc210_phy_control,
433 .regs_phy = EXYNOS4_USBPHY_BASE,
434 .regs_otg = EXYNOS4_USBOTG_BASE,
435 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
436 .usb_flags = PHY0_SLEEP,
437 };
438
439 int board_usb_init(int index, enum usb_init_type init)
440 {
441 debug("USB_udc_probe\n");
442 return dwc2_udc_probe(&s5pc210_otg_data);
443 }
444
445 int g_dnl_board_usb_cable_connected(void)
446 {
447 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
448 struct pmic *muic = pmic_get("MAX8997_MUIC");
449 if (!muic)
450 return 0;
451
452 return !!muic->chrg->chrg_type(muic);
453 #else
454 return false;
455 #endif
456
457 }
458 #endif
459
460 static void pmic_reset(void)
461 {
462 gpio_direction_output(EXYNOS4_GPIO_X07, 1);
463 gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
464 }
465
466 static void board_clock_init(void)
467 {
468 struct exynos4_clock *clk =
469 (struct exynos4_clock *)samsung_get_base_clock();
470
471 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
472 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
473 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
474 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
475
476 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
477 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
478 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
479 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
480 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
481 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
482 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
483 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
484 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
485 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
486 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
487 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
488
489 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
490 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
491 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
492 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
493 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
494 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
495 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
496 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
497 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
498 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
499 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
500 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
501
502 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
503 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
504 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
505 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
506 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
507 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
508 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
509 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
510 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
511 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
512 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
513 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
514 }
515
516 static void board_power_init(void)
517 {
518 struct exynos4_power *pwr =
519 (struct exynos4_power *)samsung_get_base_power();
520
521 /* PS HOLD */
522 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
523
524 /* Set power down */
525 writel(0, (unsigned int)&pwr->cam_configuration);
526 writel(0, (unsigned int)&pwr->tv_configuration);
527 writel(0, (unsigned int)&pwr->mfc_configuration);
528 writel(0, (unsigned int)&pwr->g3d_configuration);
529 writel(0, (unsigned int)&pwr->lcd1_configuration);
530 writel(0, (unsigned int)&pwr->gps_configuration);
531 writel(0, (unsigned int)&pwr->gps_alive_configuration);
532
533 /* It is necessary to power down core 1 */
534 /* to successfully boot CPU1 in kernel */
535 writel(0, (unsigned int)&pwr->arm_core1_configuration);
536 }
537
538 static void exynos_uart_init(void)
539 {
540 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
541 gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
542 gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
543 gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
544 }
545
546 int exynos_early_init_f(void)
547 {
548 wdt_stop();
549 pmic_reset();
550 board_clock_init();
551 exynos_uart_init();
552 board_power_init();
553
554 return 0;
555 }
556
557 void exynos_reset_lcd(void)
558 {
559 gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
560 gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
561 udelay(10000);
562 gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
563 udelay(10000);
564 gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
565 }
566
567 int lcd_power(void)
568 {
569 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
570 int ret = 0;
571 struct pmic *p = pmic_get("MAX8997_PMIC");
572 if (!p)
573 return -ENODEV;
574
575 if (pmic_probe(p))
576 return 0;
577
578 /* LDO15 voltage: 2.2v */
579 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
580 /* LDO13 voltage: 3.0v */
581 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
582
583 if (ret) {
584 puts("MAX8997 LDO setting error!\n");
585 return -1;
586 }
587 #endif
588 return 0;
589 }
590
591 int mipi_power(void)
592 {
593 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
594 int ret = 0;
595 struct pmic *p = pmic_get("MAX8997_PMIC");
596 if (!p)
597 return -ENODEV;
598
599 if (pmic_probe(p))
600 return 0;
601
602 /* LDO3 voltage: 1.1v */
603 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
604 /* LDO4 voltage: 1.8v */
605 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
606
607 if (ret) {
608 puts("MAX8997 LDO setting error!\n");
609 return -1;
610 }
611 #endif
612 return 0;
613 }
614
615 #ifdef CONFIG_LCD
616 void exynos_lcd_misc_init(vidinfo_t *vid)
617 {
618 #ifdef CONFIG_TIZEN
619 get_tizen_logo_info(vid);
620 #endif
621 #ifdef CONFIG_S6E8AX0
622 s6e8ax0_init();
623 setenv("lcdinfo", "lcd=s6e8ax0");
624 #endif
625 }
626 #endif
"Das U-Boot" Source Tree