2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 * Donghwa Lee <dh09.lee@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/pinmux.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/mipi_dsim.h>
18 #include <asm/arch/watchdog.h>
19 #include <asm/arch/power.h>
20 #include <power/pmic.h>
21 #include <usb/dwc2_udc.h>
22 #include <power/max8997_pmic.h>
23 #include <power/max8997_muic.h>
24 #include <power/battery.h>
25 #include <power/max17042_fg.h>
26 #include <power/pmic.h>
29 #include <usb_mass_storage.h>
33 DECLARE_GLOBAL_DATA_PTR
;
35 unsigned int board_rev
;
37 #ifdef CONFIG_REVISION_TAG
38 u32
get_board_rev(void)
44 static void check_hw_revision(void);
45 struct dwc2_plat_otg_data s5pc210_otg_data
;
50 printf("HW Revision:\t0x%x\n", board_rev
);
55 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
56 static void trats_low_power_mode(void)
58 struct exynos4_clock
*clk
=
59 (struct exynos4_clock
*)samsung_get_base_clock();
60 struct exynos4_power
*pwr
=
61 (struct exynos4_power
*)samsung_get_base_power();
63 /* Power down CORE1 */
64 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
65 writel(0x0, &pwr
->arm_core1_configuration
);
67 /* Change the APLL frequency */
68 /* ENABLE (1 enable) | LOCKED (1 locked) */
70 /* FSEL | MDIV | PDIV | SDIV */
71 /* [27] | [25:16] | [13:8] | [2:0] */
72 writel(0xa0c80604, &clk
->apll_con0
);
74 /* Change CPU0 clock divider */
75 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
76 /* [30:28] | [26:24] | [22:20] | [18:16] */
77 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
78 /* [14:12] | [10:8] | [6:4] | [2:0] */
79 writel(0x00000100, &clk
->div_cpu0
);
81 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
82 while (readl(&clk
->div_stat_cpu0
) & 0x1111111)
85 /* Change clock divider ratio for DMC */
86 /* DMCP_RATIO | DMCD_RATIO */
87 /* [22:20] | [18:16] */
88 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
89 /* [14:12] | [10:8] | [6:4] | [2:0] */
90 writel(0x13113117, &clk
->div_dmc0
);
92 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
93 while (readl(&clk
->div_stat_dmc0
) & 0x11111111)
96 /* Turn off unnecessary power domains */
97 writel(0x0, &pwr
->xxti_configuration
); /* XXTI */
98 writel(0x0, &pwr
->cam_configuration
); /* CAM */
99 writel(0x0, &pwr
->tv_configuration
); /* TV */
100 writel(0x0, &pwr
->mfc_configuration
); /* MFC */
101 writel(0x0, &pwr
->g3d_configuration
); /* G3D */
102 writel(0x0, &pwr
->gps_configuration
); /* GPS */
103 writel(0x0, &pwr
->gps_alive_configuration
); /* GPS_ALIVE */
105 /* Turn off unnecessary clocks */
106 writel(0x0, &clk
->gate_ip_cam
); /* CAM */
107 writel(0x0, &clk
->gate_ip_tv
); /* TV */
108 writel(0x0, &clk
->gate_ip_mfc
); /* MFC */
109 writel(0x0, &clk
->gate_ip_g3d
); /* G3D */
110 writel(0x0, &clk
->gate_ip_image
); /* IMAGE */
111 writel(0x0, &clk
->gate_ip_gps
); /* GPS */
115 int exynos_power_init(void)
117 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
119 struct power_battery
*pb
;
120 struct pmic
*p_fg
, *p_chrg
, *p_muic
, *p_bat
;
123 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
124 * to logical I2C adapter 0
126 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
127 * to logical I2C adapter 1
129 ret
= power_fg_init(I2C_9
);
130 ret
|= power_muic_init(I2C_5
);
131 ret
|= power_bat_init(0);
135 p_fg
= pmic_get("MAX17042_FG");
137 puts("MAX17042_FG: Not found\n");
141 p_chrg
= pmic_get("MAX8997_PMIC");
143 puts("MAX8997_PMIC: Not found\n");
147 p_muic
= pmic_get("MAX8997_MUIC");
149 puts("MAX8997_MUIC: Not found\n");
153 p_bat
= pmic_get("BAT_TRATS");
155 puts("BAT_TRATS: Not found\n");
159 p_fg
->parent
= p_bat
;
160 p_chrg
->parent
= p_bat
;
161 p_muic
->parent
= p_bat
;
163 p_bat
->low_power_mode
= trats_low_power_mode
;
164 p_bat
->pbat
->battery_init(p_bat
, p_fg
, p_chrg
, p_muic
);
167 chrg
= p_muic
->chrg
->chrg_type(p_muic
);
168 debug("CHARGER TYPE: %d\n", chrg
);
170 if (!p_chrg
->chrg
->chrg_bat_present(p_chrg
)) {
171 puts("No battery detected\n");
175 p_fg
->fg
->fg_battery_check(p_fg
, p_bat
);
177 if (pb
->bat
->state
== CHARGE
&& chrg
== CHARGER_USB
)
178 puts("CHARGE Battery !\n");
184 static unsigned int get_hw_revision(void)
190 /* hw_rev[3:0] == GPE1[3:0] */
191 for (i
= 0; i
< 4; i
++) {
192 int pin
= i
+ EXYNOS4_GPIO_E10
;
194 sprintf(str
, "hw_rev%d", i
);
195 gpio_request(pin
, str
);
196 gpio_cfg_pin(pin
, S5P_GPIO_INPUT
);
197 gpio_set_pull(pin
, S5P_GPIO_PULL_NONE
);
202 for (i
= 0; i
< 4; i
++)
203 hwrev
|= (gpio_get_value(EXYNOS4_GPIO_E10
+ i
) << i
);
205 debug("hwrev 0x%x\n", hwrev
);
210 static void check_hw_revision(void)
214 hwrev
= get_hw_revision();
220 #ifdef CONFIG_USB_GADGET
221 static int s5pc210_phy_control(int on
)
226 ret
= pmic_get("max8997-pmic", &dev
);
231 reg
= pmic_reg_read(dev
, MAX8997_REG_SAFEOUTCTRL
);
233 ret
= pmic_reg_write(dev
, MAX8997_REG_SAFEOUTCTRL
, reg
);
235 puts("MAX8997 setting error!\n");
238 reg
= pmic_reg_read(dev
, MAX8997_REG_LDO3CTRL
);
240 ret
= pmic_reg_write(dev
, MAX8997_REG_LDO3CTRL
, reg
);
242 puts("MAX8997 setting error!\n");
245 reg
= pmic_reg_read(dev
, MAX8997_REG_LDO8CTRL
);
247 ret
= pmic_reg_write(dev
, MAX8997_REG_LDO8CTRL
, reg
);
249 puts("MAX8997 setting error!\n");
253 reg
= pmic_reg_read(dev
, MAX8997_REG_LDO8CTRL
);
255 ret
= pmic_reg_write(dev
, MAX8997_REG_LDO8CTRL
, reg
);
257 puts("MAX8997 setting error!\n");
260 reg
= pmic_reg_read(dev
, MAX8997_REG_LDO3CTRL
);
262 ret
= pmic_reg_write(dev
, MAX8997_REG_LDO3CTRL
, reg
);
264 puts("MAX8997 setting error!\n");
267 reg
= pmic_reg_read(dev
, MAX8997_REG_SAFEOUTCTRL
);
269 ret
= pmic_reg_write(dev
, MAX8997_REG_SAFEOUTCTRL
, reg
);
271 puts("MAX8997 setting error!\n");
280 struct dwc2_plat_otg_data s5pc210_otg_data
= {
281 .phy_control
= s5pc210_phy_control
,
282 .regs_phy
= EXYNOS4_USBPHY_BASE
,
283 .regs_otg
= EXYNOS4_USBOTG_BASE
,
284 .usb_phy_ctrl
= EXYNOS4_USBPHY_CONTROL
,
285 .usb_flags
= PHY0_SLEEP
,
288 int board_usb_init(int index
, enum usb_init_type init
)
290 debug("USB_udc_probe\n");
291 return dwc2_udc_probe(&s5pc210_otg_data
);
294 int g_dnl_board_usb_cable_connected(void)
296 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
297 struct pmic
*muic
= pmic_get("MAX8997_MUIC");
301 return !!muic
->chrg
->chrg_type(muic
);
309 static void pmic_reset(void)
311 gpio_direction_output(EXYNOS4_GPIO_X07
, 1);
312 gpio_set_pull(EXYNOS4_GPIO_X27
, S5P_GPIO_PULL_NONE
);
315 static void board_clock_init(void)
317 struct exynos4_clock
*clk
=
318 (struct exynos4_clock
*)samsung_get_base_clock();
320 writel(CLK_SRC_CPU_VAL
, (unsigned int)&clk
->src_cpu
);
321 writel(CLK_SRC_TOP0_VAL
, (unsigned int)&clk
->src_top0
);
322 writel(CLK_SRC_FSYS_VAL
, (unsigned int)&clk
->src_fsys
);
323 writel(CLK_SRC_PERIL0_VAL
, (unsigned int)&clk
->src_peril0
);
325 writel(CLK_DIV_CPU0_VAL
, (unsigned int)&clk
->div_cpu0
);
326 writel(CLK_DIV_CPU1_VAL
, (unsigned int)&clk
->div_cpu1
);
327 writel(CLK_DIV_DMC0_VAL
, (unsigned int)&clk
->div_dmc0
);
328 writel(CLK_DIV_DMC1_VAL
, (unsigned int)&clk
->div_dmc1
);
329 writel(CLK_DIV_LEFTBUS_VAL
, (unsigned int)&clk
->div_leftbus
);
330 writel(CLK_DIV_RIGHTBUS_VAL
, (unsigned int)&clk
->div_rightbus
);
331 writel(CLK_DIV_TOP_VAL
, (unsigned int)&clk
->div_top
);
332 writel(CLK_DIV_FSYS1_VAL
, (unsigned int)&clk
->div_fsys1
);
333 writel(CLK_DIV_FSYS2_VAL
, (unsigned int)&clk
->div_fsys2
);
334 writel(CLK_DIV_FSYS3_VAL
, (unsigned int)&clk
->div_fsys3
);
335 writel(CLK_DIV_PERIL0_VAL
, (unsigned int)&clk
->div_peril0
);
336 writel(CLK_DIV_PERIL3_VAL
, (unsigned int)&clk
->div_peril3
);
338 writel(PLL_LOCKTIME
, (unsigned int)&clk
->apll_lock
);
339 writel(PLL_LOCKTIME
, (unsigned int)&clk
->mpll_lock
);
340 writel(PLL_LOCKTIME
, (unsigned int)&clk
->epll_lock
);
341 writel(PLL_LOCKTIME
, (unsigned int)&clk
->vpll_lock
);
342 writel(APLL_CON1_VAL
, (unsigned int)&clk
->apll_con1
);
343 writel(APLL_CON0_VAL
, (unsigned int)&clk
->apll_con0
);
344 writel(MPLL_CON1_VAL
, (unsigned int)&clk
->mpll_con1
);
345 writel(MPLL_CON0_VAL
, (unsigned int)&clk
->mpll_con0
);
346 writel(EPLL_CON1_VAL
, (unsigned int)&clk
->epll_con1
);
347 writel(EPLL_CON0_VAL
, (unsigned int)&clk
->epll_con0
);
348 writel(VPLL_CON1_VAL
, (unsigned int)&clk
->vpll_con1
);
349 writel(VPLL_CON0_VAL
, (unsigned int)&clk
->vpll_con0
);
351 writel(CLK_GATE_IP_CAM_VAL
, (unsigned int)&clk
->gate_ip_cam
);
352 writel(CLK_GATE_IP_VP_VAL
, (unsigned int)&clk
->gate_ip_tv
);
353 writel(CLK_GATE_IP_MFC_VAL
, (unsigned int)&clk
->gate_ip_mfc
);
354 writel(CLK_GATE_IP_G3D_VAL
, (unsigned int)&clk
->gate_ip_g3d
);
355 writel(CLK_GATE_IP_IMAGE_VAL
, (unsigned int)&clk
->gate_ip_image
);
356 writel(CLK_GATE_IP_LCD0_VAL
, (unsigned int)&clk
->gate_ip_lcd0
);
357 writel(CLK_GATE_IP_LCD1_VAL
, (unsigned int)&clk
->gate_ip_lcd1
);
358 writel(CLK_GATE_IP_FSYS_VAL
, (unsigned int)&clk
->gate_ip_fsys
);
359 writel(CLK_GATE_IP_GPS_VAL
, (unsigned int)&clk
->gate_ip_gps
);
360 writel(CLK_GATE_IP_PERIL_VAL
, (unsigned int)&clk
->gate_ip_peril
);
361 writel(CLK_GATE_IP_PERIR_VAL
, (unsigned int)&clk
->gate_ip_perir
);
362 writel(CLK_GATE_BLOCK_VAL
, (unsigned int)&clk
->gate_block
);
365 static void board_power_init(void)
367 struct exynos4_power
*pwr
=
368 (struct exynos4_power
*)samsung_get_base_power();
371 writel(EXYNOS4_PS_HOLD_CON_VAL
, (unsigned int)&pwr
->ps_hold_control
);
374 writel(0, (unsigned int)&pwr
->cam_configuration
);
375 writel(0, (unsigned int)&pwr
->tv_configuration
);
376 writel(0, (unsigned int)&pwr
->mfc_configuration
);
377 writel(0, (unsigned int)&pwr
->g3d_configuration
);
378 writel(0, (unsigned int)&pwr
->lcd1_configuration
);
379 writel(0, (unsigned int)&pwr
->gps_configuration
);
380 writel(0, (unsigned int)&pwr
->gps_alive_configuration
);
382 /* It is necessary to power down core 1 */
383 /* to successfully boot CPU1 in kernel */
384 writel(0, (unsigned int)&pwr
->arm_core1_configuration
);
387 static void exynos_uart_init(void)
389 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
390 gpio_request(EXYNOS4_GPIO_Y47
, "uart_sel");
391 gpio_set_pull(EXYNOS4_GPIO_Y47
, S5P_GPIO_PULL_UP
);
392 gpio_direction_output(EXYNOS4_GPIO_Y47
, 1);
395 int exynos_early_init_f(void)
406 void exynos_reset_lcd(void)
408 gpio_request(EXYNOS4_GPIO_Y45
, "lcd_reset");
409 gpio_direction_output(EXYNOS4_GPIO_Y45
, 1);
411 gpio_direction_output(EXYNOS4_GPIO_Y45
, 0);
413 gpio_direction_output(EXYNOS4_GPIO_Y45
, 1);
418 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
420 struct pmic
*p
= pmic_get("MAX8997_PMIC");
427 /* LDO15 voltage: 2.2v */
428 ret
|= pmic_reg_write(p
, MAX8997_REG_LDO15CTRL
, 0x1c | EN_LDO
);
429 /* LDO13 voltage: 3.0v */
430 ret
|= pmic_reg_write(p
, MAX8997_REG_LDO13CTRL
, 0x2c | EN_LDO
);
433 puts("MAX8997 LDO setting error!\n");
442 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
444 struct pmic
*p
= pmic_get("MAX8997_PMIC");
451 /* LDO3 voltage: 1.1v */
452 ret
|= pmic_reg_write(p
, MAX8997_REG_LDO3CTRL
, 0x6 | EN_LDO
);
453 /* LDO4 voltage: 1.8v */
454 ret
|= pmic_reg_write(p
, MAX8997_REG_LDO4CTRL
, 0x14 | EN_LDO
);
457 puts("MAX8997 LDO setting error!\n");
465 void exynos_lcd_misc_init(vidinfo_t
*vid
)
468 get_tizen_logo_info(vid
);
470 #ifdef CONFIG_S6E8AX0
472 env_set("lcdinfo", "lcd=s6e8ax0");