board/sandburst/karef/karef.c

   1 /*
   2  *  Copyright (C) 2005 Sandburst Corporation
   3  *  Travis B. Sawyer
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <common.h>
  26 #include <command.h>
  27 #include "karef.h"
  28 #include "karef_version.h"
  29 #include <timestamp.h>
  30 #include <asm/processor.h>
  31 #include <asm/io.h>
  32 #include <spd_sdram.h>
  33 #include <i2c.h>
  34 #include "../common/sb_common.h"
  35 #include "../common/ppc440gx_i2c.h"
  36
  37 void fpga_init (void);
  38
  39 KAREF_BOARD_ID_ST board_id_as[] =
  40 {
  41         {"Undefined"},                       /* Not specified */
  42         {"Kamino Reference Design"},
  43         {"Reserved"},                        /* Reserved for future use */
  44         {"Reserved"},                        /* Reserved for future use */
  45 };
  46
  47 KAREF_BOARD_ID_ST ofem_board_id_as[] =
  48 {
  49         {"Undefined"},
  50         {"1x10 + 10x2"},
  51         {"Reserved"},
  52         {"Reserved"},
  53 };
  54
  55 /*************************************************************************
  56  *  board_early_init_f
  57  *
  58  *  Setup chip selects, initialize the Opto-FPGA, initialize
  59  *  interrupt polarity and triggers.
  60  ************************************************************************/
  61 int board_early_init_f (void)
  62 {
  63         ppc440_gpio_regs_t *gpio_regs;
  64
  65         /* Enable GPIO interrupts */
  66         mtsdr(sdr_pfc0, 0x00103E00);
  67
  68         /* Setup access for LEDs, and system topology info */
  69         gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
  70         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  71         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  72
  73         /* Turn on all the leds for now */
  74         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  75
  76         /*--------------------------------------------------------------------+
  77           | Initialize EBC CONFIG
  78           +-------------------------------------------------------------------*/
  79         mtebc(xbcfg,
  80               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  81               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  82               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  83               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  84               EBC_CFG_PR_32);
  85
  86         /*--------------------------------------------------------------------+
  87           | 1/2 MB FLASH. Initialize bank 0 with default values.
  88           +-------------------------------------------------------------------*/
  89         mtebc(pb0ap,
  90               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  91               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  92               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  93               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  94               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  95               EBC_BXAP_PEN_DISABLED);
  96
  97         mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
  98               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
  99         /*--------------------------------------------------------------------+
 100           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
 101           +-------------------------------------------------------------------*/
 102         mtebc(pb1ap,
 103               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
 104               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 105               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 106               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
 107               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 108               EBC_BXAP_PEN_DISABLED);
 109
 110         mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
 111               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 112
 113         /*--------------------------------------------------------------------+
 114           | Compact Flash, uses 2 Chip Selects (2 & 6)
 115           +-------------------------------------------------------------------*/
 116         mtebc(pb2ap,
 117               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 118               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 119               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 120               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 121               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 122               EBC_BXAP_PEN_DISABLED);
 123
 124         mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 125               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 126
 127         /*--------------------------------------------------------------------+
 128           | KaRef Scan FPGA. Initialize bank 3 with default values.
 129           +-------------------------------------------------------------------*/
 130         mtebc(pb5ap,
 131               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 132               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 133               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 134               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 135               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 136
 137         mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
 138               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 139
 140         /*--------------------------------------------------------------------+
 141           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 142           | Initialize bank 4 with default values.
 143           +-------------------------------------------------------------------*/
 144         mtebc(pb4ap,
 145               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 146               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 147               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 148               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 149               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 150
 151         mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
 152               EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 153
 154         /*--------------------------------------------------------------------+
 155           | OFEM FPGA  Initialize bank 5 with default values.
 156           +-------------------------------------------------------------------*/
 157         mtebc(pb3ap,
 158               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 159               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 160               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 161               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 162               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 163
 164
 165         mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
 166               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 167
 168
 169         /*--------------------------------------------------------------------+
 170           | Compact Flash, uses 2 Chip Selects (2 & 6)
 171           +-------------------------------------------------------------------*/
 172         mtebc(pb6ap,
 173               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 174               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 175               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 176               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 177               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 178               EBC_BXAP_PEN_DISABLED);
 179
 180         mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 181               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 182
 183         /*--------------------------------------------------------------------+
 184           | BME-32. Initialize bank 7 with default values.
 185           +-------------------------------------------------------------------*/
 186         mtebc(pb7ap,
 187               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 188               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 189               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 190               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 191               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 192
 193         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
 194               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 195
 196         /*--------------------------------------------------------------------+
 197          * Setup the interrupt controller polarities, triggers, etc.
 198          +-------------------------------------------------------------------*/
 199         /*
 200          * Because of the interrupt handling rework to handle 440GX interrupts
 201          * with the common code, we needed to change names of the UIC registers.
 202          * Here the new relationship:
 203          *
 204          * U-Boot name  440GX name
 205          * -----------------------
 206          * UIC0         UICB0
 207          * UIC1         UIC0
 208          * UIC2         UIC1
 209          * UIC3         UIC2
 210          */
 211         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 212         mtdcr (uic1er, 0x00000000);     /* disable all */
 213         mtdcr (uic1cr, 0x00000000);     /* all non- critical */
 214         mtdcr (uic1pr, 0xfffffe03);     /* polarity */
 215         mtdcr (uic1tr, 0x01c00000);     /* trigger edge vs level */
 216         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
 217         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 218
 219         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 220         mtdcr (uic2er, 0x00000000);     /* disable all */
 221         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
 222         mtdcr (uic2pr, 0xffffc8ff);     /* polarity */
 223         mtdcr (uic2tr, 0x00ff0000);     /* trigger edge vs level */
 224         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
 225         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 226
 227         mtdcr (uic3sr, 0xffffffff);     /* clear all */
 228         mtdcr (uic3er, 0x00000000);     /* disable all */
 229         mtdcr (uic3cr, 0x00000000);     /* all non-critical */
 230         mtdcr (uic3pr, 0xffff83ff);     /* polarity */
 231         mtdcr (uic3tr, 0x00ff8c0f);     /* trigger edge vs level */
 232         mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
 233         mtdcr (uic3sr, 0xffffffff);     /* clear all */
 234
 235         mtdcr (uic0sr, 0xfc000000);     /* clear all */
 236         mtdcr (uic0er, 0x00000000);     /* disable all */
 237         mtdcr (uic0cr, 0x00000000);     /* all non-critical */
 238         mtdcr (uic0pr, 0xfc000000);
 239         mtdcr (uic0tr, 0x00000000);
 240         mtdcr (uic0vr, 0x00000001);
 241
 242         fpga_init();
 243
 244         return 0;
 245 }
 246
 247
 248 /*************************************************************************
 249  *  checkboard
 250  *
 251  *  Dump pertinent info to the console
 252  ************************************************************************/
 253 int checkboard (void)
 254 {
 255         sys_info_t sysinfo;
 256         unsigned char brd_rev, brd_id;
 257         unsigned short sernum;
 258         unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
 259         unsigned char ofem_brd_rev, ofem_brd_id;
 260         KAREF_FPGA_REGS_ST *karef_ps;
 261         OFEM_FPGA_REGS_ST *ofem_ps;
 262
 263         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 264         ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 265
 266         scan_id = (unsigned char)((karef_ps->revision_ul &
 267                                    SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
 268                                   >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
 269
 270         scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
 271                                    >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
 272
 273         brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
 274                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
 275
 276         brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
 277                                  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
 278
 279         ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 280                                       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 281
 282         ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
 283                                        >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
 284
 285         if (0xF != ofem_brd_id) {
 286                 ofem_id = (unsigned char)((ofem_ps->revision_ul &
 287                                            SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
 288                                           >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
 289
 290                 ofem_rev = (unsigned char)((ofem_ps->revision_ul &
 291                                             SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
 292                                            >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
 293         }
 294
 295         get_sys_info (&sysinfo);
 296
 297         sernum = sbcommon_get_serial_number();
 298
 299         printf ("Board: Sandburst Corporation Kamino Reference Design "
 300                 "Serial Number: %d\n", sernum);
 301         printf ("%s\n", KAREF_U_BOOT_REL_STR);
 302
 303         printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 304         if (sbcommon_get_master()) {
 305                 printf("Slot 0 - Master\nSlave board");
 306                 if (sbcommon_secondary_present())
 307                         printf(" present\n");
 308                 else
 309                         printf(" not detected\n");
 310         } else {
 311                 printf("Slot 1 - Slave\n\n");
 312         }
 313
 314         printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
 315         printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
 316         if(0xF != ofem_brd_id) {
 317                 printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
 318                 printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
 319         }
 320
 321         /* Fix the ack in the bme 32 */
 322         udelay(5000);
 323         out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 324         asm("eieio");
 325
 326
 327         return (0);
 328 }
 329
 330 /*************************************************************************
 331  *  misc_init_f
 332  *
 333  *  Initialize I2C bus one to gain access to the fans
 334  ************************************************************************/
 335 int misc_init_f (void)
 336 {
 337         /* Turn on i2c bus 1 */
 338         puts ("I2C1:  ");
 339         i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 340         puts ("ready\n");
 341
 342         /* Turn on fans 3 & 4 */
 343         sbcommon_fans();
 344
 345         return (0);
 346 }
 347
 348 /*************************************************************************
 349  *  misc_init_r
 350  *
 351  *  Do nothing.
 352  ************************************************************************/
 353 int misc_init_r (void)
 354 {
 355         unsigned short sernum;
 356         char envstr[255];
 357         KAREF_FPGA_REGS_ST *karef_ps;
 358         OFEM_FPGA_REGS_ST *ofem_ps;
 359
 360         if(NULL != getenv("secondserial")) {
 361                 puts("secondserial is set, switching to second serial port\n");
 362                 setenv("stderr", "serial1");
 363                 setenv("stdout", "serial1");
 364                 setenv("stdin", "serial1");
 365         }
 366
 367         setenv("ubrelver", KAREF_U_BOOT_REL_STR);
 368
 369         memset(envstr, 0, 255);
 370         sprintf (envstr, "Built %s %s by %s",
 371                  U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 372         setenv("bldstr", envstr);
 373         saveenv();
 374
 375         if( getenv("autorecover")) {
 376                 setenv("autorecover", NULL);
 377                 saveenv();
 378                 sernum = sbcommon_get_serial_number();
 379
 380                 printf("\nSetting up environment for automatic filesystem recovery\n");
 381                 /*
 382                  * Setup default bootargs
 383                  */
 384                 memset(envstr, 0, 255);
 385
 386                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 387                         "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 388                         sernum, sernum);
 389                 setenv("bootargs", envstr);
 390
 391                 /*
 392                  * Setup Default boot command
 393                  */
 394                 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 395                        "fatload ide 0 8100000 pramdisk;"
 396                        "bootm 8000000 8100000");
 397
 398                 printf("Done.  Please type allow the system to continue to boot\n");
 399         }
 400
 401         if( getenv("fakeled")) {
 402                 karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 403                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 404                 ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
 405                 karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
 406                 setenv("bootdelay", "-1");
 407                 saveenv();
 408                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 409         }
 410
 411         return (0);
 412 }
 413
 414 /*************************************************************************
 415  *  ide_set_reset
 416  ************************************************************************/
 417 #ifdef CONFIG_IDE_RESET
 418 void ide_set_reset(int on)
 419 {
 420         KAREF_FPGA_REGS_ST *karef_ps;
 421         /* TODO: ide reset */
 422         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 423
 424         if (on) {
 425                 karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 426         } else {
 427                 karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 428         }
 429 }
 430 #endif /* CONFIG_IDE_RESET */
 431
 432 /*************************************************************************
 433  *  fpga_init
 434  ************************************************************************/
 435 void fpga_init(void)
 436 {
 437         KAREF_FPGA_REGS_ST *karef_ps;
 438         OFEM_FPGA_REGS_ST *ofem_ps;
 439         unsigned char ofem_id;
 440         unsigned long tmp;
 441
 442         /* Ensure we have power all around */
 443         udelay(500);
 444
 445         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 446         tmp =
 447                 SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
 448                 SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
 449                 SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
 450                 SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
 451                 SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
 452                 SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
 453                 SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
 454                 SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
 455                 SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
 456
 457         karef_ps->reset_ul = tmp;
 458
 459         /*
 460          * Wait a bit to allow the ofem fpga to get its brains
 461          */
 462         udelay(5000);
 463
 464         /*
 465          * Check to see if the ofem is there
 466          */
 467         ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 468                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 469         if(0xF != ofem_id) {
 470                 tmp =
 471                         SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
 472                         SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
 473                         SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
 474
 475                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 476                 ofem_ps->reset_ul = tmp;
 477
 478                 ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
 479         }
 480
 481         karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
 482
 483         asm("eieio");
 484
 485         return;
 486 }
 487
 488 int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 489 {
 490         unsigned short sernum;
 491         char envstr[255];
 492
 493         sernum = sbcommon_get_serial_number();
 494
 495         memset(envstr, 0, 255);
 496         /*
 497          * Setup our ip address
 498          */
 499         sprintf(envstr, "10.100.70.%d", sernum);
 500
 501         setenv("ipaddr", envstr);
 502         /*
 503          * Setup the host ip address
 504          */
 505         setenv("serverip", "10.100.17.10");
 506
 507         /*
 508          * Setup default bootargs
 509          */
 510         memset(envstr, 0, 255);
 511
 512         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 513                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
 514                 "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
 515                 "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
 516                 sernum, sernum, sernum);
 517
 518         setenv("bootargs_nfs", envstr);
 519         setenv("bootargs", envstr);
 520
 521         /*
 522          * Setup CF bootargs
 523          */
 524         memset(envstr, 0, 255);
 525
 526         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 527                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 528                 sernum, sernum);
 529
 530         setenv("bootargs_cf", envstr);
 531
 532         /*
 533          * Setup Default boot command
 534          */
 535         setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
 536         setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
 537
 538         /*
 539          * Setup compact flash boot command
 540          */
 541         setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
 542
 543         saveenv();
 544
 545         return(1);
 546 }
 547
 548 int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 549 {
 550         unsigned short sernum;
 551         char envstr[255];
 552
 553         sernum = sbcommon_get_serial_number();
 554
 555         printf("\nSetting up environment for filesystem recovery\n");
 556         /*
 557          * Setup default bootargs
 558          */
 559         memset(envstr, 0, 255);
 560
 561         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 562                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
 563                 sernum, sernum);
 564         setenv("bootargs", envstr);
 565
 566         /*
 567          * Setup Default boot command
 568          */
 569
 570         setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 571                "fatload ide 0 8100000 pramdisk;"
 572                "bootm 8000000 8100000");
 573
 574         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 575                " please type fsrecover.sh<cr>\n");
 576
 577         return(1);
 578 }
 579
 580 U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
 581            "Set environment to factory defaults", NULL);
 582
 583 U_BOOT_CMD(karecover, 1, 1, karefRecover,
 584            "Set environment to allow for fs recovery", NULL);