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[people/ms/u-boot.git] / board / sandburst / metrobox / metrobox.c
1 /*
2 * Copyright (c) 2005
3 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7 #include <config.h>
8 #include <common.h>
9 #include <command.h>
10 #include "metrobox.h"
11 #include "metrobox_version.h"
12 #include <timestamp.h>
13 #include <asm/processor.h>
14 #include <asm/io.h>
15 #include <spd_sdram.h>
16 #include <i2c.h>
17 #include "../common/ppc440gx_i2c.h"
18 #include "../common/sb_common.h"
19 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
20 defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
21 #include <net.h>
22 #endif
23
24 void fpga_init (void);
25
26 METROBOX_BOARD_ID_ST board_id_as[] =
27 { {"Undefined"}, /* Not specified */
28 {"2x10Gb"}, /* 2 ports, 10 GbE */
29 {"20x1Gb"}, /* 20 ports, 1 GbE */
30 {"Reserved"}, /* Reserved for future use */
31 };
32
33 /*************************************************************************
34 * board_early_init_f
35 *
36 * Setup chip selects, initialize the Opto-FPGA, initialize
37 * interrupt polarity and triggers.
38 ************************************************************************/
39 int board_early_init_f (void)
40 {
41 ppc440_gpio_regs_t *gpio_regs;
42
43 /* Enable GPIO interrupts */
44 mtsdr(SDR0_PFC0, 0x00103E00);
45
46 /* Setup access for LEDs, and system topology info */
47 gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
48 gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
49 gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
50
51 /* Turn on all the leds for now */
52 gpio_regs->out = SBCOMMON_GPIO_LEDS;
53
54 /*--------------------------------------------------------------------+
55 | Initialize EBC CONFIG
56 +-------------------------------------------------------------------*/
57 mtebc(EBC0_CFG,
58 EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
59 EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
60 EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
61 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
62 EBC_CFG_PR_32);
63
64 /*--------------------------------------------------------------------+
65 | 1/2 MB FLASH. Initialize bank 0 with default values.
66 +-------------------------------------------------------------------*/
67 mtebc(PB0AP,
68 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
69 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
70 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
71 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
72 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
73 EBC_BXAP_PEN_DISABLED);
74
75 mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
76 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
77 /*--------------------------------------------------------------------+
78 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
79 +-------------------------------------------------------------------*/
80 mtebc(PB1AP,
81 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
82 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
83 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
84 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
85 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
86 EBC_BXAP_PEN_DISABLED);
87
88 mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
89 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
90
91 /*--------------------------------------------------------------------+
92 | Compact Flash, uses 2 Chip Selects (2 & 6)
93 +-------------------------------------------------------------------*/
94 mtebc(PB2AP,
95 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
96 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
97 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
98 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
99 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
100 EBC_BXAP_PEN_DISABLED);
101
102 mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
103 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
104
105 /*--------------------------------------------------------------------+
106 | OPTO & OFEM FPGA. Initialize bank 3 with default values.
107 +-------------------------------------------------------------------*/
108 mtebc(PB3AP,
109 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
110 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
111 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
112 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
113 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
114
115 mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
116 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
117
118 /*--------------------------------------------------------------------+
119 | MAC A for metrobox
120 | MAC A & B for Kamino. OFEM FPGA decodes the addresses
121 | Initialize bank 4 with default values.
122 +-------------------------------------------------------------------*/
123 mtebc(PB4AP,
124 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
125 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
126 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
127 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
128 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
129
130 mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
131 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
132
133 /*--------------------------------------------------------------------+
134 | Metrobox MAC B Initialize bank 5 with default values.
135 | KA REF FPGA Initialize bank 5 with default values.
136 +-------------------------------------------------------------------*/
137 mtebc(PB5AP,
138 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
139 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
140 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
141 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
142 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
143
144 mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) |
145 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
146
147 /*--------------------------------------------------------------------+
148 | Compact Flash, uses 2 Chip Selects (2 & 6)
149 +-------------------------------------------------------------------*/
150 mtebc(PB6AP,
151 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
152 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
153 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
154 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
155 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
156 EBC_BXAP_PEN_DISABLED);
157
158 mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
159 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
160
161 /*--------------------------------------------------------------------+
162 | BME-32. Initialize bank 7 with default values.
163 +-------------------------------------------------------------------*/
164 mtebc(PB7AP,
165 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
166 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
167 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
168 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
169 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
170
171 mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
172 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
173
174 /*--------------------------------------------------------------------+
175 * Setup the interrupt controller polarities, triggers, etc.
176 +-------------------------------------------------------------------*/
177 /*
178 * Because of the interrupt handling rework to handle 440GX interrupts
179 * with the common code, we needed to change names of the UIC registers.
180 * Here the new relationship:
181 *
182 * U-Boot name 440GX name
183 * -----------------------
184 * UIC0 UICB0
185 * UIC1 UIC0
186 * UIC2 UIC1
187 * UIC3 UIC2
188 */
189 mtdcr (UIC1SR, 0xffffffff); /* clear all */
190 mtdcr (UIC1ER, 0x00000000); /* disable all */
191 mtdcr (UIC1CR, 0x00000000); /* all non- critical */
192 mtdcr (UIC1PR, 0xfffffe03); /* polarity */
193 mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
194 mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
195 mtdcr (UIC1SR, 0xffffffff); /* clear all */
196
197 mtdcr (UIC2SR, 0xffffffff); /* clear all */
198 mtdcr (UIC2ER, 0x00000000); /* disable all */
199 mtdcr (UIC2CR, 0x00000000); /* all non-critical */
200 mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
201 mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
202 mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
203 mtdcr (UIC2SR, 0xffffffff); /* clear all */
204
205 mtdcr (UIC3SR, 0xffffffff); /* clear all */
206 mtdcr (UIC3ER, 0x00000000); /* disable all */
207 mtdcr (UIC3CR, 0x00000000); /* all non-critical */
208 mtdcr (UIC3PR, 0xffff83ff); /* polarity */
209 mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
210 mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
211 mtdcr (UIC3SR, 0xffffffff); /* clear all */
212
213 mtdcr (UIC0SR, 0xfc000000); /* clear all */
214 mtdcr (UIC0ER, 0x00000000); /* disable all */
215 mtdcr (UIC0CR, 0x00000000); /* all non-critical */
216 mtdcr (UIC0PR, 0xfc000000);
217 mtdcr (UIC0TR, 0x00000000);
218 mtdcr (UIC0VR, 0x00000001);
219
220 fpga_init();
221
222 return 0;
223 }
224
225 /*************************************************************************
226 * checkboard
227 *
228 * Dump pertinent info to the console
229 ************************************************************************/
230 int checkboard (void)
231 {
232 sys_info_t sysinfo;
233 unsigned char brd_rev, brd_id;
234 unsigned short sernum;
235 unsigned char opto_rev, opto_id;
236 OPTO_FPGA_REGS_ST *opto_ps;
237
238 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
239
240 opto_rev = (unsigned char)((opto_ps->revision_ul &
241 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
242 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
243
244 opto_id = (unsigned char)((opto_ps->revision_ul &
245 SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
246 >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
247
248 brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
249 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
250 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
251
252 brd_id = (unsigned char)((opto_ps->boardinfo_ul &
253 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
254 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
255
256 get_sys_info (&sysinfo);
257
258 sernum = sbcommon_get_serial_number();
259 printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
260 printf ("%s\n", METROBOX_U_BOOT_REL_STR);
261
262 printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
263 if (sbcommon_get_master()) {
264 printf("Slot 0 - Master\nSlave board");
265 if (sbcommon_secondary_present())
266 printf(" present\n");
267 else
268 printf(" not detected\n");
269 } else {
270 printf("Slot 1 - Slave\n\n");
271 }
272
273 printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
274 printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name);
275
276 /* Fix the ack in the bme 32 */
277 udelay(5000);
278 out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
279 asm("eieio");
280
281
282 return (0);
283 }
284
285 /*************************************************************************
286 * misc_init_f
287 *
288 * Initialize I2C bus one to gain access to the fans
289 ************************************************************************/
290 int misc_init_f (void)
291 {
292 /* Turn on i2c bus 1 */
293 puts ("I2C1: ");
294 i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
295 puts ("ready\n");
296
297 /* Turn on fans */
298 sbcommon_fans();
299
300 return (0);
301 }
302
303 /*************************************************************************
304 * misc_init_r
305 *
306 * Do nothing.
307 ************************************************************************/
308 int misc_init_r (void)
309 {
310 unsigned short sernum;
311 char envstr[255];
312 uchar enetaddr[6];
313 unsigned char opto_rev;
314 OPTO_FPGA_REGS_ST *opto_ps;
315
316 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
317
318 if(NULL != getenv("secondserial")) {
319 puts("secondserial is set, switching to second serial port\n");
320 setenv("stderr", "serial1");
321 setenv("stdout", "serial1");
322 setenv("stdin", "serial1");
323 }
324
325 setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
326
327 memset(envstr, 0, 255);
328 sprintf (envstr, "Built %s %s by %s",
329 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
330 setenv("bldstr", envstr);
331 saveenv();
332
333 if( getenv("autorecover")) {
334 setenv("autorecover", NULL);
335 saveenv();
336 sernum = sbcommon_get_serial_number();
337
338 printf("\nSetting up environment for automatic filesystem recovery\n");
339 /*
340 * Setup default bootargs
341 */
342 memset(envstr, 0, 255);
343 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
344 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
345 sernum, sernum);
346 setenv("bootargs", envstr);
347
348 /*
349 * Setup Default boot command
350 */
351 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
352 "fatload ide 0 8100000 pramdisk;"
353 "bootm 8000000 8100000");
354
355 printf("Done. Please type allow the system to continue to boot\n");
356 }
357
358 if( getenv("fakeled")) {
359 setenv("bootdelay", "-1");
360 saveenv();
361 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
362 opto_rev = (unsigned char)((opto_ps->revision_ul &
363 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
364 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
365
366 if(0x12 <= opto_rev) {
367 opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
368 }
369 }
370
371 #ifdef CONFIG_HAS_ETH0
372 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
373 board_get_enetaddr(0, enetaddr);
374 eth_setenv_enetaddr("ethaddr", enetaddr);
375 }
376 #endif
377
378 #ifdef CONFIG_HAS_ETH1
379 if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
380 board_get_enetaddr(1, enetaddr);
381 eth_setenv_enetaddr("eth1addr", enetaddr);
382 }
383 #endif
384
385 #ifdef CONFIG_HAS_ETH2
386 if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
387 board_get_enetaddr(2, enetaddr);
388 eth_setenv_enetaddr("eth2addr", enetaddr);
389 }
390 #endif
391
392 #ifdef CONFIG_HAS_ETH3
393 if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
394 board_get_enetaddr(3, enetaddr);
395 eth_setenv_enetaddr("eth3addr", enetaddr);
396 }
397 #endif
398
399 return (0);
400 }
401
402 /*************************************************************************
403 * ide_set_reset
404 ************************************************************************/
405 #ifdef CONFIG_IDE_RESET
406 void ide_set_reset(int on)
407 {
408 OPTO_FPGA_REGS_ST *opto_ps;
409 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
410
411 if (on) { /* assert RESET */
412 opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
413 } else { /* release RESET */
414 opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
415 }
416 }
417 #endif /* CONFIG_IDE_RESET */
418
419 /*************************************************************************
420 * fpga_init
421 ************************************************************************/
422 void fpga_init(void)
423 {
424 OPTO_FPGA_REGS_ST *opto_ps;
425 unsigned char opto_rev;
426 unsigned long tmp;
427
428 /* Ensure we have power all around */
429 udelay(500);
430
431 /*
432 * Take appropriate hw bits out of reset
433 */
434 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
435
436 tmp =
437 SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
438 SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
439 SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
440 SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
441 SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
442 SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
443 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
444 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
445 SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
446 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
447 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
448 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
449 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
450 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
451 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
452 SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
453 SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
454 SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
455 opto_ps->reset_ul = tmp;
456 /*
457 * Turn on the 'Slow Blink' for the System Error Led.
458 * Ensure FPGA rev is up to at least rev 0x12
459 */
460 opto_rev = (unsigned char)((opto_ps->revision_ul &
461 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
462 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
463 if(0x12 <= opto_rev) {
464 opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
465 }
466
467 asm("eieio");
468
469 return;
470 }
471
472 int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
473 {
474 unsigned short sernum;
475 char envstr[255];
476
477 sernum = sbcommon_get_serial_number();
478
479 memset(envstr, 0, 255);
480 /*
481 * Setup our ip address
482 */
483 sprintf(envstr, "10.100.60.%d", sernum);
484
485 setenv("ipaddr", envstr);
486 /*
487 * Setup the host ip address
488 */
489 setenv("serverip", "10.100.17.10");
490
491 /*
492 * Setup default bootargs
493 */
494 memset(envstr, 0, 255);
495
496 sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
497 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
498 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
499 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
500 sernum, sernum, sernum);
501
502 setenv("bootargs_nfs", envstr);
503 setenv("bootargs", envstr);
504
505 /*
506 * Setup CF bootargs
507 */
508 memset(envstr, 0, 255);
509 sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
510 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
511 sernum, sernum);
512
513 setenv("bootargs_cf", envstr);
514
515 /*
516 * Setup Default boot command
517 */
518 setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
519 setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
520
521 /*
522 * Setup compact flash boot command
523 */
524 setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
525
526 saveenv();
527
528
529 return(1);
530 }
531
532 int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
533 {
534 unsigned short sernum;
535 char envstr[255];
536
537 sernum = sbcommon_get_serial_number();
538
539 printf("\nSetting up environment for filesystem recovery\n");
540 /*
541 * Setup default bootargs
542 */
543 memset(envstr, 0, 255);
544 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
545 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
546 sernum, sernum);
547
548 setenv("bootargs", envstr);
549
550 /*
551 * Setup Default boot command
552 */
553 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
554 "fatload ide 0 8100000 pramdisk;"
555 "bootm 8000000 8100000");
556
557 printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
558 " please type fsrecover.sh<cr>\n");
559
560 return(1);
561 }
562
563 U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
564 "Set environment to factory defaults", "");
565
566 U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
567 "Set environment to allow for fs recovery", "");
"Das U-Boot" Source Tree