board/sandpoint/early_init.S

   1 /*
   2  * (C) Copyright 2001
   3  * Thomas Koeller, tkoeller@gmx.net
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __ASSEMBLY__
  25 #define __ASSEMBLY__    1
  26 #endif
  27
  28 #include <config.h>
  29 #include <asm/processor.h>
  30 #include <mpc824x.h>
  31 #include <ppc_asm.tmpl>
  32
  33 #if defined(USE_DINK32)
  34   /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
  35   #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
  36 #else
  37   #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
  38 #endif
  39
  40         .text
  41
  42         /* Values to program into memory controller registers */
  43 tbl:    .long   MCCR1, MCCR1VAL
  44         .long   MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
  45         .long   MCCR3
  46         .long   (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
  47                 (CFG_REFREC << MCCR3_REFREC_SHIFT) | \
  48                 (CFG_RDLAT  << MCCR3_RDLAT_SHIFT)
  49         .long   MCCR4
  50         .long   (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
  51                 (CFG_REGISTERD_TYPE_BUFFER << 20) | \
  52                 (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
  53                 ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
  54                 (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
  55                 (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
  56                 ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
  57         .long   MSAR1
  58         .long   (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
  59                 (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
  60                 (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  61                 (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  62         .long   EMSAR1
  63         .long   (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
  64                 (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
  65                 (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  66                 (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  67         .long   MSAR2
  68         .long   (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
  69                 (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
  70                 (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  71                 (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  72         .long   EMSAR2
  73         .long   (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
  74                 (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
  75                 (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  76                 (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  77         .long   MEAR1
  78         .long   (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
  79                 (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
  80                 (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  81                 (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  82         .long   EMEAR1
  83         .long   (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
  84                 (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
  85                 (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  86                 (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  87         .long   MEAR2
  88         .long   (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
  89                 (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
  90                 (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  91                 (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  92         .long   EMEAR2
  93         .long   (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
  94                 (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
  95                 (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  96                 (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  97         .long   0
  98
  99
 100         /*
 101          * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
 102          * must be done in assembly, since we have no stack at this point.
 103          */
 104         .global early_init_f
 105 early_init_f:
 106         mflr    r10
 107
 108         /* basic memory controller configuration */
 109         lis     r3, CONFIG_ADDR_HIGH
 110         lis     r4, CONFIG_DATA_HIGH
 111         bl      lab
 112 lab:    mflr    r5
 113         lwzu    r0, tbl - lab(r5)
 114 loop:   lwz     r1, 4(r5)
 115         stwbrx  r0, 0, r3
 116         eieio
 117         stwbrx  r1, 0, r4
 118         eieio
 119         lwzu    r0, 8(r5)
 120         cmpli   cr0, 0, r0, 0
 121         bne     cr0, loop
 122
 123         /* set bank enable bits */
 124         lis     r0, MBER@h
 125         ori     r0, 0, MBER@l
 126         li      r1, CFG_BANK_ENABLE
 127         stwbrx  r0, 0, r3
 128         eieio
 129         stb     r1, 0(r4)
 130         eieio
 131
 132         /* delay loop */
 133         lis     r0, 0x0003
 134         mtctr   r0
 135 delay:  bdnz    delay
 136
 137         /* enable memory controller */
 138         lis     r0, MCCR1@h
 139         ori     r0, 0, MCCR1@l
 140         stwbrx  r0, 0, r3
 141         eieio
 142         lwbrx   r0, 0, r4
 143         oris    r0, 0, MCCR1_MEMGO@h
 144         stwbrx  r0, 0, r4
 145         eieio
 146
 147         /* set up stack pointer */
 148         lis     r1, CFG_INIT_SP_OFFSET@h
 149         ori     r1, r1, CFG_INIT_SP_OFFSET@l
 150
 151         mtlr    r10
 152         blr