2 * sbc8349.c -- WindRiver SBC8349 board support.
3 * Copyright (c) 2006-2007 Wind River Systems, Inc.
5 * Paul Gortmaker <paul.gortmaker@windriver.com>
6 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/mpc8349_pci.h>
16 #include <spd_sdram.h>
18 #if defined(CONFIG_OF_LIBFDT)
22 DECLARE_GLOBAL_DATA_PTR
;
24 int fixed_sdram(void);
25 void sdram_init(void);
27 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
28 void ddr_enable_ecc(unsigned int dram_size
);
31 #ifdef CONFIG_BOARD_EARLY_INIT_F
32 int board_early_init_f (void)
38 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
42 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
45 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
)im
)
48 /* DDR SDRAM - Main SODIMM */
49 im
->sysconf
.ddrlaw
[0].bar
= CONFIG_SYS_DDR_BASE
& LAWBAR_BAR
;
50 #if defined(CONFIG_SPD_EEPROM)
53 msize
= fixed_sdram();
56 * Initialize SDRAM if it is on local bus.
60 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
62 * Initialize and enable DDR ECC.
64 ddr_enable_ecc(msize
* 1024 * 1024);
66 /* set total bus SDRAM size(bytes) -- DDR */
67 gd
->ram_size
= msize
* 1024 * 1024;
72 #if !defined(CONFIG_SPD_EEPROM)
73 /*************************************************************************
74 * fixed sdram init -- doesn't use serial presence detect.
75 ************************************************************************/
78 volatile immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
79 u32 msize
= CONFIG_SYS_DDR_SIZE
;
80 u32 ddr_size
= msize
<< 20; /* DDR size in bytes */
81 u32 ddr_size_log2
= __ilog2(msize
);
83 im
->sysconf
.ddrlaw
[0].bar
= CONFIG_SYS_DDR_SDRAM_BASE
& 0xfffff000;
84 im
->sysconf
.ddrlaw
[0].ar
= LAWAR_EN
| ((ddr_size_log2
- 1) & LAWAR_SIZE
);
86 #if (CONFIG_SYS_DDR_SIZE != 256)
87 #warning Currently any ddr size other than 256 is not supported
90 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
91 #warning Chip select bounds is only configurable in 16MB increments
93 im
->ddr
.csbnds
[2].csbnds
=
94 ((CONFIG_SYS_DDR_SDRAM_BASE
>> CSBNDS_SA_SHIFT
) & CSBNDS_SA
) |
95 (((CONFIG_SYS_DDR_SDRAM_BASE
+ ddr_size
- 1) >>
96 CSBNDS_EA_SHIFT
) & CSBNDS_EA
);
97 im
->ddr
.cs_config
[2] = CONFIG_SYS_DDR_CS2_CONFIG
;
99 /* currently we use only one CS, so disable the other banks */
100 im
->ddr
.cs_config
[0] = 0;
101 im
->ddr
.cs_config
[1] = 0;
102 im
->ddr
.cs_config
[3] = 0;
104 im
->ddr
.timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
105 im
->ddr
.timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
109 #if defined(CONFIG_DDR_2T_TIMING)
112 | SDRAM_CFG_SDRAM_TYPE_DDR1
;
113 #if defined (CONFIG_DDR_32BIT)
114 /* for 32-bit mode burst length is 8 */
115 im
->ddr
.sdram_cfg
|= (SDRAM_CFG_32_BE
| SDRAM_CFG_8_BE
);
117 im
->ddr
.sdram_mode
= CONFIG_SYS_DDR_MODE
;
119 im
->ddr
.sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
122 /* enable DDR controller */
123 im
->ddr
.sdram_cfg
|= SDRAM_CFG_MEM_EN
;
126 #endif/*!CONFIG_SYS_SPD_EEPROM*/
129 int checkboard (void)
131 puts("Board: Wind River SBC834x\n");
136 * if board is fitted with SDRAM
138 #if defined(CONFIG_SYS_BR2_PRELIM) \
139 && defined(CONFIG_SYS_OR2_PRELIM) \
140 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
141 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
143 * Initialize SDRAM memory on the Local Bus.
146 void sdram_init(void)
148 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
149 volatile fsl_lbc_t
*lbc
= &immap
->im_lbc
;
150 uint
*sdram_addr
= (uint
*)CONFIG_SYS_LBC_SDRAM_BASE
;
152 puts("\n SDRAM on Local Bus: ");
153 print_size (CONFIG_SYS_LBC_SDRAM_SIZE
* 1024 * 1024, "\n");
156 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
159 /* setup mtrpt, lsrt and lbcr for LB bus */
160 lbc
->lbcr
= CONFIG_SYS_LBC_LBCR
;
161 lbc
->mrtpr
= CONFIG_SYS_LBC_MRTPR
;
162 lbc
->lsrt
= CONFIG_SYS_LBC_LSRT
;
166 * Configure the SDRAM controller Machine Mode Register.
168 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_5
; /* 0x40636733; normal operation */
170 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_1
; /* 0x68636733; precharge all the banks */
175 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_2
; /* 0x48636733; auto refresh */
202 /* 0x58636733; mode register write operation */
203 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_4
;
208 lbc
->lsdmr
= CONFIG_SYS_LBC_LSDMR_5
; /* 0x40636733; normal operation */
214 void sdram_init(void)
216 puts(" SDRAM on Local Bus: Disabled in config\n");
220 #if defined(CONFIG_OF_BOARD_SETUP)
221 int ft_board_setup(void *blob
, bd_t
*bd
)
223 ft_cpu_setup(blob
, bd
);
225 ft_pci_setup(blob
, bd
);