board/sbc8548/sbc8548.c

   1 /*
   2  * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
   3  *
   4  * Copyright 2007 Embedded Specialties, Inc.
   5  *
   6  * Copyright 2004, 2007 Freescale Semiconductor.
   7  *
   8  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <pci.h>
  31 #include <asm/processor.h>
  32 #include <asm/immap_85xx.h>
  33 #include <asm/fsl_pci.h>
  34 #include <asm/fsl_ddr_sdram.h>
  35 #include <asm/fsl_serdes.h>
  36 #include <spd_sdram.h>
  37 #include <netdev.h>
  38 #include <tsec.h>
  39 #include <miiphy.h>
  40 #include <libfdt.h>
  41 #include <fdt_support.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 void local_bus_init(void);
  46
  47 int board_early_init_f (void)
  48 {
  49         return 0;
  50 }
  51
  52 int checkboard (void)
  53 {
  54         volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  55         volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
  56
  57         printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
  58                         in_8(rev) >> 4);
  59
  60         /*
  61          * Initialize local bus.
  62          */
  63         local_bus_init ();
  64
  65         out_be32(&ecm->eedr, 0xffffffff);       /* clear ecm errors */
  66         out_be32(&ecm->eeer, 0xffffffff);       /* enable ecm errors */
  67         return 0;
  68 }
  69
  70 /*
  71  * Initialize Local Bus
  72  */
  73 void
  74 local_bus_init(void)
  75 {
  76         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  77         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  78
  79         uint clkdiv;
  80         sys_info_t sysinfo;
  81
  82         get_sys_info(&sysinfo);
  83         clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
  84
  85         out_be32(&gur->lbiuiplldcr1, 0x00078080);
  86         if (clkdiv == 16) {
  87                 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
  88         } else if (clkdiv == 8) {
  89                 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
  90         } else if (clkdiv == 4) {
  91                 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
  92         }
  93
  94         setbits_be32(&lbc->lcrr, 0x00030000);
  95
  96         asm("sync;isync;msync");
  97
  98         out_be32(&lbc->ltesr, 0xffffffff);      /* Clear LBC error IRQs */
  99         out_be32(&lbc->lteir, 0xffffffff);      /* Enable LBC error IRQs */
 100 }
 101
 102 /*
 103  * Initialize SDRAM memory on the Local Bus.
 104  */
 105 void lbc_sdram_init(void)
 106 {
 107 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
 108
 109         uint idx;
 110         const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
 111         volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 112         uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 113         uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
 114
 115         puts("    SDRAM: ");
 116
 117         print_size(size, "\n");
 118
 119         /*
 120          * Setup SDRAM Base and Option Registers
 121          */
 122         set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 123         set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 124         set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
 125         set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
 126
 127         out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
 128         asm("msync");
 129
 130         out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
 131         out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 132         asm("msync");
 133
 134         /*
 135          * Issue PRECHARGE ALL command.
 136          */
 137         out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
 138         asm("sync;msync");
 139         *sdram_addr = 0xff;
 140         ppcDcbf((unsigned long) sdram_addr);
 141         *sdram_addr2 = 0xff;
 142         ppcDcbf((unsigned long) sdram_addr2);
 143         udelay(100);
 144
 145         /*
 146          * Issue 8 AUTO REFRESH commands.
 147          */
 148         for (idx = 0; idx < 8; idx++) {
 149                 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
 150                 asm("sync;msync");
 151                 *sdram_addr = 0xff;
 152                 ppcDcbf((unsigned long) sdram_addr);
 153                 *sdram_addr2 = 0xff;
 154                 ppcDcbf((unsigned long) sdram_addr2);
 155                 udelay(100);
 156         }
 157
 158         /*
 159          * Issue 8 MODE-set command.
 160          */
 161         out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
 162         asm("sync;msync");
 163         *sdram_addr = 0xff;
 164         ppcDcbf((unsigned long) sdram_addr);
 165         *sdram_addr2 = 0xff;
 166         ppcDcbf((unsigned long) sdram_addr2);
 167         udelay(100);
 168
 169         /*
 170          * Issue RFEN command.
 171          */
 172         out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
 173         asm("sync;msync");
 174         *sdram_addr = 0xff;
 175         ppcDcbf((unsigned long) sdram_addr);
 176         *sdram_addr2 = 0xff;
 177         ppcDcbf((unsigned long) sdram_addr2);
 178         udelay(200);    /* Overkill. Must wait > 200 bus cycles */
 179
 180 #endif  /* enable SDRAM init */
 181 }
 182
 183 #if defined(CONFIG_SYS_DRAM_TEST)
 184 int
 185 testdram(void)
 186 {
 187         uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
 188         uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 189         uint *p;
 190
 191         printf("Testing DRAM from 0x%08x to 0x%08x\n",
 192                CONFIG_SYS_MEMTEST_START,
 193                CONFIG_SYS_MEMTEST_END);
 194
 195         printf("DRAM test phase 1:\n");
 196         for (p = pstart; p < pend; p++)
 197                 *p = 0xaaaaaaaa;
 198
 199         for (p = pstart; p < pend; p++) {
 200                 if (*p != 0xaaaaaaaa) {
 201                         printf ("DRAM test fails at: %08x\n", (uint) p);
 202                         return 1;
 203                 }
 204         }
 205
 206         printf("DRAM test phase 2:\n");
 207         for (p = pstart; p < pend; p++)
 208                 *p = 0x55555555;
 209
 210         for (p = pstart; p < pend; p++) {
 211                 if (*p != 0x55555555) {
 212                         printf ("DRAM test fails at: %08x\n", (uint) p);
 213                         return 1;
 214                 }
 215         }
 216
 217         printf("DRAM test passed.\n");
 218         return 0;
 219 }
 220 #endif
 221
 222 #if !defined(CONFIG_SPD_EEPROM)
 223 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
 224 /*************************************************************************
 225  *  fixed_sdram init -- doesn't use serial presence detect.
 226  *  assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
 227  ************************************************************************/
 228 phys_size_t fixed_sdram(void)
 229 {
 230         volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 231
 232         out_be32(&ddr->cs0_bnds, 0x0000007f);
 233         out_be32(&ddr->cs1_bnds, 0x008000ff);
 234         out_be32(&ddr->cs2_bnds, 0x00000000);
 235         out_be32(&ddr->cs3_bnds, 0x00000000);
 236         out_be32(&ddr->cs0_config, 0x80010101);
 237         out_be32(&ddr->cs1_config, 0x80010101);
 238         out_be32(&ddr->cs2_config, 0x00000000);
 239         out_be32(&ddr->cs3_config, 0x00000000);
 240         out_be32(&ddr->timing_cfg_3, 0x00000000);
 241         out_be32(&ddr->timing_cfg_0, 0x00220802);
 242         out_be32(&ddr->timing_cfg_1, 0x38377322);
 243         out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
 244         out_be32(&ddr->sdram_cfg, 0x4300C000);
 245         out_be32(&ddr->sdram_cfg_2, 0x24401000);
 246         out_be32(&ddr->sdram_mode, 0x23C00542);
 247         out_be32(&ddr->sdram_mode_2, 0x00000000);
 248         out_be32(&ddr->sdram_interval, 0x05080100);
 249         out_be32(&ddr->sdram_md_cntl, 0x00000000);
 250         out_be32(&ddr->sdram_data_init, 0x00000000);
 251         out_be32(&ddr->sdram_clk_cntl, 0x03800000);
 252         asm("sync;isync;msync");
 253         udelay(500);
 254
 255         #if defined (CONFIG_DDR_ECC)
 256           /* Enable ECC checking */
 257           out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
 258         #else
 259           out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
 260         #endif
 261
 262         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 263 }
 264 #endif
 265
 266 #ifdef CONFIG_PCI1
 267 static struct pci_controller pci1_hose;
 268 #endif  /* CONFIG_PCI1 */
 269
 270 #ifdef CONFIG_PCI
 271 void
 272 pci_init_board(void)
 273 {
 274         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 275         int first_free_busno = 0;
 276
 277 #ifdef CONFIG_PCI1
 278         struct fsl_pci_info pci_info;
 279         u32 devdisr = in_be32(&gur->devdisr);
 280         u32 pordevsr = in_be32(&gur->pordevsr);
 281         u32 porpllsr = in_be32(&gur->porpllsr);
 282
 283         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 284                 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
 285                 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
 286                 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 287                 uint pci_speed = CONFIG_SYS_CLK_FREQ;   /* get_clock_freq() */
 288
 289                 printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
 290                         (pci_32) ? 32 : 64,
 291                         (pci_speed == 33000000) ? "33" :
 292                         (pci_speed == 66000000) ? "66" : "unknown",
 293                         pci_clk_sel ? "sync" : "async",
 294                         pci_arb ? "arbiter" : "external-arbiter");
 295
 296                 SET_STD_PCI_INFO(pci_info, 1);
 297                 set_next_law(pci_info.mem_phys,
 298                         law_size_bits(pci_info.mem_size), pci_info.law);
 299                 set_next_law(pci_info.io_phys,
 300                         law_size_bits(pci_info.io_size), pci_info.law);
 301
 302                 first_free_busno = fsl_pci_init_port(&pci_info,
 303                                         &pci1_hose, first_free_busno);
 304         } else {
 305                 printf("PCI: disabled\n");
 306         }
 307
 308         puts("\n");
 309 #else
 310         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 311 #endif
 312
 313         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
 314
 315         fsl_pcie_init_board(first_free_busno);
 316 }
 317 #endif
 318
 319 int board_eth_init(bd_t *bis)
 320 {
 321         tsec_standard_init(bis);
 322         pci_eth_init(bis);
 323         return 0;       /* otherwise cpu_eth_init gets run */
 324 }
 325
 326 int last_stage_init(void)
 327 {
 328         return 0;
 329 }
 330
 331 #if defined(CONFIG_OF_BOARD_SETUP)
 332 void ft_board_setup(void *blob, bd_t *bd)
 333 {
 334         ft_cpu_setup(blob, bd);
 335
 336 #ifdef CONFIG_FSL_PCI_INIT
 337         FT_FSL_PCI_SETUP;
 338 #endif
 339 }
 340 #endif