board/sc520_cdp/sc520_cdp.c

   1 /*
   2  *
   3  * (C) Copyright 2002
   4  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <pci.h>
  27 #include <asm/io.h>
  28 #include <asm/pci.h>
  29 #include <asm/ic/sc520.h>
  30 #include <asm/ic/ali512x.h>
  31 #include <ssi.h>
  32
  33 #undef SC520_CDP_DEBUG
  34
  35 #ifdef  SC520_CDP_DEBUG
  36 #define PRINTF(fmt,args...)     printf (fmt ,##args)
  37 #else
  38 #define PRINTF(fmt,args...)
  39 #endif
  40
  41 /* ------------------------------------------------------------------------- */
  42
  43
  44 /*
  45  * Theory:
  46  * We first set up all IRQs to be non-pci, edge triggered,
  47  * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
  48  * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
  49  * as needed. Whe choose the irqs to gram from a configurable list
  50  * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
  51  * such as 0 thngas will not work)
  52  */
  53
  54 static void irq_init(void)
  55 {
  56         /* disable global interrupt mode */
  57         write_mmcr_byte(SC520_PICICR, 0x40);
  58
  59         /* set all irqs to edge */
  60         write_mmcr_byte(SC520_MPICMODE, 0x00);
  61         write_mmcr_byte(SC520_SL1PICMODE, 0x00);
  62         write_mmcr_byte(SC520_SL2PICMODE, 0x00);
  63
  64         /* active low polarity on PIC interrupt pins,
  65          *  active high polarity on all other irq pins */
  66         write_mmcr_word(SC520_INTPINPOL, 0x0000);
  67
  68         /* set irq number mapping */
  69         write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */
  70         write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
  71         write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
  72         write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */
  73         write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
  74         write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
  75         write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
  76         write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
  77         write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
  78         write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
  79         write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
  80         write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED);      /* disable Synchronius serial INT */
  81         write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
  82         write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
  83         write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
  84         write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
  85         write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
  86
  87         if (CFG_USE_SIO_UART) {
  88                 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
  89                 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
  90                 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3);          /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
  91                 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4);          /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
  92         } else {
  93                 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);         /* Set internal UART2 INT to IRQ4 */
  94                 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);         /* Set internal UART2 INT to IRQ3 */
  95                 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ3 (ISA IRQ3) */
  96                 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ4 (ISA IRQ4) */
  97         }
  98
  99         write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1);             /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
 100         write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5);             /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
 101         write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6);             /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
 102         write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7);             /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
 103         write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8);             /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
 104         write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9);             /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
 105         write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11);            /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
 106         write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12);            /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
 107         write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14);            /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
 108
 109         write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);                /* Map PCI hostbridge INT to NMI */
 110         write_mmcr_word(SC520_ECCMAP, 0x100);                    /* Map SDRAM ECC failure INT to NMI */
 111
 112 }
 113
 114
 115 /* PCI stuff */
 116 static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 117 {
 118         /* a configurable lists of irqs to steal
 119          * when we need one (a board with more pci interrupt pins
 120          * would use a larger table */
 121         static int irq_list[] = {
 122                 CFG_FIRST_PCI_IRQ,
 123                 CFG_SECOND_PCI_IRQ,
 124                 CFG_THIRD_PCI_IRQ,
 125                 CFG_FORTH_PCI_IRQ
 126         };
 127         static int next_irq_index=0;
 128
 129         char tmp_pin;
 130         int pin;
 131
 132         pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
 133         pin = tmp_pin;
 134
 135         pin-=1; /* pci config space use 1-based numbering */
 136         if (-1 == pin) {
 137                 return; /* device use no irq */
 138         }
 139
 140
 141         /* map device number +  pin to a pin on the sc520 */
 142         switch (PCI_DEV(dev)) {
 143         case 20:
 144                 pin+=SC520_PCI_INTA;
 145                 break;
 146
 147         case 19:
 148                 pin+=SC520_PCI_INTB;
 149                 break;
 150
 151         case 18:
 152                 pin+=SC520_PCI_INTC;
 153                 break;
 154
 155         case 17:
 156                 pin+=SC520_PCI_INTD;
 157                 break;
 158
 159         default:
 160                 return;
 161         }
 162
 163         pin&=3; /* wrap around */
 164
 165         if (sc520_pci_ints[pin] == -1) {
 166                 /* re-route one interrupt for us */
 167                 if (next_irq_index > 3) {
 168                         return;
 169                 }
 170                 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
 171                         return;
 172                 }
 173                 next_irq_index++;
 174         }
 175
 176
 177         if (-1 != sc520_pci_ints[pin]) {
 178                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 179                                            sc520_pci_ints[pin]);
 180         }
 181         PRINTF("fixup_irq: device %d pin %c irq %d\n",
 182                PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
 183 }
 184
 185 static struct pci_controller sc520_cdp_hose = {
 186         fixup_irq: pci_sc520_cdp_fixup_irq,
 187 };
 188
 189 void pci_init_board(void)
 190 {
 191         pci_sc520_init(&sc520_cdp_hose);
 192 }
 193
 194
 195 static void silence_uart(int port)
 196 {
 197         outb(0, port+1);
 198 }
 199
 200 void setup_ali_sio(int uart_primary)
 201 {
 202         ali512x_init();
 203
 204         ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0);
 205         ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3);
 206         ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4);
 207         ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3);
 208         ali512x_set_rtc(ALI_DISABLED, 0, 0);
 209         ali512x_set_kbc(ALI_ENABLED, 1, 12);
 210         ali512x_set_cio(ALI_ENABLED);
 211
 212         /* IrDa pins */
 213         ali512x_cio_function(12, 1, 0, 0);
 214         ali512x_cio_function(13, 1, 0, 0);
 215
 216         /* SSI chip select pins */
 217         ali512x_cio_function(14, 0, 0, 0);  /* SSI_CS */
 218         ali512x_cio_function(15, 0, 0, 0);  /* SSI_MV */
 219         ali512x_cio_function(16, 0, 0, 0);  /* SSI_SPI# */
 220
 221         /* Board REV pins */
 222         ali512x_cio_function(20, 0, 0, 1);
 223         ali512x_cio_function(21, 0, 0, 1);
 224         ali512x_cio_function(22, 0, 0, 1);
 225         ali512x_cio_function(23, 0, 0, 1);
 226 }
 227
 228
 229 /* set up the ISA bus timing and system address mappings */
 230 static void bus_init(void)
 231 {
 232
 233         /* set up the GP IO pins */
 234         write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff);     /* set the GPIO pin function 31-16 reg */
 235         write_mmcr_word(SC520_PIOPFS15_0, 0xffff);      /* set the GPIO pin function 15-0 reg */
 236         write_mmcr_byte(SC520_CSPFS, 0xf8);             /* set the CS pin function  reg */
 237         write_mmcr_byte(SC520_CLKSEL, 0x70);
 238
 239
 240         write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */
 241         write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
 242         write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
 243         write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
 244         write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
 245         write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
 246         write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
 247
 248         write_mmcr_word(SC520_BOOTCSCTL, 0x1823);               /* set up timing of BOOTCS */
 249         write_mmcr_word(SC520_ROMCS1CTL, 0x1823);               /* set up timing of ROMCS1 */
 250         write_mmcr_word(SC520_ROMCS2CTL, 0x1823);               /* set up timing of ROMCS2 */
 251
 252         /* adjust the memory map:
 253          * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
 254          * and 256MB to 1G-128k  (0x1000000 - 0x37ffffff) is mapped to PCI mmio
 255          * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
 256
 257
 258         /* SRAM = GPCS3 128k @ d0000-effff*/
 259         write_mmcr_long(SC520_PAR2,  0x4e00400d);
 260
 261         /* IDE0 = GPCS6 1f0-1f7 */
 262         write_mmcr_long(SC520_PAR3,  0x380801f0);
 263
 264         /* IDE1 = GPCS7 3f6 */
 265         write_mmcr_long(SC520_PAR4,  0x3c0003f6);
 266         /* bootcs */
 267         write_mmcr_long(SC520_PAR12, 0x8bffe800);
 268         /* romcs2 */
 269         write_mmcr_long(SC520_PAR13, 0xcbfff000);
 270         /* romcs1 */
 271         write_mmcr_long(SC520_PAR14, 0xabfff800);
 272         /* 680 LEDS */
 273         write_mmcr_long(SC520_PAR15, 0x30000640);
 274
 275         write_mmcr_byte(SC520_ADDDECCTL, 0);
 276
 277         asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
 278
 279         if (CFG_USE_SIO_UART) {
 280                 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
 281                 setup_ali_sio(1);
 282         } else {
 283                 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
 284                 setup_ali_sio(0);
 285                 silence_uart(0x3e8);
 286                 silence_uart(0x2e8);
 287         }
 288
 289 }
 290
 291 /* GPCS usage
 292  * GPCS0       PIO27 (NMI)
 293  * GPCS1       ROMCS1
 294  * GPCS2       ROMCS2
 295  * GPCS3       SRAMCS       PAR2
 296  * GPCS4       unused       PAR3
 297  * GPCS5       unused       PAR4
 298  * GPCS6       IDE
 299  * GPCS7       IDE
 300  */
 301
 302
 303 /* par usage:
 304  * PAR0   legacy_video
 305  * PAR1   PCI ROM mapping
 306  * PAR2   SRAM
 307  * PAR3   IDE
 308  * PAR4   IDE
 309  * PAR5   legacy_video
 310  * PAR6   legacy_video
 311  * PAR7   legacy_video
 312  * PAR8   legacy_video
 313  * PAR9   legacy_video
 314  * PAR10  legacy_video
 315  * PAR11  ISAROM
 316  * PAR12  BOOTCS
 317  * PAR13  ROMCS1
 318  * PAR14  ROMCS2
 319  * PAR15  Port 0x680 LED display
 320  */
 321
 322 /*
 323  * This function should map a chunk of size bytes
 324  * of the system address space to the ISA bus
 325  *
 326  * The function will return the memory address
 327  * as seen by the host (which may very will be the
 328  * same as the bus address)
 329  */
 330 u32 isa_map_rom(u32 bus_addr, int size)
 331 {
 332         u32 par;
 333
 334         PRINTF("isa_map_rom asked to map %d bytes at %x\n",
 335                size, bus_addr);
 336
 337         par = size;
 338         if (par < 0x80000) {
 339                 par = 0x80000;
 340         }
 341         par >>= 12;
 342         par--;
 343         par&=0x7f;
 344         par <<= 18;
 345         par |= (bus_addr>>12);
 346         par |= 0x50000000;
 347
 348         PRINTF ("setting PAR11 to %x\n", par);
 349
 350         /* Map rom 0x10000 with PAR1 */
 351         write_mmcr_long(SC520_PAR11,  par);
 352
 353         return bus_addr;
 354 }
 355
 356 /*
 357  * this function removed any mapping created
 358  * with pci_get_rom_window()
 359  */
 360 void isa_unmap_rom(u32 addr)
 361 {
 362         PRINTF("isa_unmap_rom asked to unmap %x", addr);
 363         if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
 364                 write_mmcr_long(SC520_PAR11, 0);
 365                 PRINTF(" done\n");
 366                 return;
 367         }
 368         PRINTF(" not ours\n");
 369 }
 370
 371 #ifdef CONFIG_PCI
 372 #define PCI_ROM_TEMP_SPACE 0x10000
 373 /*
 374  * This function should map a chunk of size bytes
 375  * of the system address space to the PCI bus,
 376  * suitable to map PCI ROMS (bus address < 16M)
 377  * the function will return the host memory address
 378  * which should be converted into a bus address
 379  * before used to configure the PCI rom address
 380  * decoder
 381  */
 382 u32 pci_get_rom_window(struct pci_controller *hose, int size)
 383 {
 384         u32 par;
 385
 386         par = size;
 387         if (par < 0x80000) {
 388                 par = 0x80000;
 389         }
 390         par >>= 16;
 391         par--;
 392         par&=0x7ff;
 393         par <<= 14;
 394         par |= (PCI_ROM_TEMP_SPACE>>16);
 395         par |= 0x72000000;
 396
 397         PRINTF ("setting PAR1 to %x\n", par);
 398
 399         /* Map rom 0x10000 with PAR1 */
 400         write_mmcr_long(SC520_PAR1,  par);
 401
 402         return PCI_ROM_TEMP_SPACE;
 403 }
 404
 405 /*
 406  * this function removed any mapping created
 407  * with pci_get_rom_window()
 408  */
 409 void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
 410 {
 411         PRINTF("pci_remove_rom_window: %x", addr);
 412         if (addr == PCI_ROM_TEMP_SPACE) {
 413                 write_mmcr_long(SC520_PAR1, 0);
 414                 PRINTF(" done\n");
 415                 return;
 416         }
 417         PRINTF(" not ours\n");
 418
 419 }
 420
 421 /*
 422  * This function is called in order to provide acces to the
 423  * legacy video I/O ports on the PCI bus.
 424  * After this function accesses to I/O ports 0x3b0-0x3bb and
 425  * 0x3c0-0x3df shuld result in transactions on the PCI bus.
 426  *
 427  */
 428 int pci_enable_legacy_video_ports(struct pci_controller *hose)
 429 {
 430         /* Map video memory to 0xa0000*/
 431         write_mmcr_long(SC520_PAR0,  0x7200400a);
 432
 433         /* forward all I/O accesses to PCI */
 434         write_mmcr_byte(SC520_ADDDECCTL,
 435                         read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
 436
 437
 438         /* so we map away all io ports to pci (only way to access pci io
 439          * below 0x400. But then we have to map back the portions that we dont
 440          * use so that the generate cycles on the GPIO bus where the sio and
 441          * ISA slots are connected, this requre the use of several PAR registers
 442          */
 443
 444         /* bring 0x100 - 0x1ef back to ISA using PAR5 */
 445         write_mmcr_long(SC520_PAR5, 0x30ef0100);
 446
 447         /* IDE use 1f0-1f7 */
 448
 449         /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
 450         write_mmcr_long(SC520_PAR6, 0x30ff01f8);
 451
 452         /* com2 use 2f8-2ff */
 453
 454         /* bring 0x300 - 0x3af back to ISA using PAR7 */
 455         write_mmcr_long(SC520_PAR7, 0x30af0300);
 456
 457         /* vga use 3b0-3bb */
 458
 459         /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
 460         write_mmcr_long(SC520_PAR8, 0x300303bc);
 461
 462         /* vga use 3c0-3df */
 463
 464         /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
 465         write_mmcr_long(SC520_PAR9, 0x301503e0);
 466
 467         /* ide use 3f6 */
 468
 469         /* bring 0x3f7  back to ISA using PAR10 */
 470         write_mmcr_long(SC520_PAR10, 0x300003f7);
 471
 472         /* com1 use 3f8-3ff */
 473
 474         return 0;
 475 }
 476 #endif
 477
 478 /*
 479  * Miscelaneous platform dependent initialisations
 480  */
 481
 482 int board_init(void)
 483 {
 484         DECLARE_GLOBAL_DATA_PTR;
 485
 486         init_sc520();
 487         bus_init();
 488         irq_init();
 489
 490         /* max drive current on SDRAM */
 491         write_mmcr_word(SC520_DSCTL, 0x0100);
 492
 493         /* enter debug mode after next reset (only if jumper is also set) */
 494         write_mmcr_byte(SC520_RESCFG, 0x08);
 495         /* configure the software timer to 33.333MHz */
 496         write_mmcr_byte(SC520_SWTMRCFG, 0);
 497         gd->bus_clk = 33333000;
 498
 499         return 0;
 500 }
 501
 502 int dram_init(void)
 503 {
 504         init_sc520_dram();
 505         return 0;
 506 }
 507
 508 void show_boot_progress(int val)
 509 {
 510         outb(val&0xff, 0x80);
 511         outb((val&0xff00)>>8, 0x680);
 512 }
 513
 514
 515 int last_stage_init(void)
 516 {
 517         int minor;
 518         int major;
 519
 520         major = minor = 0;
 521         major |= ali512x_cio_in(23)?2:0;
 522         major |= ali512x_cio_in(22)?1:0;
 523         minor |= ali512x_cio_in(21)?2:0;
 524         minor |= ali512x_cio_in(20)?1:0;
 525
 526         printf("AMD SC520 CDP revision %d.%d\n", major, minor);
 527
 528         return 0;
 529 }
 530
 531
 532 void ssi_chip_select(int dev)
 533 {
 534
 535         /* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
 536         switch (dev) {
 537         case 1: /* SPI EEPROM */
 538                 ali512x_cio_out(16, 0);
 539                 break;
 540
 541         case 2: /* MW EEPROM */
 542                 ali512x_cio_out(15, 1);
 543                 break;
 544
 545         case 3: /* AUX */
 546                 ali512x_cio_out(14, 1);
 547                 break;
 548
 549         case 0:
 550                 ali512x_cio_out(16, 1);
 551                 ali512x_cio_out(15, 0);
 552                 ali512x_cio_out(14, 0);
 553                 break;
 554
 555         default:
 556                 printf("Illegal SSI device requested: %d\n", dev);
 557         }
 558 }
 559
 560
 561 void spi_init_f(void)
 562 {
 563 #ifdef CONFIG_SC520_CDP_USE_SPI
 564         spi_eeprom_probe(1);
 565 #endif
 566 #ifdef CONFIG_SC520_CDP_USE_MW
 567         mw_eeprom_probe(2);
 568 #endif
 569 }
 570
 571 ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
 572 {
 573         int offset;
 574         int i;
 575         ssize_t res;
 576
 577         offset = 0;
 578         for (i=0;i<alen;i++) {
 579                 offset <<= 8;
 580                 offset |= addr[i];
 581         }
 582
 583 #ifdef CONFIG_SC520_CDP_USE_SPI
 584         res = spi_eeprom_read(1, offset, buffer, len);
 585 #endif
 586 #ifdef CONFIG_SC520_CDP_USE_MW
 587         res = mw_eeprom_read(2, offset, buffer, len);
 588 #endif
 589         return res;
 590 }
 591
 592 ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
 593 {
 594         int offset;
 595         int i;
 596         ssize_t res;
 597
 598         offset = 0;
 599         for (i=0;i<alen;i++) {
 600                 offset <<= 8;
 601                 offset |= addr[i];
 602         }
 603
 604 #ifdef CONFIG_SC520_CDP_USE_SPI
 605         res = spi_eeprom_write(1, offset, buffer, len);
 606 #endif
 607 #ifdef CONFIG_SC520_CDP_USE_MW
 608         res = mw_eeprom_write(2, offset, buffer, len);
 609 #endif
 610         return res;
 611 }