board/siemens/common/fpga.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24
  25 #include <common.h>
  26 #include <command.h>
  27 #include <linux/ctype.h>
  28 #include <common.h>
  29
  30 #include "fpga.h"
  31
  32 int  power_on_reset(void);
  33
  34 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
  35
  36
  37 static int fpga_get_version(fpga_t* fpga, char* name)
  38 {
  39     char vname[12];
  40     /*
  41      * Net-list string format:
  42      *     "vvvvvvvvddddddddn...".
  43      *     Version Date    Name
  44      *     "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
  45      */
  46     if (strlen(name) < (16 + strlen(fpga->name)))
  47         goto failure;
  48     /* Check FPGA name */
  49     if (strcmp(&name[16], fpga->name) != 0)
  50         goto failure;
  51     /* Get version number */
  52     memcpy(vname, name, 8);
  53     vname[8] = '\0';
  54     return simple_strtoul(vname, NULL, 16);
  55
  56  failure:
  57     printf("Image name %s is invalid\n", name);
  58     return -1;
  59 }
  60
  61 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
  62
  63 static fpga_t* fpga_get(char* fpga_name)
  64 {
  65     char name[FPGA_NAME_LEN];
  66     int i;
  67
  68     if (strlen(fpga_name) >= FPGA_NAME_LEN)
  69         goto failure;
  70     for (i = 0; i < strlen(fpga_name); i++)
  71         name[i] = toupper(fpga_name[i]);
  72     name[i] = '\0';
  73     for (i = 0; i < fpga_count; i++) {
  74         if (strcmp(name, fpga_list[i].name) == 0)
  75             return &fpga_list[i];
  76     }
  77  failure:
  78     printf("FPGA: name %s is invalid\n", fpga_name);
  79     return NULL;
  80 }
  81
  82 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
  83
  84 static void fpga_status (fpga_t* fpga)
  85 {
  86     /* Check state */
  87     if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
  88         printf ("%s is loaded (%08lx)\n",
  89                 fpga->name, fpga_control(fpga, FPGA_GET_ID));
  90     else
  91         printf ("%s is NOT loaded\n", fpga->name);
  92 }
  93
  94 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
  95
  96 #define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
  97
  98 static int fpga_reset (fpga_t* fpga)
  99 {
 100     int i;
 101
 102     /* Set PROG to low and wait til INIT goes low */
 103     fpga_control(fpga, FPGA_PROG_SET_LOW);
 104     for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
 105         udelay (100);
 106         if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
 107             break;
 108     }
 109     if (i == FPGA_RESET_TIMEOUT)
 110         goto failure;
 111
 112     /* Set PROG to high and wait til INIT goes high */
 113     fpga_control(fpga, FPGA_PROG_SET_HIGH);
 114     for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
 115         udelay (100);
 116         if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
 117             break;
 118     }
 119     if (i == FPGA_RESET_TIMEOUT)
 120         goto failure;
 121
 122     return 0;
 123  failure:
 124     return 1;
 125 }
 126
 127 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
 128
 129 #define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
 130
 131 static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
 132 {
 133     volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
 134     image_header_t hdr;
 135     ulong len, checksum;
 136     uchar *data = (uchar *)&hdr;
 137     char *s, msg[32];
 138     int verify, i;
 139
 140     /*
 141      * Check the image header and data of the net-list
 142      */
 143     memcpy (&hdr, (char *)addr, sizeof(image_header_t));
 144
 145     if (hdr.ih_magic != IH_MAGIC) {
 146         strcpy (msg, "Bad Image Magic Number");
 147         goto failure;
 148     }
 149
 150     len  = sizeof(image_header_t);
 151
 152     checksum = hdr.ih_hcrc;
 153     hdr.ih_hcrc = 0;
 154
 155     if (crc32 (0, data, len) != checksum) {
 156         strcpy (msg, "Bad Image Header CRC");
 157         goto failure;
 158     }
 159
 160     data = (uchar*)(addr + sizeof(image_header_t));
 161     len  = hdr.ih_size;
 162
 163     s = getenv ("verify");
 164     verify = (s && (*s == 'n')) ? 0 : 1;
 165     if (verify) {
 166         if (crc32 (0, data, len) != hdr.ih_dcrc) {
 167             strcpy (msg, "Bad Image Data CRC");
 168             goto failure;
 169         }
 170     }
 171
 172     if (checkall && fpga_get_version(fpga, (char *)(hdr.ih_name)) < 0)
 173         return 1;
 174
 175     /* align length */
 176     if (len & 1)
 177         ++len;
 178
 179     /*
 180      * Reset FPGA and wait for completion
 181      */
 182     if (fpga_reset(fpga)) {
 183         strcpy (msg, "Reset Timeout");
 184         goto failure;
 185     }
 186
 187     printf ("(%s)... ", hdr.ih_name);
 188     /*
 189      * Copy data to FPGA
 190      */
 191     fpga_control (fpga, FPGA_LOAD_MODE);
 192     while (len--) {
 193         *fpga_addr = *data++;
 194     }
 195     fpga_control (fpga, FPGA_READ_MODE);
 196
 197     /*
 198      * Wait for completion and check error status if timeout
 199      */
 200     for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
 201         udelay (100);
 202         if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
 203             break;
 204     }
 205     if (i == FPGA_LOAD_TIMEOUT) {
 206         if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
 207             strcpy(msg, "Invalid Size");
 208         else
 209             strcpy(msg, "CRC Error");
 210         goto failure;
 211     }
 212
 213     printf("done\n");
 214     return 0;
 215
 216  failure:
 217
 218     printf("ERROR: %s\n", msg);
 219     return 1;
 220 }
 221
 222 #if defined(CONFIG_CMD_BSP)
 223
 224 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
 225
 226 int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 227 {
 228     ulong addr = 0;
 229     int i;
 230     fpga_t* fpga;
 231
 232     if (argc < 2)
 233         goto failure;
 234
 235     if (strncmp(argv[1], "stat", 4) == 0) {             /* status */
 236         if (argc == 2) {
 237             for (i = 0; i < fpga_count; i++) {
 238                 fpga_status (&fpga_list[i]);
 239             }
 240         }
 241         else if (argc == 3) {
 242             if ((fpga = fpga_get(argv[2])) == 0)
 243                 goto failure;
 244             fpga_status (fpga);
 245         }
 246         else
 247             goto failure;
 248     }
 249     else if (strcmp(argv[1],"load") == 0) {             /* load */
 250         if (argc == 3 && fpga_count == 1) {
 251             fpga = &fpga_list[0];
 252         }
 253         else if (argc == 4) {
 254             if ((fpga = fpga_get(argv[2])) == 0)
 255                 goto failure;
 256         }
 257         else
 258             goto failure;
 259
 260         addr = simple_strtoul(argv[argc-1], NULL, 16);
 261
 262         printf ("FPGA load %s: addr %08lx: ",
 263                 fpga->name, addr);
 264         fpga_load (fpga, addr, 1);
 265
 266     }
 267     else if (strncmp(argv[1], "rese", 4) == 0) {        /* reset */
 268         if (argc == 2 && fpga_count == 1) {
 269             fpga = &fpga_list[0];
 270         }
 271         else if (argc == 3) {
 272             if ((fpga = fpga_get(argv[2])) == 0)
 273                 goto failure;
 274         }
 275         else
 276             goto failure;
 277
 278         printf ("FPGA reset %s: ", fpga->name);
 279         if (fpga_reset(fpga))
 280             printf ("ERROR: Timeout\n");
 281         else
 282             printf ("done\n");
 283     }
 284     else
 285         goto failure;
 286
 287     return 0;
 288
 289  failure:
 290     printf ("Usage:\n%s\n", cmdtp->usage);
 291     return 1;
 292 }
 293
 294 U_BOOT_CMD(
 295         fpga,   4,      1,      do_fpga,
 296         "fpga    - access FPGA(s)\n",
 297         "fpga status [name] - print FPGA status\n"
 298         "fpga reset  [name] - reset FPGA\n"
 299         "fpga load [name] addr - load FPGA configuration data\n"
 300 );
 301
 302 #endif
 303
 304 /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
 305
 306 int fpga_init (void)
 307 {
 308     ulong addr;
 309     ulong new_id, old_id = 0;
 310     image_header_t *hdr;
 311     fpga_t* fpga;
 312     int do_load, i, j;
 313     char name[16], *s;
 314
 315     /*
 316      *  Port setup for FPGA control
 317      */
 318     for (i = 0; i < fpga_count; i++) {
 319         fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
 320     }
 321
 322     /*
 323      * Load FPGA(s): a new net-list is loaded if the FPGA is
 324      * empty, Power-on-Reset or the old one is not up-to-date
 325      */
 326     for (i = 0; i < fpga_count; i++) {
 327         fpga = &fpga_list[i];
 328         printf ("%s:  ", fpga->name);
 329
 330         for (j = 0; j < strlen(fpga->name); j++)
 331             name[j] = tolower(fpga->name[j]);
 332         name[j] = '\0';
 333         sprintf(name, "%s_addr", name);
 334         addr = 0;
 335         if ((s = getenv(name)) != NULL)
 336             addr = simple_strtoul(s, NULL, 16);
 337
 338         if (!addr) {
 339             printf ("env. variable %s undefined\n", name);
 340             return 1;
 341         }
 342
 343         hdr = (image_header_t *)addr;
 344         if ((new_id = fpga_get_version(fpga, (char *)(hdr->ih_name))) == -1)
 345             return 1;
 346
 347         do_load = 1;
 348
 349         if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
 350             old_id = fpga_control(fpga, FPGA_GET_ID);
 351             if (new_id == old_id)
 352                 do_load = 0;
 353         }
 354
 355         if (do_load) {
 356             printf ("loading ");
 357             fpga_load (fpga, addr, 0);
 358         } else {
 359             printf ("loaded (%08lx)\n", old_id);
 360         }
 361     }
 362
 363     return 0;
 364 }