2 * Board functions for TI AM335X based rut board
3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * u-boot:/board/ti/am335x/board.c
9 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
11 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/omap.h>
21 #include <asm/arch/ddr_defs.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/mmc_host_def.h>
25 #include <asm/arch/sys_proto.h>
35 #include "../common/factoryset.h"
36 #include "../../../drivers/video/da8xx-fb.h"
38 DECLARE_GLOBAL_DATA_PTR
;
41 * Read header information from EEPROM into global structure.
43 static int read_eeprom(void)
48 #ifdef CONFIG_SPL_BUILD
49 static void board_init_ddr(void)
51 struct emif_regs rut_ddr3_emif_reg_data
= {
52 .sdram_config
= 0x61C04AB2,
53 .sdram_tim1
= 0x0888A39B,
54 .sdram_tim2
= 0x26337FDA,
55 .sdram_tim3
= 0x501F830F,
56 .emif_ddr_phy_ctlr_1
= 0x6,
57 .zq_config
= 0x50074BE4,
61 struct ddr_data rut_ddr3_data
= {
62 .datardsratio0
= 0x3b,
63 .datawdsratio0
= 0x85,
64 .datafwsratio0
= 0x100,
65 .datawrsratio0
= 0xc1,
66 .datauserank0delay
= 1,
67 .datadldiff0
= PHY_DLL_LOCK_DIFF
,
70 struct cmd_control rut_ddr3_cmd_ctrl_data
= {
82 config_ddr(DDR_PLL_FREQ
, RUT_IOCTRL_VAL
, &rut_ddr3_data
,
83 &rut_ddr3_cmd_ctrl_data
, &rut_ddr3_emif_reg_data
, 0);
86 static void spl_siemens_board_init(void)
90 #endif /* if def CONFIG_SPL_BUILD */
92 #if defined(CONFIG_DRIVER_TI_CPSW)
93 static void cpsw_control(int enabled
)
95 /* VTP can be added here */
100 static struct cpsw_slave_data cpsw_slaves
[] = {
102 .slave_reg_ofs
= 0x208,
103 .sliver_reg_ofs
= 0xd80,
105 .phy_if
= PHY_INTERFACE_MODE_RMII
,
108 .slave_reg_ofs
= 0x308,
109 .sliver_reg_ofs
= 0xdc0,
111 .phy_if
= PHY_INTERFACE_MODE_RMII
,
115 static struct cpsw_platform_data cpsw_data
= {
116 .mdio_base
= CPSW_MDIO_BASE
,
117 .cpsw_base
= CPSW_BASE
,
120 .cpdma_reg_ofs
= 0x800,
122 .slave_data
= cpsw_slaves
,
123 .ale_reg_ofs
= 0xd00,
125 .host_port_reg_ofs
= 0x108,
126 .hw_stats_reg_ofs
= 0x900,
127 .bd_ram_ofs
= 0x2000,
128 .mac_control
= (1 << 5),
129 .control
= cpsw_control
,
131 .version
= CPSW_CTRL_VERSION_2
,
134 #if defined(CONFIG_DRIVER_TI_CPSW) || \
135 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
136 int board_eth_init(bd_t
*bis
)
138 struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
142 #ifndef CONFIG_SPL_BUILD
146 /* Set rgmii mode and enable rmii clock to be sourced from chip */
147 writel((RMII_MODE_ENABLE
| RMII_CHIPCKL_ENABLE
), &cdev
->miisel
);
149 rv
= cpsw_register(&cpsw_data
);
151 printf("Error %d registering CPSW switch\n", rv
);
156 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
157 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
159 #if defined(CONFIG_HW_WATCHDOG)
160 static bool hw_watchdog_init_done
;
161 static int hw_watchdog_trigger_level
;
163 void hw_watchdog_reset(void)
165 if (!hw_watchdog_init_done
)
168 hw_watchdog_trigger_level
= hw_watchdog_trigger_level
? 0 : 1;
169 gpio_set_value(WATCHDOG_TRIGGER_GPIO
, hw_watchdog_trigger_level
);
172 void hw_watchdog_init(void)
174 gpio_request(WATCHDOG_TRIGGER_GPIO
, "watchdog_trigger");
175 gpio_direction_output(WATCHDOG_TRIGGER_GPIO
, hw_watchdog_trigger_level
);
179 hw_watchdog_init_done
= 1;
181 #endif /* defined(CONFIG_HW_WATCHDOG) */
183 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
184 static struct da8xx_panel lcd_panels
[] = {
185 /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
187 .name
= "KWH043MC17-F01",
190 .hfp
= 50, /* no spec, "don't care" values */
196 .pxl_clk
= 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
199 /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
201 .name
= "KWH043ST20-F01",
204 .hfp
= 50, /* no spec, "don't care" values */
210 .pxl_clk
= 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
213 /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
215 .name
= "MI0430VT-1",
218 .hfp
= 50, /* no spec, "don't care" values */
224 .pxl_clk
= 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
229 static const struct display_panel disp_panels
[] = {
250 static const struct lcd_ctrl_config lcd_cfgs
[] = {
261 .invert_line_clock
= 1,
262 .invert_frm_clock
= 1,
277 .invert_line_clock
= 1,
278 .invert_frm_clock
= 1,
293 .invert_line_clock
= 1,
294 .invert_frm_clock
= 1,
302 /* no console on this board */
303 int board_cfb_skip(void)
308 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
309 #define PLL_GET_N(v) (v & 0x7f)
311 static struct dpll_regs dpll_lcd_regs
= {
312 .cm_clkmode_dpll
= CM_WKUP
+ 0x98,
313 .cm_idlest_dpll
= CM_WKUP
+ 0x48,
314 .cm_clksel_dpll
= CM_WKUP
+ 0x54,
317 static int get_clk(struct dpll_regs
*dpll_regs
)
323 val
= readl(dpll_regs
->cm_clksel_dpll
);
326 f
= (m
* V_OSCK
) / n
;
335 return get_clk(&dpll_lcd_regs
);
338 static int conf_disp_pll(int m
, int n
)
340 struct cm_perpll
*cmper
= (struct cm_perpll
*)CM_PER
;
341 struct cm_dpll
*cmdpll
= (struct cm_dpll
*)CM_DPLL
;
342 struct dpll_params dpll_lcd
= {m
, n
, -1, -1, -1, -1, -1};
343 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
344 struct cm_wkuppll
*cmwkup
= (struct cm_wkuppll
*)CM_WKUP
;
347 u32
*const clk_domains
[] = {
351 u32
*const clk_modules_explicit_en
[] = {
353 &cmper
->lcdcclkstctrl
,
357 do_enable_clocks(clk_domains
, clk_modules_explicit_en
, 1);
358 /* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */
359 writel(0x0, &cmdpll
->clklcdcpixelclk
);
361 do_setup_dpll(&dpll_lcd_regs
, &dpll_lcd
);
363 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
364 writel(0x64, &cmwkup
->resv6
[3]); /* 0x50 */
365 writel(0x800, &cmwkup
->resv6
[2]); /* 0x4c */
366 writel(readl(&cmwkup
->clkmoddplldisp
) | (1 << 12),
367 &cmwkup
->clkmoddplldisp
); /* 0x98 */
372 static int set_gpio(int gpio
, int state
)
374 gpio_request(gpio
, "temp");
375 gpio_direction_output(gpio
, state
);
376 gpio_set_value(gpio
, state
);
381 static int enable_lcd(void)
383 unsigned char buf
[1];
385 set_gpio(BOARD_LCD_RESET
, 1);
388 kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3
);
392 i2c_write(0x24, 0x7, 1, buf
, 1);
394 i2c_write(0x24, 0x8, 1, buf
, 1);
398 int arch_early_init_r(void)
404 static int board_video_init(void)
407 int anzdisp
= ARRAY_SIZE(lcd_panels
);
410 for (i
= 0; i
< anzdisp
; i
++) {
411 if (strncmp((const char *)factory_dat
.disp_name
,
413 strlen((const char *)factory_dat
.disp_name
)) == 0) {
414 printf("DISPLAY: %s\n", factory_dat
.disp_name
);
420 printf("%s: %s not found, using default %s\n", __func__
,
421 factory_dat
.disp_name
, lcd_panels
[i
].name
);
423 conf_disp_pll(25, 2);
424 da8xx_video_init(&lcd_panels
[display
], &lcd_cfgs
[display
],
425 lcd_cfgs
[display
].bpp
);
431 #endif /* ifdef CONFIG_VIDEO */
432 #include "../common/board.c"