board/sixnet/sixnet.c

   1 /*
   2  * (C) Copyright 2001, 2002
   3  * Dave Ellis, SIXNET, dge@sixnetio.com.
   4  *  Based on code by:
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  * and other contributors to U-Boot. See file CREDITS for list
   7  * of people who contributed to this  project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <config.h>
  27 #include <jffs2/jffs2.h>
  28 #include <mpc8xx.h>
  29 #include <net.h>        /* for eth_init() */
  30 #include <rtc.h>
  31 #include "sixnet.h"
  32 #ifdef CONFIG_SHOW_BOOT_PROGRESS
  33 # include <status_led.h>
  34 #endif
  35
  36 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
  37 #include <linux/mtd/nand_legacy.h>
  38 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
  39 #endif
  40
  41 #define ORMASK(size) ((-size) & OR_AM_MSK)
  42
  43 static long ram_size(ulong *, long);
  44
  45 /* ------------------------------------------------------------------------- */
  46
  47 #ifdef CONFIG_SHOW_BOOT_PROGRESS
  48 void show_boot_progress (int status)
  49 {
  50 #if defined(CONFIG_STATUS_LED)
  51 # if defined(STATUS_LED_BOOT)
  52         if (status == 15) {
  53                 /* ready to transfer to kernel, make sure LED is proper state */
  54                 status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
  55         }
  56 # endif /* STATUS_LED_BOOT */
  57 #endif /* CONFIG_STATUS_LED */
  58 }
  59 #endif
  60
  61 /* ------------------------------------------------------------------------- */
  62
  63 /*
  64  * Check Board Identity:
  65  * returns 0 if recognized, -1 if unknown
  66  */
  67
  68 int checkboard (void)
  69 {
  70         puts ("Board: SIXNET SXNI855T\n");
  71         return 0;
  72 }
  73
  74 /* ------------------------------------------------------------------------- */
  75
  76 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
  77 #error "SXNI855T has no PCMCIA port"
  78 #endif  /* CFG_CMD_PCMCIA */
  79
  80 /* ------------------------------------------------------------------------- */
  81
  82 #define _not_used_ 0xffffffff
  83
  84 /* UPMB table for dual UART. */
  85
  86 /* this table is for 50MHz operation, it should work at all lower speeds */
  87 const uint duart_table[] =
  88 {
  89         /* single read. (offset 0 in upm RAM) */
  90         0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
  91         0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
  92
  93         /* burst read. (offset 8 in upm RAM) */
  94         _not_used_, _not_used_, _not_used_, _not_used_,
  95         _not_used_, _not_used_, _not_used_, _not_used_,
  96         _not_used_, _not_used_, _not_used_, _not_used_,
  97         _not_used_, _not_used_, _not_used_, _not_used_,
  98
  99         /* single write. (offset 18 in upm RAM) */
 100         0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
 101         0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
 102
 103         /* burst write. (offset 20 in upm RAM) */
 104         _not_used_, _not_used_, _not_used_, _not_used_,
 105         _not_used_, _not_used_, _not_used_, _not_used_,
 106         _not_used_, _not_used_, _not_used_, _not_used_,
 107         _not_used_, _not_used_, _not_used_, _not_used_,
 108
 109         /* refresh. (offset 30 in upm RAM) */
 110         _not_used_, _not_used_, _not_used_, _not_used_,
 111         _not_used_, _not_used_, _not_used_, _not_used_,
 112         _not_used_, _not_used_, _not_used_, _not_used_,
 113
 114         /* exception. (offset 3c in upm RAM) */
 115         _not_used_, _not_used_, _not_used_, _not_used_,
 116 };
 117
 118 /* Load FPGA very early in boot sequence, since it must be
 119  * loaded before the 16C2550 serial channels can be used as
 120  * console channels.
 121  *
 122  * Note: Much of the configuration is not complete. The
 123  *       stack is in DPRAM since SDRAM has not been initialized,
 124  *       so the stack must be kept small. Global variables
 125  *       are still in FLASH, so they cannot be written.
 126  *       Only the FLASH, DPRAM, immap and FPGA can be addressed,
 127  *       the other chip selects may not have been initialized.
 128  *       The clocks have been initialized, so udelay() can be
 129  *       used.
 130  */
 131 #define FPGA_DONE       0x0080  /* PA8, input, high when FPGA load complete */
 132 #define FPGA_PROGRAM_L  0x0040  /* PA9, output, low to reset, high to start */
 133 #define FPGA_INIT_L     0x0020  /* PA10, input, low indicates not ready */
 134 #define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG))       /* FPGA port */
 135
 136 int board_postclk_init (void)
 137 {
 138
 139         /* the data to load to the XCSxxXL FPGA */
 140         static const unsigned char fpgadata[] = {
 141 # include "fpgadata.c"
 142         };
 143
 144         volatile immap_t     *immap = (immap_t *)CFG_IMMR;
 145         volatile memctl8xx_t *memctl = &immap->im_memctl;
 146 #define porta (immap->im_ioport.iop_padat)
 147         const unsigned char* pdata;
 148
 149         /* /INITFPGA and DONEFPGA signals are inputs */
 150         immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
 151
 152         /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
 153         porta &= ~FPGA_PROGRAM_L;
 154
 155         /* Set FPGA as an output */
 156         immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
 157
 158         /* delay a little to make sure FPGA sees it, really
 159          * only need less than a microsecond.
 160          */
 161         udelay(10);
 162
 163         /* unassert /PROGRAM */
 164         porta |= FPGA_PROGRAM_L;
 165
 166         /* delay while FPGA does last erase, indicated by
 167          * /INITFPGA going high. This should happen within a
 168          * few milliseconds.
 169          */
 170         /* ### FIXME - a timeout check would be good, maybe flash
 171          * the status LED to indicate the error?
 172          */
 173         while ((porta & FPGA_INIT_L) == 0)
 174                 ; /* waiting */
 175
 176         /* write program data to FPGA at the programming address
 177          * so extra /CS1 strobes at end of configuration don't actually
 178          * write to any registers.
 179          */
 180         fpga = 0xff;            /* first write is ignored       */
 181         fpga = 0xff;            /* fill byte                    */
 182         fpga = 0xff;            /* fill byte                    */
 183         fpga = 0x4f;            /* preamble code                */
 184         fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
 185         fpga = 0x4b;            /* field check code */
 186
 187         pdata = fpgadata;
 188         /* while no error write out each of the 28 byte frames */
 189         while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
 190                && pdata < fpgadata + sizeof(fpgadata)) {
 191
 192                 fpga = 0x4f;    /* preamble code */
 193
 194                 /* 21 bytes of data in a frame */
 195                 fpga = *(pdata++); fpga = *(pdata++);
 196                 fpga = *(pdata++); fpga = *(pdata++);
 197                 fpga = *(pdata++); fpga = *(pdata++);
 198                 fpga = *(pdata++); fpga = *(pdata++);
 199                 fpga = *(pdata++); fpga = *(pdata++);
 200                 fpga = *(pdata++); fpga = *(pdata++);
 201                 fpga = *(pdata++); fpga = *(pdata++);
 202                 fpga = *(pdata++); fpga = *(pdata++);
 203                 fpga = *(pdata++); fpga = *(pdata++);
 204                 fpga = *(pdata++); fpga = *(pdata++);
 205                 fpga = *(pdata++);
 206
 207                 fpga = 0x4b;    /* field check code             */
 208                 fpga = 0xff;    /* extended write cycle         */
 209                 fpga = 0x4b;    /* extended write cycle
 210                                  * (actually 0x4b from bitgen.exe)
 211                                  */
 212                 fpga = 0xff;    /* extended write cycle         */
 213                 fpga = 0xff;    /* extended write cycle         */
 214                 fpga = 0xff;    /* extended write cycle         */
 215         }
 216
 217         fpga = 0xff;            /* startup byte                 */
 218         fpga = 0xff;            /* startup byte                 */
 219         fpga = 0xff;            /* startup byte                 */
 220         fpga = 0xff;            /* startup byte                 */
 221
 222 #if 0 /* ### FIXME */
 223         /* If didn't load all the data or FPGA_DONE is low the load failed.
 224          * Maybe someday stop here and flash the status LED? The console
 225          * is not configured, so can't print an error message. Can't write
 226          * global variables to set a flag (except gd?).
 227          * For now it must work.
 228          */
 229 #endif
 230
 231         /* Now that the FPGA is loaded, set up the Dual UART chip
 232          * selects. Must be done here since it may be used as the console.
 233          */
 234         upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
 235
 236         memctl->memc_mbmr = DUART_MBMR;
 237         memctl->memc_or5 = DUART_OR_VALUE;
 238         memctl->memc_br5 = DUART_BR5_VALUE;
 239         memctl->memc_or6 = DUART_OR_VALUE;
 240         memctl->memc_br6 = DUART_BR6_VALUE;
 241
 242         return (0);
 243 }
 244
 245 /* ------------------------------------------------------------------------- */
 246
 247 /* base address for SRAM, assume 32-bit port,  valid */
 248 #define NVRAM_BR_VALUE   (CFG_SRAM_BASE | BR_PS_32 | BR_V)
 249
 250 /*  up to 64MB - will be adjusted for actual size */
 251 #define NVRAM_OR_PRELIM  (ORMASK(CFG_SRAM_SIZE) \
 252         | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
 253 /*
 254  * Miscellaneous platform dependent initializations after running in RAM.
 255  */
 256
 257 int misc_init_r (void)
 258 {
 259         DECLARE_GLOBAL_DATA_PTR;
 260
 261         volatile immap_t     *immap = (immap_t *)CFG_IMMR;
 262         volatile memctl8xx_t *memctl = &immap->im_memctl;
 263         char* s;
 264         char* e;
 265         int reg;
 266         bd_t *bd = gd->bd;
 267
 268         memctl->memc_or2 = NVRAM_OR_PRELIM;
 269         memctl->memc_br2 = NVRAM_BR_VALUE;
 270
 271         /* Is there any SRAM? Is it 16 or 32 bits wide? */
 272
 273         /* First look for 32-bit SRAM */
 274         bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
 275
 276         if (bd->bi_sramsize == 0) {
 277             /* no 32-bit SRAM, but there could be 16-bit SRAM since
 278              * it would report size 0 when configured for 32-bit bus.
 279              * Try again with a 16-bit bus.
 280              */
 281             memctl->memc_br2 |= BR_PS_16;
 282             bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
 283         }
 284
 285         if (bd->bi_sramsize == 0) {
 286             memctl->memc_br2 = 0;       /* disable select since nothing there */
 287         }
 288         else {
 289             /* adjust or2 for actual size of SRAM */
 290             memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
 291             bd->bi_sramstart = CFG_SRAM_BASE;
 292             printf("SRAM:  %lu KB\n", bd->bi_sramsize >> 10);
 293         }
 294
 295
 296         /* set standard MPC8xx clock so kernel will see the time
 297          * even if it doesn't have a DS1306 clock driver.
 298          * This helps with experimenting with standard kernels.
 299          */
 300         {
 301             ulong tim;
 302             struct rtc_time tmp;
 303
 304             rtc_get(&tmp);      /* get time from DS1306 RTC */
 305
 306             /* convert to seconds since 1970 */
 307             tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
 308                          tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
 309
 310             immap->im_sitk.sitk_rtck = KAPWR_KEY;
 311             immap->im_sit.sit_rtc = tim;
 312         }
 313
 314         /* set up ethernet address for SCC ethernet. If eth1addr
 315          * is present it gets a unique address, otherwise it
 316          * shares the FEC address.
 317          */
 318         s = getenv("eth1addr");
 319         if (s == NULL)
 320                 s = getenv("ethaddr");
 321         for (reg=0; reg<6; ++reg) {
 322                 bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
 323                 if (s)
 324                         s = (*e) ? e+1 : e;
 325         }
 326
 327         return (0);
 328 }
 329
 330 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 331 void nand_init(void)
 332 {
 333         unsigned long totlen = nand_probe(CFG_DFLASH_BASE);
 334
 335         printf ("%4lu MB\n", totlen >> 20);
 336 }
 337 #endif
 338
 339 /* ------------------------------------------------------------------------- */
 340
 341 /*
 342  * Check memory range for valid RAM. A simple memory test determines
 343  * the actually available RAM size between addresses `base' and
 344  * `base + maxsize'.
 345  *
 346  * The memory size MUST be a power of 2 for this to work.
 347  *
 348  * The only memory modified is 8 bytes at offset 0. This is important
 349  * since for the SRAM this location is reserved for autosizing, so if
 350  * it is modified and the board is reset before ram_size() completes
 351  * no damage is  done. Normally even the memory at 0 is preserved. The
 352  * higher SRAM addresses may contain battery backed RAM disk data which
 353  * must never be corrupted.
 354  */
 355
 356 static long ram_size(ulong *base, long maxsize)
 357 {
 358     volatile long       *test_addr;
 359     volatile ulong      *base_addr = base;
 360     ulong               ofs;            /* byte offset from base_addr */
 361     ulong               save;           /* to make test non-destructive */
 362     ulong               save2;          /* to make test non-destructive */
 363     long                ramsize = -1;   /* size not determined yet */
 364
 365     save = *base_addr;          /* save value at 0 so can restore */
 366     save2 = *(base_addr+1);     /* save value at 4 so can restore */
 367
 368     /* is any SRAM present? */
 369     *base_addr = 0x5555aaaa;
 370
 371     /* It is important to drive the data bus with different data so
 372      * it doesn't remember the value and look like RAM that isn't there.
 373      */
 374     *(base_addr + 1) = 0xaaaa5555;      /* use write to modify data bus */
 375
 376     if (*base_addr != 0x5555aaaa)
 377         ramsize = 0;            /* no RAM present, or defective */
 378     else {
 379         *base_addr = 0xaaaa5555;
 380         *(base_addr + 1) = 0x5555aaaa;  /* use write to modify data bus */
 381         if (*base_addr != 0xaaaa5555)
 382             ramsize = 0;        /* no RAM present, or defective */
 383     }
 384
 385     /* now size it if any is present */
 386     for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
 387         test_addr = (long*)((long)base_addr + ofs);     /* location to test */
 388
 389         *base_addr = ~*test_addr;
 390         if (*base_addr == *test_addr)
 391             ramsize = ofs;      /* wrapped back to 0, so this is the size */
 392     }
 393
 394     *base_addr = save;          /* restore value at 0 */
 395     *(base_addr+1) = save2;     /* restore value at 4 */
 396     return (ramsize);
 397 }
 398
 399 /* ------------------------------------------------------------------------- */
 400 /* sdram table based on the FADS manual                                      */
 401 /* for chip MB811171622A-100                                                 */
 402
 403 /* this table is for 50MHz operation, it should work at all lower speeds */
 404
 405 const uint sdram_table[] =
 406 {
 407         /* single read. (offset 0 in upm RAM) */
 408         0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
 409         0x1ff77c47,
 410
 411         /* precharge and Mode Register Set initialization (offset 5).
 412          * This is also entered at offset 6 to do Mode Register Set
 413          * without the precharge.
 414          */
 415         0x1ff77c34, 0xefeabc34, 0x1fb57c35,
 416
 417         /* burst read. (offset 8 in upm RAM) */
 418         0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
 419         0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
 420         _not_used_, _not_used_, _not_used_, _not_used_,
 421         _not_used_, _not_used_, _not_used_, _not_used_,
 422
 423         /* single write. (offset 18 in upm RAM) */
 424         /* FADS had 0x1f27fc04, ...
 425          * but most other boards have 0x1f07fc04, which
 426          * sets GPL0 from A11MPC to 0 1/4 clock earlier,
 427          * like the single read.
 428          * This seems better so I am going with the change.
 429          */
 430         0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
 431         _not_used_, _not_used_, _not_used_, _not_used_,
 432
 433         /* burst write. (offset 20 in upm RAM) */
 434         0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
 435         0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
 436         _not_used_, _not_used_, _not_used_, _not_used_,
 437         _not_used_, _not_used_, _not_used_, _not_used_,
 438
 439         /* refresh. (offset 30 in upm RAM) */
 440         0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 441         0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
 442         _not_used_, _not_used_, _not_used_, _not_used_,
 443
 444         /* exception. (offset 3c in upm RAM) */
 445         0x7ffffc07, _not_used_, _not_used_, _not_used_ };
 446
 447 /* ------------------------------------------------------------------------- */
 448
 449 #define SDRAM_MAX_SIZE          0x10000000      /* max 256 MB SDRAM */
 450
 451 /* precharge and set Mode Register */
 452 #define SDRAM_MCR_PRE    (MCR_OP_RUN | MCR_UPM_A |      /* select UPM     */ \
 453                           MCR_MB_CS3 |                  /* chip select    */ \
 454                           MCR_MLCF(1) | MCR_MAD(5))     /* 1 time at 0x05 */
 455
 456 /* set Mode Register, no precharge */
 457 #define SDRAM_MCR_MRS    (MCR_OP_RUN | MCR_UPM_A |      /* select UPM     */ \
 458                           MCR_MB_CS3 |                  /* chip select    */ \
 459                           MCR_MLCF(1) | MCR_MAD(6))     /* 1 time at 0x06 */
 460
 461 /* runs refresh loop twice so get 8 refresh cycles */
 462 #define SDRAM_MCR_REFR   (MCR_OP_RUN | MCR_UPM_A |      /* select UPM     */ \
 463                           MCR_MB_CS3 |                  /* chip select    */ \
 464                           MCR_MLCF(2) | MCR_MAD(0x30))  /* twice at 0x30  */
 465
 466 /* MAMR values work in either mamr or mbmr */
 467 #define SDRAM_MAMR_BASE  /* refresh at 50MHz */                           \
 468                          ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE             \
 469                          | MAMR_DSA_1_CYCL      /* 1 cycle disable */     \
 470                          | MAMR_RLFA_1X         /* Read loop 1 time */    \
 471                          | MAMR_WLFA_1X         /* Write loop 1 time */   \
 472                          | MAMR_TLFA_4X)        /* Timer loop 4 times */
 473 /* 8 column SDRAM */
 474 #define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE                                  \
 475                          | MAMR_AMA_TYPE_0      /* Address MUX 0 */       \
 476                          | MAMR_G0CLA_A11)      /* GPL0 A11[MPC] */
 477
 478 /* 9 column SDRAM */
 479 #define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE                                  \
 480                          | MAMR_AMA_TYPE_1      /* Address MUX 1 */       \
 481                          | MAMR_G0CLA_A10)      /* GPL0 A10[MPC] */
 482
 483 /* base address 0, 32-bit port, SDRAM UPM, valid */
 484 #define SDRAM_BR_VALUE   (BR_PS_32 | BR_MS_UPMA | BR_V)
 485
 486 /*  up to 256MB, SAM, G5LS - will be adjusted for actual size */
 487 #define SDRAM_OR_PRELIM  (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
 488
 489 /* This is the Mode Select Register value for the SDRAM.
 490  * Burst length: 4
 491  * Burst Type: sequential
 492  * CAS Latency: 2
 493  * Write Burst Length: burst
 494  */
 495 #define SDRAM_MODE   0x22       /* CAS latency 2, burst length 4 */
 496
 497 /* ------------------------------------------------------------------------- */
 498
 499 long int initdram(int board_type)
 500 {
 501         volatile immap_t     *immap = (immap_t *)CFG_IMMR;
 502         volatile memctl8xx_t *memctl = &immap->im_memctl;
 503         uint size_sdram = 0;
 504         uint size_sdram9 = 0;
 505         uint base = 0;          /* SDRAM must start at 0 */
 506         int i;
 507
 508         upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 509
 510         /* Configure the refresh (mostly).  This needs to be
 511          * based upon processor clock speed and optimized to provide
 512          * the highest level of performance.
 513          *
 514          * Preliminary prescaler for refresh.
 515          * This value is selected for four cycles in 31.2 us,
 516          * which gives 8192 cycles in 64 milliseconds.
 517          * This may be too fast, but works for any memory.
 518          * It is adjusted to 4096 cycles in 64 milliseconds if
 519          * possible once we know what memory we have.
 520          *
 521          * We have to be careful changing UPM registers after we
 522          * ask it to run these commands.
 523          *
 524          * PTA - periodic timer period for our design is
 525          *       50 MHz x 31.2us
 526          *       ---------------  = 195
 527          *       1 x 8 x 1
 528          *
 529          *    50MHz clock
 530          *    31.2us refresh interval
 531          *    SCCR[DFBRG] 0
 532          *    PTP divide by 8
 533          *    1 chip select
 534          */
 535         memctl->memc_mptpr = MPTPR_PTP_DIV8;    /* 0x0800 */
 536         memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
 537
 538         /* The SDRAM Mode Register value is shifted left 2 bits since
 539          * A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
 540          */
 541         memctl->memc_mar = SDRAM_MODE << 2;     /* MRS code */
 542         udelay(200);            /* SDRAM needs 200uS before set it up */
 543
 544         /* Now run the precharge/nop/mrs commands. */
 545         memctl->memc_mcr = SDRAM_MCR_PRE;
 546         udelay(2);
 547
 548         /* Run 8 refresh cycles (2 sets of 4) */
 549         memctl->memc_mcr = SDRAM_MCR_REFR;      /* run refresh twice */
 550         udelay(2);
 551
 552         /* some brands want Mode Register set after the refresh
 553          * cycles. This shouldn't hurt anything for the brands
 554          * that were happy with the first time we set it.
 555          */
 556         memctl->memc_mcr = SDRAM_MCR_MRS;
 557         udelay(2);
 558
 559         memctl->memc_mamr = SDRAM_MAMR_8COL;    /* enable refresh */
 560         memctl->memc_or3 = SDRAM_OR_PRELIM;
 561         memctl->memc_br3 = SDRAM_BR_VALUE + base;
 562
 563         /* Some brands need at least 10 DRAM accesses to stabilize.
 564          * It wont hurt the brands that don't.
 565          */
 566         for (i=0; i<10; ++i) {
 567                 volatile ulong *addr = (volatile ulong *)base;
 568                 ulong val;
 569
 570                 val = *(addr + i);
 571                 *(addr + i) = val;
 572         }
 573
 574         /* Check SDRAM memory Size in 8 column mode.
 575          * For a 9 column memory we will get half the actual size.
 576          */
 577         size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
 578
 579         /* Check SDRAM memory Size in 9 column mode.
 580          * For an 8 column memory we will see at most 4 megabytes.
 581          */
 582         memctl->memc_mamr = SDRAM_MAMR_9COL;
 583         size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
 584
 585         if (size_sdram < size_sdram9)   /* leave configuration at 9 columns */
 586                 size_sdram = size_sdram9;
 587         else                            /* go back to 8 columns */
 588                 memctl->memc_mamr = SDRAM_MAMR_8COL;
 589
 590         /* adjust or3 for actual size of SDRAM
 591          */
 592         memctl->memc_or3 |= ORMASK(size_sdram);
 593
 594         /* Adjust refresh rate depending on SDRAM type.
 595          * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
 596          * it at the current (fast) rate.
 597          * For 16, 64 and 128 MBit half the rate will do.
 598          */
 599         if (size_sdram <= 32 * 1024 * 1024)
 600                 memctl->memc_mptpr = MPTPR_PTP_DIV16;   /* 0x0400 */
 601
 602         return (size_sdram);
 603 }