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sunxi: Convert CONFIG_MACPWR to Kconfig
[people/ms/u-boot.git] / board / sunxi / board.c
1 /*
2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4 *
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
8 *
9 * Some board init for the Allwinner A10-evb board.
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14 #include <common.h>
15 #include <mmc.h>
16 #include <axp_pmic.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/display.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/spl.h>
24 #include <asm/arch/usb_phy.h>
25 #ifndef CONFIG_ARM64
26 #include <asm/armv7.h>
27 #endif
28 #include <asm/gpio.h>
29 #include <asm/io.h>
30 #include <crc.h>
31 #include <environment.h>
32 #include <libfdt.h>
33 #include <nand.h>
34 #include <net.h>
35 #include <sy8106a.h>
36
37 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
38 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
39 int soft_i2c_gpio_sda;
40 int soft_i2c_gpio_scl;
41
42 static int soft_i2c_board_init(void)
43 {
44 int ret;
45
46 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
47 if (soft_i2c_gpio_sda < 0) {
48 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
50 return soft_i2c_gpio_sda;
51 }
52 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
53 if (ret) {
54 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
56 return ret;
57 }
58
59 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
60 if (soft_i2c_gpio_scl < 0) {
61 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
63 return soft_i2c_gpio_scl;
64 }
65 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
66 if (ret) {
67 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
69 return ret;
70 }
71
72 return 0;
73 }
74 #else
75 static int soft_i2c_board_init(void) { return 0; }
76 #endif
77
78 DECLARE_GLOBAL_DATA_PTR;
79
80 /* add board specific code here */
81 int board_init(void)
82 {
83 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
84
85 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
86
87 #ifndef CONFIG_ARM64
88 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
89 debug("id_pfr1: 0x%08x\n", id_pfr1);
90 /* Generic Timer Extension available? */
91 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
92 uint32_t freq;
93
94 debug("Setting CNTFRQ\n");
95
96 /*
97 * CNTFRQ is a secure register, so we will crash if we try to
98 * write this from the non-secure world (read is OK, though).
99 * In case some bootcode has already set the correct value,
100 * we avoid the risk of writing to it.
101 */
102 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
103 if (freq != COUNTER_FREQUENCY) {
104 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
105 freq, COUNTER_FREQUENCY);
106 #ifdef CONFIG_NON_SECURE
107 printf("arch timer frequency is wrong, but cannot adjust it\n");
108 #else
109 asm volatile("mcr p15, 0, %0, c14, c0, 0"
110 : : "r"(COUNTER_FREQUENCY));
111 #endif
112 }
113 }
114 #endif /* !CONFIG_ARM64 */
115
116 ret = axp_gpio_init();
117 if (ret)
118 return ret;
119
120 #ifdef CONFIG_SATAPWR
121 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
122 gpio_request(satapwr_pin, "satapwr");
123 gpio_direction_output(satapwr_pin, 1);
124 #endif
125 #ifdef CONFIG_MACPWR
126 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
127 gpio_request(macpwr_pin, "macpwr");
128 gpio_direction_output(macpwr_pin, 1);
129 #endif
130
131 /* Uses dm gpio code so do this here and not in i2c_init_board() */
132 return soft_i2c_board_init();
133 }
134
135 int dram_init(void)
136 {
137 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
138
139 return 0;
140 }
141
142 #if defined(CONFIG_NAND_SUNXI)
143 static void nand_pinmux_setup(void)
144 {
145 unsigned int pin;
146
147 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
148 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
149
150 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
151 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
152 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
153 #endif
154 /* sun4i / sun7i do have a PC23, but it is not used for nand,
155 * only sun7i has a PC24 */
156 #ifdef CONFIG_MACH_SUN7I
157 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
158 #endif
159 }
160
161 static void nand_clock_setup(void)
162 {
163 struct sunxi_ccm_reg *const ccm =
164 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
165
166 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
167 #ifdef CONFIG_MACH_SUN9I
168 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
169 #else
170 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
171 #endif
172 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
173 }
174
175 void board_nand_init(void)
176 {
177 nand_pinmux_setup();
178 nand_clock_setup();
179 #ifndef CONFIG_SPL_BUILD
180 sunxi_nand_init();
181 #endif
182 }
183 #endif
184
185 #ifdef CONFIG_GENERIC_MMC
186 static void mmc_pinmux_setup(int sdc)
187 {
188 unsigned int pin;
189 __maybe_unused int pins;
190
191 switch (sdc) {
192 case 0:
193 /* SDC0: PF0-PF5 */
194 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
195 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
196 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
197 sunxi_gpio_set_drv(pin, 2);
198 }
199 break;
200
201 case 1:
202 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
203
204 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
205 if (pins == SUNXI_GPIO_H) {
206 /* SDC1: PH22-PH-27 */
207 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
208 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
209 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
210 sunxi_gpio_set_drv(pin, 2);
211 }
212 } else {
213 /* SDC1: PG0-PG5 */
214 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
215 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
216 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
217 sunxi_gpio_set_drv(pin, 2);
218 }
219 }
220 #elif defined(CONFIG_MACH_SUN5I)
221 /* SDC1: PG3-PG8 */
222 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
223 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
224 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
225 sunxi_gpio_set_drv(pin, 2);
226 }
227 #elif defined(CONFIG_MACH_SUN6I)
228 /* SDC1: PG0-PG5 */
229 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
230 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
231 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
232 sunxi_gpio_set_drv(pin, 2);
233 }
234 #elif defined(CONFIG_MACH_SUN8I)
235 if (pins == SUNXI_GPIO_D) {
236 /* SDC1: PD2-PD7 */
237 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
238 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
239 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
240 sunxi_gpio_set_drv(pin, 2);
241 }
242 } else {
243 /* SDC1: PG0-PG5 */
244 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
245 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
246 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
247 sunxi_gpio_set_drv(pin, 2);
248 }
249 }
250 #endif
251 break;
252
253 case 2:
254 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
255
256 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
257 /* SDC2: PC6-PC11 */
258 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
259 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
260 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
261 sunxi_gpio_set_drv(pin, 2);
262 }
263 #elif defined(CONFIG_MACH_SUN5I)
264 if (pins == SUNXI_GPIO_E) {
265 /* SDC2: PE4-PE9 */
266 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
267 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
268 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
269 sunxi_gpio_set_drv(pin, 2);
270 }
271 } else {
272 /* SDC2: PC6-PC15 */
273 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
274 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
275 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
276 sunxi_gpio_set_drv(pin, 2);
277 }
278 }
279 #elif defined(CONFIG_MACH_SUN6I)
280 if (pins == SUNXI_GPIO_A) {
281 /* SDC2: PA9-PA14 */
282 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
283 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
284 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
285 sunxi_gpio_set_drv(pin, 2);
286 }
287 } else {
288 /* SDC2: PC6-PC15, PC24 */
289 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
290 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
291 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
292 sunxi_gpio_set_drv(pin, 2);
293 }
294
295 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
296 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
297 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
298 }
299 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
300 /* SDC2: PC5-PC6, PC8-PC16 */
301 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
302 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
303 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
304 sunxi_gpio_set_drv(pin, 2);
305 }
306
307 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
308 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
309 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
310 sunxi_gpio_set_drv(pin, 2);
311 }
312 #elif defined(CONFIG_MACH_SUN9I)
313 /* SDC2: PC6-PC16 */
314 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
315 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
316 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
317 sunxi_gpio_set_drv(pin, 2);
318 }
319 #endif
320 break;
321
322 case 3:
323 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
324
325 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
326 /* SDC3: PI4-PI9 */
327 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
328 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
329 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
330 sunxi_gpio_set_drv(pin, 2);
331 }
332 #elif defined(CONFIG_MACH_SUN6I)
333 if (pins == SUNXI_GPIO_A) {
334 /* SDC3: PA9-PA14 */
335 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
336 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
337 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
338 sunxi_gpio_set_drv(pin, 2);
339 }
340 } else {
341 /* SDC3: PC6-PC15, PC24 */
342 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
343 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
344 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
345 sunxi_gpio_set_drv(pin, 2);
346 }
347
348 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
349 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
350 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
351 }
352 #endif
353 break;
354
355 default:
356 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
357 break;
358 }
359 }
360
361 int board_mmc_init(bd_t *bis)
362 {
363 __maybe_unused struct mmc *mmc0, *mmc1;
364 __maybe_unused char buf[512];
365
366 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
367 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
368 if (!mmc0)
369 return -1;
370
371 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
372 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
373 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
374 if (!mmc1)
375 return -1;
376 #endif
377
378 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
379 /*
380 * On systems with an emmc (mmc2), figure out if we are booting from
381 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc.
382 * are searched there first. Note we only do this for u-boot proper,
383 * not for the SPL, see spl_boot_device().
384 */
385 if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) {
386 /* Booting from emmc / mmc2, swap */
387 mmc0->block_dev.devnum = 1;
388 mmc1->block_dev.devnum = 0;
389 }
390 #endif
391
392 return 0;
393 }
394 #endif
395
396 void i2c_init_board(void)
397 {
398 #ifdef CONFIG_I2C0_ENABLE
399 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
400 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
401 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
402 clock_twi_onoff(0, 1);
403 #elif defined(CONFIG_MACH_SUN6I)
404 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
405 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
406 clock_twi_onoff(0, 1);
407 #elif defined(CONFIG_MACH_SUN8I)
408 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
409 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
410 clock_twi_onoff(0, 1);
411 #endif
412 #endif
413
414 #ifdef CONFIG_I2C1_ENABLE
415 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
416 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
417 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
418 clock_twi_onoff(1, 1);
419 #elif defined(CONFIG_MACH_SUN5I)
420 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
421 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
422 clock_twi_onoff(1, 1);
423 #elif defined(CONFIG_MACH_SUN6I)
424 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
425 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
426 clock_twi_onoff(1, 1);
427 #elif defined(CONFIG_MACH_SUN8I)
428 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
429 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
430 clock_twi_onoff(1, 1);
431 #endif
432 #endif
433
434 #ifdef CONFIG_I2C2_ENABLE
435 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
436 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
437 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
438 clock_twi_onoff(2, 1);
439 #elif defined(CONFIG_MACH_SUN5I)
440 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
441 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
442 clock_twi_onoff(2, 1);
443 #elif defined(CONFIG_MACH_SUN6I)
444 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
445 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
446 clock_twi_onoff(2, 1);
447 #elif defined(CONFIG_MACH_SUN8I)
448 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
449 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
450 clock_twi_onoff(2, 1);
451 #endif
452 #endif
453
454 #ifdef CONFIG_I2C3_ENABLE
455 #if defined(CONFIG_MACH_SUN6I)
456 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
457 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
458 clock_twi_onoff(3, 1);
459 #elif defined(CONFIG_MACH_SUN7I)
460 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
461 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
462 clock_twi_onoff(3, 1);
463 #endif
464 #endif
465
466 #ifdef CONFIG_I2C4_ENABLE
467 #if defined(CONFIG_MACH_SUN7I)
468 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
469 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
470 clock_twi_onoff(4, 1);
471 #endif
472 #endif
473
474 #ifdef CONFIG_R_I2C_ENABLE
475 clock_twi_onoff(5, 1);
476 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
477 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
478 #endif
479 }
480
481 #ifdef CONFIG_SPL_BUILD
482 void sunxi_board_init(void)
483 {
484 int power_failed = 0;
485 unsigned long ramsize;
486
487 #ifdef CONFIG_SY8106A_POWER
488 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
489 #endif
490
491 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
492 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
493 defined CONFIG_AXP818_POWER
494 power_failed = axp_init();
495
496 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
497 defined CONFIG_AXP818_POWER
498 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
499 #endif
500 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
501 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
502 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
503 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
504 #endif
505 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
506 defined CONFIG_AXP818_POWER
507 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
508 #endif
509
510 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
511 defined CONFIG_AXP818_POWER
512 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
513 #endif
514 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
515 #if !defined(CONFIG_AXP152_POWER)
516 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
517 #endif
518 #ifdef CONFIG_AXP209_POWER
519 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
520 #endif
521
522 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
523 defined(CONFIG_AXP818_POWER)
524 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
525 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
526 #if !defined CONFIG_AXP809_POWER
527 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
528 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
529 #endif
530 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
531 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
532 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
533 #endif
534
535 #ifdef CONFIG_AXP818_POWER
536 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
537 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
538 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
539 #endif
540
541 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
542 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
543 #endif
544 #endif
545 printf("DRAM:");
546 ramsize = sunxi_dram_init();
547 printf(" %d MiB\n", (int)(ramsize >> 20));
548 if (!ramsize)
549 hang();
550
551 /*
552 * Only clock up the CPU to full speed if we are reasonably
553 * assured it's being powered with suitable core voltage
554 */
555 if (!power_failed)
556 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
557 else
558 printf("Failed to set core voltage! Can't set CPU frequency\n");
559 }
560 #endif
561
562 #ifdef CONFIG_USB_GADGET
563 int g_dnl_board_usb_cable_connected(void)
564 {
565 return sunxi_usb_phy_vbus_detect(0);
566 }
567 #endif
568
569 #ifdef CONFIG_SERIAL_TAG
570 void get_board_serial(struct tag_serialnr *serialnr)
571 {
572 char *serial_string;
573 unsigned long long serial;
574
575 serial_string = getenv("serial#");
576
577 if (serial_string) {
578 serial = simple_strtoull(serial_string, NULL, 16);
579
580 serialnr->high = (unsigned int) (serial >> 32);
581 serialnr->low = (unsigned int) (serial & 0xffffffff);
582 } else {
583 serialnr->high = 0;
584 serialnr->low = 0;
585 }
586 }
587 #endif
588
589 /*
590 * Check the SPL header for the "sunxi" variant. If found: parse values
591 * that might have been passed by the loader ("fel" utility), and update
592 * the environment accordingly.
593 */
594 static void parse_spl_header(const uint32_t spl_addr)
595 {
596 struct boot_file_head *spl = (void *)(ulong)spl_addr;
597 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
598 return; /* signature mismatch, no usable header */
599
600 uint8_t spl_header_version = spl->spl_signature[3];
601 if (spl_header_version != SPL_HEADER_VERSION) {
602 printf("sunxi SPL version mismatch: expected %u, got %u\n",
603 SPL_HEADER_VERSION, spl_header_version);
604 return;
605 }
606 if (!spl->fel_script_address)
607 return;
608
609 if (spl->fel_uEnv_length != 0) {
610 /*
611 * data is expected in uEnv.txt compatible format, so "env
612 * import -t" the string(s) at fel_script_address right away.
613 */
614 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
615 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
616 return;
617 }
618 /* otherwise assume .scr format (mkimage-type script) */
619 setenv_hex("fel_scriptaddr", spl->fel_script_address);
620 }
621
622 /*
623 * Note this function gets called multiple times.
624 * It must not make any changes to env variables which already exist.
625 */
626 static void setup_environment(const void *fdt)
627 {
628 char serial_string[17] = { 0 };
629 unsigned int sid[4];
630 uint8_t mac_addr[6];
631 char ethaddr[16];
632 int i, ret;
633
634 ret = sunxi_get_sid(sid);
635 if (ret == 0 && sid[0] != 0) {
636 /*
637 * The single words 1 - 3 of the SID have quite a few bits
638 * which are the same on many models, so we take a crc32
639 * of all 3 words, to get a more unique value.
640 *
641 * Note we only do this on newer SoCs as we cannot change
642 * the algorithm on older SoCs since those have been using
643 * fixed mac-addresses based on only using word 3 for a
644 * long time and changing a fixed mac-address with an
645 * u-boot update is not good.
646 */
647 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
648 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
649 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
650 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
651 #endif
652
653 /* Ensure the NIC specific bytes of the mac are not all 0 */
654 if ((sid[3] & 0xffffff) == 0)
655 sid[3] |= 0x800000;
656
657 for (i = 0; i < 4; i++) {
658 sprintf(ethaddr, "ethernet%d", i);
659 if (!fdt_get_alias(fdt, ethaddr))
660 continue;
661
662 if (i == 0)
663 strcpy(ethaddr, "ethaddr");
664 else
665 sprintf(ethaddr, "eth%daddr", i);
666
667 if (getenv(ethaddr))
668 continue;
669
670 /* Non OUI / registered MAC address */
671 mac_addr[0] = (i << 4) | 0x02;
672 mac_addr[1] = (sid[0] >> 0) & 0xff;
673 mac_addr[2] = (sid[3] >> 24) & 0xff;
674 mac_addr[3] = (sid[3] >> 16) & 0xff;
675 mac_addr[4] = (sid[3] >> 8) & 0xff;
676 mac_addr[5] = (sid[3] >> 0) & 0xff;
677
678 eth_setenv_enetaddr(ethaddr, mac_addr);
679 }
680
681 if (!getenv("serial#")) {
682 snprintf(serial_string, sizeof(serial_string),
683 "%08x%08x", sid[0], sid[3]);
684
685 setenv("serial#", serial_string);
686 }
687 }
688 }
689
690 int misc_init_r(void)
691 {
692 __maybe_unused int ret;
693
694 setenv("fel_booted", NULL);
695 setenv("fel_scriptaddr", NULL);
696 /* determine if we are running in FEL mode */
697 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
698 setenv("fel_booted", "1");
699 parse_spl_header(SPL_ADDR);
700 }
701
702 setup_environment(gd->fdt_blob);
703
704 #ifndef CONFIG_MACH_SUN9I
705 ret = sunxi_usb_phy_probe();
706 if (ret)
707 return ret;
708 #endif
709 sunxi_musb_board_init();
710
711 return 0;
712 }
713
714 int ft_board_setup(void *blob, bd_t *bd)
715 {
716 int __maybe_unused r;
717
718 /*
719 * Call setup_environment again in case the boot fdt has
720 * ethernet aliases the u-boot copy does not have.
721 */
722 setup_environment(blob);
723
724 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
725 r = sunxi_simplefb_setup(blob);
726 if (r)
727 return r;
728 #endif
729 return 0;
730 }
"Das U-Boot" Source Tree