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[people/ms/u-boot.git] / board / sunxi / board.c
1 /*
2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4 *
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
8 *
9 * Some board init for the Allwinner A10-evb board.
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14 #include <common.h>
15 #include <mmc.h>
16 #include <axp_pmic.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/display.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/spl.h>
24 #include <asm/arch/usb_phy.h>
25 #ifndef CONFIG_ARM64
26 #include <asm/armv7.h>
27 #endif
28 #include <asm/gpio.h>
29 #include <asm/io.h>
30 #include <crc.h>
31 #include <environment.h>
32 #include <libfdt.h>
33 #include <nand.h>
34 #include <net.h>
35 #include <sy8106a.h>
36 #include <asm/setup.h>
37
38 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
39 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
40 int soft_i2c_gpio_sda;
41 int soft_i2c_gpio_scl;
42
43 static int soft_i2c_board_init(void)
44 {
45 int ret;
46
47 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
48 if (soft_i2c_gpio_sda < 0) {
49 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
50 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
51 return soft_i2c_gpio_sda;
52 }
53 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
54 if (ret) {
55 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
56 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
57 return ret;
58 }
59
60 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
61 if (soft_i2c_gpio_scl < 0) {
62 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
63 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
64 return soft_i2c_gpio_scl;
65 }
66 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
67 if (ret) {
68 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
69 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
70 return ret;
71 }
72
73 return 0;
74 }
75 #else
76 static int soft_i2c_board_init(void) { return 0; }
77 #endif
78
79 DECLARE_GLOBAL_DATA_PTR;
80
81 void i2c_init_board(void)
82 {
83 #ifdef CONFIG_I2C0_ENABLE
84 #if defined(CONFIG_MACH_SUN4I) || \
85 defined(CONFIG_MACH_SUN5I) || \
86 defined(CONFIG_MACH_SUN7I) || \
87 defined(CONFIG_MACH_SUN8I_R40)
88 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
89 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
90 clock_twi_onoff(0, 1);
91 #elif defined(CONFIG_MACH_SUN6I)
92 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
93 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
94 clock_twi_onoff(0, 1);
95 #elif defined(CONFIG_MACH_SUN8I)
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
97 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
98 clock_twi_onoff(0, 1);
99 #endif
100 #endif
101
102 #ifdef CONFIG_I2C1_ENABLE
103 #if defined(CONFIG_MACH_SUN4I) || \
104 defined(CONFIG_MACH_SUN7I) || \
105 defined(CONFIG_MACH_SUN8I_R40)
106 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
107 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
108 clock_twi_onoff(1, 1);
109 #elif defined(CONFIG_MACH_SUN5I)
110 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
111 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
112 clock_twi_onoff(1, 1);
113 #elif defined(CONFIG_MACH_SUN6I)
114 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
115 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
116 clock_twi_onoff(1, 1);
117 #elif defined(CONFIG_MACH_SUN8I)
118 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
119 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
120 clock_twi_onoff(1, 1);
121 #endif
122 #endif
123
124 #ifdef CONFIG_I2C2_ENABLE
125 #if defined(CONFIG_MACH_SUN4I) || \
126 defined(CONFIG_MACH_SUN7I) || \
127 defined(CONFIG_MACH_SUN8I_R40)
128 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
129 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
130 clock_twi_onoff(2, 1);
131 #elif defined(CONFIG_MACH_SUN5I)
132 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
133 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
134 clock_twi_onoff(2, 1);
135 #elif defined(CONFIG_MACH_SUN6I)
136 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
137 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
138 clock_twi_onoff(2, 1);
139 #elif defined(CONFIG_MACH_SUN8I)
140 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
141 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
142 clock_twi_onoff(2, 1);
143 #endif
144 #endif
145
146 #ifdef CONFIG_I2C3_ENABLE
147 #if defined(CONFIG_MACH_SUN6I)
148 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
149 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
150 clock_twi_onoff(3, 1);
151 #elif defined(CONFIG_MACH_SUN7I) || \
152 defined(CONFIG_MACH_SUN8I_R40)
153 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
154 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
155 clock_twi_onoff(3, 1);
156 #endif
157 #endif
158
159 #ifdef CONFIG_I2C4_ENABLE
160 #if defined(CONFIG_MACH_SUN7I) || \
161 defined(CONFIG_MACH_SUN8I_R40)
162 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
163 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
164 clock_twi_onoff(4, 1);
165 #endif
166 #endif
167
168 #ifdef CONFIG_R_I2C_ENABLE
169 clock_twi_onoff(5, 1);
170 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
171 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
172 #endif
173 }
174
175 /* add board specific code here */
176 int board_init(void)
177 {
178 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
179
180 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
181
182 #ifndef CONFIG_ARM64
183 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
184 debug("id_pfr1: 0x%08x\n", id_pfr1);
185 /* Generic Timer Extension available? */
186 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
187 uint32_t freq;
188
189 debug("Setting CNTFRQ\n");
190
191 /*
192 * CNTFRQ is a secure register, so we will crash if we try to
193 * write this from the non-secure world (read is OK, though).
194 * In case some bootcode has already set the correct value,
195 * we avoid the risk of writing to it.
196 */
197 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
198 if (freq != COUNTER_FREQUENCY) {
199 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
200 freq, COUNTER_FREQUENCY);
201 #ifdef CONFIG_NON_SECURE
202 printf("arch timer frequency is wrong, but cannot adjust it\n");
203 #else
204 asm volatile("mcr p15, 0, %0, c14, c0, 0"
205 : : "r"(COUNTER_FREQUENCY));
206 #endif
207 }
208 }
209 #endif /* !CONFIG_ARM64 */
210
211 ret = axp_gpio_init();
212 if (ret)
213 return ret;
214
215 #ifdef CONFIG_SATAPWR
216 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
217 gpio_request(satapwr_pin, "satapwr");
218 gpio_direction_output(satapwr_pin, 1);
219 #endif
220 #ifdef CONFIG_MACPWR
221 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
222 gpio_request(macpwr_pin, "macpwr");
223 gpio_direction_output(macpwr_pin, 1);
224 #endif
225
226 #ifdef CONFIG_DM_I2C
227 /*
228 * Temporary workaround for enabling I2C clocks until proper sunxi DM
229 * clk, reset and pinctrl drivers land.
230 */
231 i2c_init_board();
232 #endif
233
234 /* Uses dm gpio code so do this here and not in i2c_init_board() */
235 return soft_i2c_board_init();
236 }
237
238 int dram_init(void)
239 {
240 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
241
242 return 0;
243 }
244
245 #if defined(CONFIG_NAND_SUNXI)
246 static void nand_pinmux_setup(void)
247 {
248 unsigned int pin;
249
250 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
251 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
252
253 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
254 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
255 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
256 #endif
257 /* sun4i / sun7i do have a PC23, but it is not used for nand,
258 * only sun7i has a PC24 */
259 #ifdef CONFIG_MACH_SUN7I
260 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
261 #endif
262 }
263
264 static void nand_clock_setup(void)
265 {
266 struct sunxi_ccm_reg *const ccm =
267 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
268
269 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
270 #ifdef CONFIG_MACH_SUN9I
271 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
272 #else
273 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
274 #endif
275 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
276 }
277
278 void board_nand_init(void)
279 {
280 nand_pinmux_setup();
281 nand_clock_setup();
282 #ifndef CONFIG_SPL_BUILD
283 sunxi_nand_init();
284 #endif
285 }
286 #endif
287
288 #ifdef CONFIG_MMC
289 static void mmc_pinmux_setup(int sdc)
290 {
291 unsigned int pin;
292 __maybe_unused int pins;
293
294 switch (sdc) {
295 case 0:
296 /* SDC0: PF0-PF5 */
297 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
298 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
299 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
300 sunxi_gpio_set_drv(pin, 2);
301 }
302 break;
303
304 case 1:
305 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
306
307 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
308 defined(CONFIG_MACH_SUN8I_R40)
309 if (pins == SUNXI_GPIO_H) {
310 /* SDC1: PH22-PH-27 */
311 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
312 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
313 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
314 sunxi_gpio_set_drv(pin, 2);
315 }
316 } else {
317 /* SDC1: PG0-PG5 */
318 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
319 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
320 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
321 sunxi_gpio_set_drv(pin, 2);
322 }
323 }
324 #elif defined(CONFIG_MACH_SUN5I)
325 /* SDC1: PG3-PG8 */
326 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
327 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
328 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
329 sunxi_gpio_set_drv(pin, 2);
330 }
331 #elif defined(CONFIG_MACH_SUN6I)
332 /* SDC1: PG0-PG5 */
333 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
334 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
335 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
336 sunxi_gpio_set_drv(pin, 2);
337 }
338 #elif defined(CONFIG_MACH_SUN8I)
339 if (pins == SUNXI_GPIO_D) {
340 /* SDC1: PD2-PD7 */
341 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
342 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
343 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
344 sunxi_gpio_set_drv(pin, 2);
345 }
346 } else {
347 /* SDC1: PG0-PG5 */
348 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
349 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
350 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
351 sunxi_gpio_set_drv(pin, 2);
352 }
353 }
354 #endif
355 break;
356
357 case 2:
358 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
359
360 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
361 /* SDC2: PC6-PC11 */
362 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
363 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
364 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
365 sunxi_gpio_set_drv(pin, 2);
366 }
367 #elif defined(CONFIG_MACH_SUN5I)
368 if (pins == SUNXI_GPIO_E) {
369 /* SDC2: PE4-PE9 */
370 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
371 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
372 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
373 sunxi_gpio_set_drv(pin, 2);
374 }
375 } else {
376 /* SDC2: PC6-PC15 */
377 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
378 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
379 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
380 sunxi_gpio_set_drv(pin, 2);
381 }
382 }
383 #elif defined(CONFIG_MACH_SUN6I)
384 if (pins == SUNXI_GPIO_A) {
385 /* SDC2: PA9-PA14 */
386 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
387 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
388 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
389 sunxi_gpio_set_drv(pin, 2);
390 }
391 } else {
392 /* SDC2: PC6-PC15, PC24 */
393 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
394 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
395 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
396 sunxi_gpio_set_drv(pin, 2);
397 }
398
399 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
400 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
401 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
402 }
403 #elif defined(CONFIG_MACH_SUN8I_R40)
404 /* SDC2: PC6-PC15, PC24 */
405 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
406 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
407 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
408 sunxi_gpio_set_drv(pin, 2);
409 }
410
411 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
412 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
413 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
414 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
415 /* SDC2: PC5-PC6, PC8-PC16 */
416 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
417 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
418 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
419 sunxi_gpio_set_drv(pin, 2);
420 }
421
422 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
423 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
424 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
425 sunxi_gpio_set_drv(pin, 2);
426 }
427 #elif defined(CONFIG_MACH_SUN9I)
428 /* SDC2: PC6-PC16 */
429 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
430 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
431 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
432 sunxi_gpio_set_drv(pin, 2);
433 }
434 #endif
435 break;
436
437 case 3:
438 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
439
440 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
441 defined(CONFIG_MACH_SUN8I_R40)
442 /* SDC3: PI4-PI9 */
443 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
444 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
445 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
446 sunxi_gpio_set_drv(pin, 2);
447 }
448 #elif defined(CONFIG_MACH_SUN6I)
449 if (pins == SUNXI_GPIO_A) {
450 /* SDC3: PA9-PA14 */
451 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
452 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
453 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
454 sunxi_gpio_set_drv(pin, 2);
455 }
456 } else {
457 /* SDC3: PC6-PC15, PC24 */
458 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
459 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
460 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
461 sunxi_gpio_set_drv(pin, 2);
462 }
463
464 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
465 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
466 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
467 }
468 #endif
469 break;
470
471 default:
472 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
473 break;
474 }
475 }
476
477 int board_mmc_init(bd_t *bis)
478 {
479 __maybe_unused struct mmc *mmc0, *mmc1;
480 __maybe_unused char buf[512];
481
482 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
483 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
484 if (!mmc0)
485 return -1;
486
487 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
488 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
489 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
490 if (!mmc1)
491 return -1;
492 #endif
493
494 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
495 /*
496 * On systems with an emmc (mmc2), figure out if we are booting from
497 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc.
498 * are searched there first. Note we only do this for u-boot proper,
499 * not for the SPL, see spl_boot_device().
500 */
501 if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) {
502 /* Booting from emmc / mmc2, swap */
503 mmc0->block_dev.devnum = 1;
504 mmc1->block_dev.devnum = 0;
505 }
506 #endif
507
508 return 0;
509 }
510 #endif
511
512 #ifdef CONFIG_SPL_BUILD
513 void sunxi_board_init(void)
514 {
515 int power_failed = 0;
516
517 #ifdef CONFIG_SY8106A_POWER
518 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
519 #endif
520
521 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
522 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
523 defined CONFIG_AXP818_POWER
524 power_failed = axp_init();
525
526 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
527 defined CONFIG_AXP818_POWER
528 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
529 #endif
530 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
531 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
532 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
533 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
534 #endif
535 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
536 defined CONFIG_AXP818_POWER
537 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
538 #endif
539
540 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
541 defined CONFIG_AXP818_POWER
542 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
543 #endif
544 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
545 #if !defined(CONFIG_AXP152_POWER)
546 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
547 #endif
548 #ifdef CONFIG_AXP209_POWER
549 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
550 #endif
551
552 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
553 defined(CONFIG_AXP818_POWER)
554 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
555 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
556 #if !defined CONFIG_AXP809_POWER
557 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
558 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
559 #endif
560 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
561 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
562 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
563 #endif
564
565 #ifdef CONFIG_AXP818_POWER
566 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
567 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
568 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
569 #endif
570
571 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
572 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
573 #endif
574 #endif
575 printf("DRAM:");
576 gd->ram_size = sunxi_dram_init();
577 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
578 if (!gd->ram_size)
579 hang();
580
581 /*
582 * Only clock up the CPU to full speed if we are reasonably
583 * assured it's being powered with suitable core voltage
584 */
585 if (!power_failed)
586 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
587 else
588 printf("Failed to set core voltage! Can't set CPU frequency\n");
589 }
590 #endif
591
592 #ifdef CONFIG_USB_GADGET
593 int g_dnl_board_usb_cable_connected(void)
594 {
595 return sunxi_usb_phy_vbus_detect(0);
596 }
597 #endif
598
599 #ifdef CONFIG_SERIAL_TAG
600 void get_board_serial(struct tag_serialnr *serialnr)
601 {
602 char *serial_string;
603 unsigned long long serial;
604
605 serial_string = getenv("serial#");
606
607 if (serial_string) {
608 serial = simple_strtoull(serial_string, NULL, 16);
609
610 serialnr->high = (unsigned int) (serial >> 32);
611 serialnr->low = (unsigned int) (serial & 0xffffffff);
612 } else {
613 serialnr->high = 0;
614 serialnr->low = 0;
615 }
616 }
617 #endif
618
619 /*
620 * Check the SPL header for the "sunxi" variant. If found: parse values
621 * that might have been passed by the loader ("fel" utility), and update
622 * the environment accordingly.
623 */
624 static void parse_spl_header(const uint32_t spl_addr)
625 {
626 struct boot_file_head *spl = (void *)(ulong)spl_addr;
627 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
628 return; /* signature mismatch, no usable header */
629
630 uint8_t spl_header_version = spl->spl_signature[3];
631 if (spl_header_version != SPL_HEADER_VERSION) {
632 printf("sunxi SPL version mismatch: expected %u, got %u\n",
633 SPL_HEADER_VERSION, spl_header_version);
634 return;
635 }
636 if (!spl->fel_script_address)
637 return;
638
639 if (spl->fel_uEnv_length != 0) {
640 /*
641 * data is expected in uEnv.txt compatible format, so "env
642 * import -t" the string(s) at fel_script_address right away.
643 */
644 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
645 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
646 return;
647 }
648 /* otherwise assume .scr format (mkimage-type script) */
649 setenv_hex("fel_scriptaddr", spl->fel_script_address);
650 }
651
652 /*
653 * Note this function gets called multiple times.
654 * It must not make any changes to env variables which already exist.
655 */
656 static void setup_environment(const void *fdt)
657 {
658 char serial_string[17] = { 0 };
659 unsigned int sid[4];
660 uint8_t mac_addr[6];
661 char ethaddr[16];
662 int i, ret;
663
664 ret = sunxi_get_sid(sid);
665 if (ret == 0 && sid[0] != 0) {
666 /*
667 * The single words 1 - 3 of the SID have quite a few bits
668 * which are the same on many models, so we take a crc32
669 * of all 3 words, to get a more unique value.
670 *
671 * Note we only do this on newer SoCs as we cannot change
672 * the algorithm on older SoCs since those have been using
673 * fixed mac-addresses based on only using word 3 for a
674 * long time and changing a fixed mac-address with an
675 * u-boot update is not good.
676 */
677 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
678 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
679 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
680 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
681 #endif
682
683 /* Ensure the NIC specific bytes of the mac are not all 0 */
684 if ((sid[3] & 0xffffff) == 0)
685 sid[3] |= 0x800000;
686
687 for (i = 0; i < 4; i++) {
688 sprintf(ethaddr, "ethernet%d", i);
689 if (!fdt_get_alias(fdt, ethaddr))
690 continue;
691
692 if (i == 0)
693 strcpy(ethaddr, "ethaddr");
694 else
695 sprintf(ethaddr, "eth%daddr", i);
696
697 if (getenv(ethaddr))
698 continue;
699
700 /* Non OUI / registered MAC address */
701 mac_addr[0] = (i << 4) | 0x02;
702 mac_addr[1] = (sid[0] >> 0) & 0xff;
703 mac_addr[2] = (sid[3] >> 24) & 0xff;
704 mac_addr[3] = (sid[3] >> 16) & 0xff;
705 mac_addr[4] = (sid[3] >> 8) & 0xff;
706 mac_addr[5] = (sid[3] >> 0) & 0xff;
707
708 eth_setenv_enetaddr(ethaddr, mac_addr);
709 }
710
711 if (!getenv("serial#")) {
712 snprintf(serial_string, sizeof(serial_string),
713 "%08x%08x", sid[0], sid[3]);
714
715 env_set("serial#", serial_string);
716 }
717 }
718 }
719
720 int misc_init_r(void)
721 {
722 __maybe_unused int ret;
723
724 env_set("fel_booted", NULL);
725 env_set("fel_scriptaddr", NULL);
726 /* determine if we are running in FEL mode */
727 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */
728 env_set("fel_booted", "1");
729 parse_spl_header(SPL_ADDR);
730 }
731
732 setup_environment(gd->fdt_blob);
733
734 #ifndef CONFIG_MACH_SUN9I
735 ret = sunxi_usb_phy_probe();
736 if (ret)
737 return ret;
738 #endif
739 sunxi_musb_board_init();
740
741 return 0;
742 }
743
744 int ft_board_setup(void *blob, bd_t *bd)
745 {
746 int __maybe_unused r;
747
748 /*
749 * Call setup_environment again in case the boot fdt has
750 * ethernet aliases the u-boot copy does not have.
751 */
752 setup_environment(blob);
753
754 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
755 r = sunxi_simplefb_setup(blob);
756 if (r)
757 return r;
758 #endif
759 return 0;
760 }
761
762 #ifdef CONFIG_SPL_LOAD_FIT
763 int board_fit_config_name_match(const char *name)
764 {
765 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
766 const char *cmp_str = (void *)(ulong)SPL_ADDR;
767
768 /* Check if there is a DT name stored in the SPL header and use that. */
769 if (spl->dt_name_offset) {
770 cmp_str += spl->dt_name_offset;
771 } else {
772 #ifdef CONFIG_DEFAULT_DEVICE_TREE
773 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
774 #else
775 return 0;
776 #endif
777 };
778
779 /* Differentiate the two Pine64 board DTs by their DRAM size. */
780 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
781 if ((gd->ram_size > 512 * 1024 * 1024))
782 return !strstr(name, "plus");
783 else
784 return !!strstr(name, "plus");
785 } else {
786 return strcmp(name, cmp_str);
787 }
788 }
789 #endif
"Das U-Boot" Source Tree