2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * Some board init for the Allwinner A10-evb board.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/display.h>
20 #include <asm/arch/dram.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm/arch/spl.h>
24 #include <asm/arch/usb_phy.h>
26 #include <asm/armv7.h>
31 #include <environment.h>
37 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
38 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
39 int soft_i2c_gpio_sda
;
40 int soft_i2c_gpio_scl
;
42 static int soft_i2c_board_init(void)
46 soft_i2c_gpio_sda
= sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA
);
47 if (soft_i2c_gpio_sda
< 0) {
48 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA
, soft_i2c_gpio_sda
);
50 return soft_i2c_gpio_sda
;
52 ret
= gpio_request(soft_i2c_gpio_sda
, "soft-i2c-sda");
54 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA
, ret
);
59 soft_i2c_gpio_scl
= sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL
);
60 if (soft_i2c_gpio_scl
< 0) {
61 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL
, soft_i2c_gpio_scl
);
63 return soft_i2c_gpio_scl
;
65 ret
= gpio_request(soft_i2c_gpio_scl
, "soft-i2c-scl");
67 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL
, ret
);
75 static int soft_i2c_board_init(void) { return 0; }
78 DECLARE_GLOBAL_DATA_PTR
;
80 void i2c_init_board(void)
82 #ifdef CONFIG_I2C0_ENABLE
83 #if defined(CONFIG_MACH_SUN4I) || \
84 defined(CONFIG_MACH_SUN5I) || \
85 defined(CONFIG_MACH_SUN7I) || \
86 defined(CONFIG_MACH_SUN8I_R40)
87 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0
);
88 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0
);
89 clock_twi_onoff(0, 1);
90 #elif defined(CONFIG_MACH_SUN6I)
91 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0
);
92 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0
);
93 clock_twi_onoff(0, 1);
94 #elif defined(CONFIG_MACH_SUN8I)
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0
);
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0
);
97 clock_twi_onoff(0, 1);
101 #ifdef CONFIG_I2C1_ENABLE
102 #if defined(CONFIG_MACH_SUN4I) || \
103 defined(CONFIG_MACH_SUN7I) || \
104 defined(CONFIG_MACH_SUN8I_R40)
105 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1
);
106 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1
);
107 clock_twi_onoff(1, 1);
108 #elif defined(CONFIG_MACH_SUN5I)
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1
);
110 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1
);
111 clock_twi_onoff(1, 1);
112 #elif defined(CONFIG_MACH_SUN6I)
113 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1
);
114 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1
);
115 clock_twi_onoff(1, 1);
116 #elif defined(CONFIG_MACH_SUN8I)
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1
);
118 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1
);
119 clock_twi_onoff(1, 1);
123 #ifdef CONFIG_I2C2_ENABLE
124 #if defined(CONFIG_MACH_SUN4I) || \
125 defined(CONFIG_MACH_SUN7I) || \
126 defined(CONFIG_MACH_SUN8I_R40)
127 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2
);
128 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2
);
129 clock_twi_onoff(2, 1);
130 #elif defined(CONFIG_MACH_SUN5I)
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2
);
132 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2
);
133 clock_twi_onoff(2, 1);
134 #elif defined(CONFIG_MACH_SUN6I)
135 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2
);
136 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2
);
137 clock_twi_onoff(2, 1);
138 #elif defined(CONFIG_MACH_SUN8I)
139 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2
);
140 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2
);
141 clock_twi_onoff(2, 1);
145 #ifdef CONFIG_I2C3_ENABLE
146 #if defined(CONFIG_MACH_SUN6I)
147 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3
);
148 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3
);
149 clock_twi_onoff(3, 1);
150 #elif defined(CONFIG_MACH_SUN7I) || \
151 defined(CONFIG_MACH_SUN8I_R40)
152 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3
);
153 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3
);
154 clock_twi_onoff(3, 1);
158 #ifdef CONFIG_I2C4_ENABLE
159 #if defined(CONFIG_MACH_SUN7I) || \
160 defined(CONFIG_MACH_SUN8I_R40)
161 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4
);
162 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4
);
163 clock_twi_onoff(4, 1);
167 #ifdef CONFIG_R_I2C_ENABLE
168 clock_twi_onoff(5, 1);
169 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI
);
170 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI
);
174 /* add board specific code here */
177 __maybe_unused
int id_pfr1
, ret
, satapwr_pin
, macpwr_pin
;
179 gd
->bd
->bi_boot_params
= (PHYS_SDRAM_0
+ 0x100);
182 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1
));
183 debug("id_pfr1: 0x%08x\n", id_pfr1
);
184 /* Generic Timer Extension available? */
185 if ((id_pfr1
>> CPUID_ARM_GENTIMER_SHIFT
) & 0xf) {
188 debug("Setting CNTFRQ\n");
191 * CNTFRQ is a secure register, so we will crash if we try to
192 * write this from the non-secure world (read is OK, though).
193 * In case some bootcode has already set the correct value,
194 * we avoid the risk of writing to it.
196 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq
));
197 if (freq
!= COUNTER_FREQUENCY
) {
198 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
199 freq
, COUNTER_FREQUENCY
);
200 #ifdef CONFIG_NON_SECURE
201 printf("arch timer frequency is wrong, but cannot adjust it\n");
203 asm volatile("mcr p15, 0, %0, c14, c0, 0"
204 : : "r"(COUNTER_FREQUENCY
));
208 #endif /* !CONFIG_ARM64 */
210 ret
= axp_gpio_init();
214 #ifdef CONFIG_SATAPWR
215 satapwr_pin
= sunxi_name_to_gpio(CONFIG_SATAPWR
);
216 gpio_request(satapwr_pin
, "satapwr");
217 gpio_direction_output(satapwr_pin
, 1);
220 macpwr_pin
= sunxi_name_to_gpio(CONFIG_MACPWR
);
221 gpio_request(macpwr_pin
, "macpwr");
222 gpio_direction_output(macpwr_pin
, 1);
227 * Temporary workaround for enabling I2C clocks until proper sunxi DM
228 * clk, reset and pinctrl drivers land.
233 /* Uses dm gpio code so do this here and not in i2c_init_board() */
234 return soft_i2c_board_init();
239 gd
->ram_size
= get_ram_size((long *)PHYS_SDRAM_0
, PHYS_SDRAM_0_SIZE
);
244 #if defined(CONFIG_NAND_SUNXI)
245 static void nand_pinmux_setup(void)
249 for (pin
= SUNXI_GPC(0); pin
<= SUNXI_GPC(19); pin
++)
250 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_NAND
);
252 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
253 for (pin
= SUNXI_GPC(20); pin
<= SUNXI_GPC(22); pin
++)
254 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_NAND
);
256 /* sun4i / sun7i do have a PC23, but it is not used for nand,
257 * only sun7i has a PC24 */
258 #ifdef CONFIG_MACH_SUN7I
259 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND
);
263 static void nand_clock_setup(void)
265 struct sunxi_ccm_reg
*const ccm
=
266 (struct sunxi_ccm_reg
*)SUNXI_CCM_BASE
;
268 setbits_le32(&ccm
->ahb_gate0
, (CLK_GATE_OPEN
<< AHB_GATE_OFFSET_NAND0
));
269 #ifdef CONFIG_MACH_SUN9I
270 setbits_le32(&ccm
->ahb_gate1
, (1 << AHB_GATE_OFFSET_DMA
));
272 setbits_le32(&ccm
->ahb_gate0
, (1 << AHB_GATE_OFFSET_DMA
));
274 setbits_le32(&ccm
->nand0_clk_cfg
, CCM_NAND_CTRL_ENABLE
| AHB_DIV_1
);
277 void board_nand_init(void)
281 #ifndef CONFIG_SPL_BUILD
287 #ifdef CONFIG_GENERIC_MMC
288 static void mmc_pinmux_setup(int sdc
)
291 __maybe_unused
int pins
;
296 for (pin
= SUNXI_GPF(0); pin
<= SUNXI_GPF(5); pin
++) {
297 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPF_SDC0
);
298 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
299 sunxi_gpio_set_drv(pin
, 2);
304 pins
= sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS
);
306 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
307 defined(CONFIG_MACH_SUN8I_R40)
308 if (pins
== SUNXI_GPIO_H
) {
309 /* SDC1: PH22-PH-27 */
310 for (pin
= SUNXI_GPH(22); pin
<= SUNXI_GPH(27); pin
++) {
311 sunxi_gpio_set_cfgpin(pin
, SUN4I_GPH_SDC1
);
312 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
313 sunxi_gpio_set_drv(pin
, 2);
317 for (pin
= SUNXI_GPG(0); pin
<= SUNXI_GPG(5); pin
++) {
318 sunxi_gpio_set_cfgpin(pin
, SUN4I_GPG_SDC1
);
319 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
320 sunxi_gpio_set_drv(pin
, 2);
323 #elif defined(CONFIG_MACH_SUN5I)
325 for (pin
= SUNXI_GPG(3); pin
<= SUNXI_GPG(8); pin
++) {
326 sunxi_gpio_set_cfgpin(pin
, SUN5I_GPG_SDC1
);
327 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
328 sunxi_gpio_set_drv(pin
, 2);
330 #elif defined(CONFIG_MACH_SUN6I)
332 for (pin
= SUNXI_GPG(0); pin
<= SUNXI_GPG(5); pin
++) {
333 sunxi_gpio_set_cfgpin(pin
, SUN6I_GPG_SDC1
);
334 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
335 sunxi_gpio_set_drv(pin
, 2);
337 #elif defined(CONFIG_MACH_SUN8I)
338 if (pins
== SUNXI_GPIO_D
) {
340 for (pin
= SUNXI_GPD(2); pin
<= SUNXI_GPD(7); pin
++) {
341 sunxi_gpio_set_cfgpin(pin
, SUN8I_GPD_SDC1
);
342 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
343 sunxi_gpio_set_drv(pin
, 2);
347 for (pin
= SUNXI_GPG(0); pin
<= SUNXI_GPG(5); pin
++) {
348 sunxi_gpio_set_cfgpin(pin
, SUN8I_GPG_SDC1
);
349 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
350 sunxi_gpio_set_drv(pin
, 2);
357 pins
= sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS
);
359 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
361 for (pin
= SUNXI_GPC(6); pin
<= SUNXI_GPC(11); pin
++) {
362 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
363 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
364 sunxi_gpio_set_drv(pin
, 2);
366 #elif defined(CONFIG_MACH_SUN5I)
367 if (pins
== SUNXI_GPIO_E
) {
369 for (pin
= SUNXI_GPE(4); pin
<= SUNXI_GPD(9); pin
++) {
370 sunxi_gpio_set_cfgpin(pin
, SUN5I_GPE_SDC2
);
371 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
372 sunxi_gpio_set_drv(pin
, 2);
376 for (pin
= SUNXI_GPC(6); pin
<= SUNXI_GPC(15); pin
++) {
377 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
378 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
379 sunxi_gpio_set_drv(pin
, 2);
382 #elif defined(CONFIG_MACH_SUN6I)
383 if (pins
== SUNXI_GPIO_A
) {
385 for (pin
= SUNXI_GPA(9); pin
<= SUNXI_GPA(14); pin
++) {
386 sunxi_gpio_set_cfgpin(pin
, SUN6I_GPA_SDC2
);
387 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
388 sunxi_gpio_set_drv(pin
, 2);
391 /* SDC2: PC6-PC15, PC24 */
392 for (pin
= SUNXI_GPC(6); pin
<= SUNXI_GPC(15); pin
++) {
393 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
394 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
395 sunxi_gpio_set_drv(pin
, 2);
398 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2
);
399 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP
);
400 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
402 #elif defined(CONFIG_MACH_SUN8I_R40)
403 /* SDC2: PC6-PC15, PC24 */
404 for (pin
= SUNXI_GPC(6); pin
<= SUNXI_GPC(15); pin
++) {
405 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
406 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
407 sunxi_gpio_set_drv(pin
, 2);
410 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2
);
411 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP
);
412 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
413 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
414 /* SDC2: PC5-PC6, PC8-PC16 */
415 for (pin
= SUNXI_GPC(5); pin
<= SUNXI_GPC(6); pin
++) {
416 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
417 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
418 sunxi_gpio_set_drv(pin
, 2);
421 for (pin
= SUNXI_GPC(8); pin
<= SUNXI_GPC(16); pin
++) {
422 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
423 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
424 sunxi_gpio_set_drv(pin
, 2);
426 #elif defined(CONFIG_MACH_SUN9I)
428 for (pin
= SUNXI_GPC(6); pin
<= SUNXI_GPC(16); pin
++) {
429 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPC_SDC2
);
430 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
431 sunxi_gpio_set_drv(pin
, 2);
437 pins
= sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS
);
439 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
440 defined(CONFIG_MACH_SUN8I_R40)
442 for (pin
= SUNXI_GPI(4); pin
<= SUNXI_GPI(9); pin
++) {
443 sunxi_gpio_set_cfgpin(pin
, SUNXI_GPI_SDC3
);
444 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
445 sunxi_gpio_set_drv(pin
, 2);
447 #elif defined(CONFIG_MACH_SUN6I)
448 if (pins
== SUNXI_GPIO_A
) {
450 for (pin
= SUNXI_GPA(9); pin
<= SUNXI_GPA(14); pin
++) {
451 sunxi_gpio_set_cfgpin(pin
, SUN6I_GPA_SDC3
);
452 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
453 sunxi_gpio_set_drv(pin
, 2);
456 /* SDC3: PC6-PC15, PC24 */
457 for (pin
= SUNXI_GPC(6); pin
<= SUNXI_GPC(15); pin
++) {
458 sunxi_gpio_set_cfgpin(pin
, SUN6I_GPC_SDC3
);
459 sunxi_gpio_set_pull(pin
, SUNXI_GPIO_PULL_UP
);
460 sunxi_gpio_set_drv(pin
, 2);
463 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3
);
464 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP
);
465 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
471 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc
);
476 int board_mmc_init(bd_t
*bis
)
478 __maybe_unused
struct mmc
*mmc0
, *mmc1
;
479 __maybe_unused
char buf
[512];
481 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT
);
482 mmc0
= sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT
);
486 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
487 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA
);
488 mmc1
= sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA
);
493 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
495 * On systems with an emmc (mmc2), figure out if we are booting from
496 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc.
497 * are searched there first. Note we only do this for u-boot proper,
498 * not for the SPL, see spl_boot_device().
500 if (readb(SPL_ADDR
+ 0x28) == SUNXI_BOOTED_FROM_MMC2
) {
501 /* Booting from emmc / mmc2, swap */
502 mmc0
->block_dev
.devnum
= 1;
503 mmc1
->block_dev
.devnum
= 0;
511 #ifdef CONFIG_SPL_BUILD
512 void sunxi_board_init(void)
514 int power_failed
= 0;
515 unsigned long ramsize
;
517 #ifdef CONFIG_SY8106A_POWER
518 power_failed
= sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT
);
521 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
522 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
523 defined CONFIG_AXP818_POWER
524 power_failed
= axp_init();
526 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
527 defined CONFIG_AXP818_POWER
528 power_failed
|= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT
);
530 power_failed
|= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT
);
531 power_failed
|= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT
);
532 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
533 power_failed
|= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT
);
535 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
536 defined CONFIG_AXP818_POWER
537 power_failed
|= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT
);
540 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
541 defined CONFIG_AXP818_POWER
542 power_failed
|= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT
);
544 power_failed
|= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT
);
545 #if !defined(CONFIG_AXP152_POWER)
546 power_failed
|= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT
);
548 #ifdef CONFIG_AXP209_POWER
549 power_failed
|= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT
);
552 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
553 defined(CONFIG_AXP818_POWER)
554 power_failed
|= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT
);
555 power_failed
|= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT
);
556 #if !defined CONFIG_AXP809_POWER
557 power_failed
|= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT
);
558 power_failed
|= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT
);
560 power_failed
|= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT
);
561 power_failed
|= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT
);
562 power_failed
|= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT
);
565 #ifdef CONFIG_AXP818_POWER
566 power_failed
|= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT
);
567 power_failed
|= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT
);
568 power_failed
|= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT
);
571 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
572 power_failed
|= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON
));
576 ramsize
= sunxi_dram_init();
577 printf(" %d MiB\n", (int)(ramsize
>> 20));
582 * Only clock up the CPU to full speed if we are reasonably
583 * assured it's being powered with suitable core voltage
586 clock_set_pll1(CONFIG_SYS_CLK_FREQ
);
588 printf("Failed to set core voltage! Can't set CPU frequency\n");
592 #ifdef CONFIG_USB_GADGET
593 int g_dnl_board_usb_cable_connected(void)
595 return sunxi_usb_phy_vbus_detect(0);
599 #ifdef CONFIG_SERIAL_TAG
600 void get_board_serial(struct tag_serialnr
*serialnr
)
603 unsigned long long serial
;
605 serial_string
= getenv("serial#");
608 serial
= simple_strtoull(serial_string
, NULL
, 16);
610 serialnr
->high
= (unsigned int) (serial
>> 32);
611 serialnr
->low
= (unsigned int) (serial
& 0xffffffff);
620 * Check the SPL header for the "sunxi" variant. If found: parse values
621 * that might have been passed by the loader ("fel" utility), and update
622 * the environment accordingly.
624 static void parse_spl_header(const uint32_t spl_addr
)
626 struct boot_file_head
*spl
= (void *)(ulong
)spl_addr
;
627 if (memcmp(spl
->spl_signature
, SPL_SIGNATURE
, 3) != 0)
628 return; /* signature mismatch, no usable header */
630 uint8_t spl_header_version
= spl
->spl_signature
[3];
631 if (spl_header_version
!= SPL_HEADER_VERSION
) {
632 printf("sunxi SPL version mismatch: expected %u, got %u\n",
633 SPL_HEADER_VERSION
, spl_header_version
);
636 if (!spl
->fel_script_address
)
639 if (spl
->fel_uEnv_length
!= 0) {
641 * data is expected in uEnv.txt compatible format, so "env
642 * import -t" the string(s) at fel_script_address right away.
644 himport_r(&env_htab
, (char *)(uintptr_t)spl
->fel_script_address
,
645 spl
->fel_uEnv_length
, '\n', H_NOCLEAR
, 0, 0, NULL
);
648 /* otherwise assume .scr format (mkimage-type script) */
649 setenv_hex("fel_scriptaddr", spl
->fel_script_address
);
653 * Note this function gets called multiple times.
654 * It must not make any changes to env variables which already exist.
656 static void setup_environment(const void *fdt
)
658 char serial_string
[17] = { 0 };
664 ret
= sunxi_get_sid(sid
);
665 if (ret
== 0 && sid
[0] != 0) {
667 * The single words 1 - 3 of the SID have quite a few bits
668 * which are the same on many models, so we take a crc32
669 * of all 3 words, to get a more unique value.
671 * Note we only do this on newer SoCs as we cannot change
672 * the algorithm on older SoCs since those have been using
673 * fixed mac-addresses based on only using word 3 for a
674 * long time and changing a fixed mac-address with an
675 * u-boot update is not good.
677 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
678 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
679 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
680 sid
[3] = crc32(0, (unsigned char *)&sid
[1], 12);
683 /* Ensure the NIC specific bytes of the mac are not all 0 */
684 if ((sid
[3] & 0xffffff) == 0)
687 for (i
= 0; i
< 4; i
++) {
688 sprintf(ethaddr
, "ethernet%d", i
);
689 if (!fdt_get_alias(fdt
, ethaddr
))
693 strcpy(ethaddr
, "ethaddr");
695 sprintf(ethaddr
, "eth%daddr", i
);
700 /* Non OUI / registered MAC address */
701 mac_addr
[0] = (i
<< 4) | 0x02;
702 mac_addr
[1] = (sid
[0] >> 0) & 0xff;
703 mac_addr
[2] = (sid
[3] >> 24) & 0xff;
704 mac_addr
[3] = (sid
[3] >> 16) & 0xff;
705 mac_addr
[4] = (sid
[3] >> 8) & 0xff;
706 mac_addr
[5] = (sid
[3] >> 0) & 0xff;
708 eth_setenv_enetaddr(ethaddr
, mac_addr
);
711 if (!getenv("serial#")) {
712 snprintf(serial_string
, sizeof(serial_string
),
713 "%08x%08x", sid
[0], sid
[3]);
715 setenv("serial#", serial_string
);
720 int misc_init_r(void)
722 __maybe_unused
int ret
;
724 setenv("fel_booted", NULL
);
725 setenv("fel_scriptaddr", NULL
);
726 /* determine if we are running in FEL mode */
727 if (!is_boot0_magic(SPL_ADDR
+ 4)) { /* eGON.BT0 */
728 setenv("fel_booted", "1");
729 parse_spl_header(SPL_ADDR
);
732 setup_environment(gd
->fdt_blob
);
734 #ifndef CONFIG_MACH_SUN9I
735 ret
= sunxi_usb_phy_probe();
739 sunxi_musb_board_init();
744 int ft_board_setup(void *blob
, bd_t
*bd
)
746 int __maybe_unused r
;
749 * Call setup_environment again in case the boot fdt has
750 * ethernet aliases the u-boot copy does not have.
752 setup_environment(blob
);
754 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
755 r
= sunxi_simplefb_setup(blob
);