board/sx1/lowlevel_init.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2003
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * -- Some bits of code used from rrload's head_OMAP1510.s --
   8  * Copyright (C) 2002 RidgeRun, Inc.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <config.h>
  30 #include <version.h>
  31
  32 #if defined(CONFIG_OMAP1510)
  33 #include <./configs/omap1510.h>
  34 #endif
  35
  36 #define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
  37
  38
  39 _TEXT_BASE:
  40         .word   CONFIG_SYS_TEXT_BASE     /* sdram load addr from config.mk */
  41
  42 .globl lowlevel_init
  43 lowlevel_init:
  44
  45         /*
  46          * Configure 1510 pins functions to match our board.
  47          */
  48         ldr     r0, REG_PULL_DWN_CTRL_0
  49         ldr     r1, VAL_PULL_DWN_CTRL_0
  50         str     r1, [r0]
  51         ldr     r0, REG_PULL_DWN_CTRL_1
  52         ldr     r1, VAL_PULL_DWN_CTRL_1
  53         str     r1, [r0]
  54         ldr     r0, REG_PULL_DWN_CTRL_2
  55         ldr     r1, VAL_PULL_DWN_CTRL_2
  56         str     r1, [r0]
  57         ldr     r0, REG_PULL_DWN_CTRL_3
  58         ldr     r1, VAL_PULL_DWN_CTRL_3
  59         str     r1, [r0]
  60         ldr     r0, REG_FUNC_MUX_CTRL_4
  61         ldr     r1, VAL_FUNC_MUX_CTRL_4
  62         str     r1, [r0]
  63         ldr     r0, REG_FUNC_MUX_CTRL_5
  64         ldr     r1, VAL_FUNC_MUX_CTRL_5
  65         str     r1, [r0]
  66         ldr     r0, REG_FUNC_MUX_CTRL_6
  67         ldr     r1, VAL_FUNC_MUX_CTRL_6
  68         str     r1, [r0]
  69         ldr     r0, REG_FUNC_MUX_CTRL_7
  70         ldr     r1, VAL_FUNC_MUX_CTRL_7
  71         str     r1, [r0]
  72         ldr     r0, REG_FUNC_MUX_CTRL_8
  73         ldr     r1, VAL_FUNC_MUX_CTRL_8
  74         str     r1, [r0]
  75         ldr     r0, REG_FUNC_MUX_CTRL_9
  76         ldr     r1, VAL_FUNC_MUX_CTRL_9
  77         str     r1, [r0]
  78         ldr     r0, REG_FUNC_MUX_CTRL_A
  79         ldr     r1, VAL_FUNC_MUX_CTRL_A
  80         str     r1, [r0]
  81         ldr     r0, REG_FUNC_MUX_CTRL_B
  82         ldr     r1, VAL_FUNC_MUX_CTRL_B
  83         str     r1, [r0]
  84         ldr     r0, REG_FUNC_MUX_CTRL_C
  85         ldr     r1, VAL_FUNC_MUX_CTRL_C
  86         str     r1, [r0]
  87         ldr     r0, REG_FUNC_MUX_CTRL_D
  88         ldr     r1, VAL_FUNC_MUX_CTRL_D
  89         str     r1, [r0]
  90         ldr     r0, REG_VOLTAGE_CTRL_0
  91         ldr     r1, VAL_VOLTAGE_CTRL_0
  92         str     r1, [r0]
  93         ldr     r0, REG_TEST_DBG_CTRL_0
  94         ldr     r1, VAL_TEST_DBG_CTRL_0
  95         str     r1, [r0]
  96         ldr     r0, REG_MOD_CONF_CTRL_0
  97         ldr     r1, VAL_MOD_CONF_CTRL_0
  98         str     r1, [r0]
  99
 100         /* Move to 1510 mode */
 101         ldr     r0, REG_COMP_MODE_CTRL_0
 102         ldr     r1, VAL_COMP_MODE_CTRL_0
 103         str     r1, [r0]
 104
 105         /* Set up Traffic Ctlr*/
 106         ldr r0, REG_TC_IMIF_PRIO
 107         mov r1, #0x0
 108         str r1, [r0]
 109         ldr r0, REG_TC_EMIFS_PRIO
 110         str r1, [r0]
 111         ldr r0, REG_TC_EMIFF_PRIO
 112         str r1, [r0]
 113
 114         ldr r0, REG_TC_EMIFS_CONFIG
 115         ldr r1, [r0]
 116         bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
 117         bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
 118         str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
 119
 120         ldr r0, _GPIO_PIN_CONTROL_REG
 121         mov r1,#0
 122         orr r1, r1, #0x0001 /* M_PCM_SYNC */
 123         orr r1, r1, #0x4000 /* IPC_ACTIVE */
 124         strh r1,[r0]
 125
 126         ldr r0, _GPIO_DIR_CONTROL_REG
 127         mov r1,#0
 128         bic r1, r1, #0x0001 /* M_PCM_SYNC */
 129         bic r1, r1, #0x4000 /* IPC_ACTIVE */
 130         strh r1,[r0]
 131
 132         ldr r0, _GPIO_DATA_OUTPUT_REG
 133         mov r1,#0
 134         bic r1, r1, #0x0001 /* M_PCM_SYNC */
 135         orr r1, r1, #0x4000 /* IPC_ACTIVE */
 136         strh r1,[r0]
 137
 138         /* Setup some clock domains */
 139         ldr r1, =OMAP1510_CLKS
 140         ldr r0, REG_ARM_IDLECT2
 141         strh r1, [r0]  /* CLKM, Clock domain control. */
 142
 143         mov r1, #0x01  /* PER_EN bit */
 144         ldr r0, REG_ARM_RSTCT2
 145         strh r1, [r0]  /* CLKM; Peripheral reset. */
 146
 147         /* Set CLKM to Sync-Scalable  */
 148         /* I supposidly need to enable the dsp clock before switching */
 149         mov r1, #0x1000
 150         ldr r0, REG_ARM_SYSST
 151         strh r1, [r0]
 152         mov r0, #0x400
 153 1:
 154         subs r0, r0, #0x1   /* wait for any bubbles to finish */
 155         bne 1b
 156
 157         ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
 158         ldr r0, REG_ARM_CKCTL
 159         strh r1, [r0]
 160
 161         /* setup DPLL 1 */
 162         ldr r1, VAL_DPLL1_CTL
 163         ldr r0, REG_DPLL1_CTL
 164         strh r1, [r0]
 165         ands r1, r1, #0x10  /* Check if PLL is enabled. */
 166         beq lock_end        /* Do not look for lock if BYPASS selected */
 167 2:
 168         ldrh r1, [r0]
 169         ands r1, r1, #0x01  /* Check the LOCK bit. */
 170         beq 2b              /* ...loop until bit goes hi. */
 171 lock_end:
 172
 173         /* Set memory timings corresponding to the new clock speed */
 174
 175         /* Check execution location to determine current execution location
 176          * and branch to appropriate initialization code.
 177          */
 178         mov r0, #0x10000000                 /* Load physical SDRAM base. */
 179         mov r1, pc                          /* Get current execution location. */
 180         cmp r1, r0                          /* Compare. */
 181         bge skip_sdram                      /* Skip over EMIF-fast initialization if running from SDRAM. */
 182
 183         /*
 184          * Delay for SDRAM initialization.
 185          */
 186         mov r3, #0x1800                        /* value should be checked */
 187 3:
 188         subs r3, r3, #0x1                     /* Decrement count */
 189         bne 3b
 190
 191         /*
 192          * Set SDRAM control values. Disable refresh before MRS command.
 193          */
 194         ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
 195         bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
 196         orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
 197         orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
 198         ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
 199         str r3, [r2]                        /* Store the passed value with AR disabled. */
 200
 201         ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
 202         ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
 203         str r1, [r2]                        /* Store the passed value.*/
 204
 205         ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
 206         str r0, [r2]                        /* Store the passed value. */
 207
 208         /*
 209          * Delay for SDRAM initialization.
 210          */
 211         mov r3, #0x1800
 212 4:
 213         subs r3, r3, #1                     /* Decrement count. */
 214         bne 4b
 215
 216 skip_sdram:
 217
 218         /* slow interface */
 219         ldr r1, VAL_TC_EMIFS_CS0_CONFIG
 220         ldr r0, REG_TC_EMIFS_CS0_CONFIG
 221         str r1, [r0] /* Chip Select 0 */
 222         ldr r1, VAL_TC_EMIFS_CS1_CONFIG
 223         ldr r0, REG_TC_EMIFS_CS1_CONFIG
 224         str r1, [r0] /* Chip Select 1 */
 225         ldr r1, VAL_TC_EMIFS_CS2_CONFIG
 226         ldr r0, REG_TC_EMIFS_CS2_CONFIG
 227         str r1, [r0] /* Chip Select 2 */
 228         ldr r1, VAL_TC_EMIFS_CS3_CONFIG
 229         ldr r0, REG_TC_EMIFS_CS3_CONFIG
 230         str r1, [r0] /* Chip Select 3 */
 231
 232         /* back to arch calling code */
 233         mov     pc, lr
 234
 235 /* the literal pools origin */
 236         .ltorg
 237
 238 /* OMAP configuration registers */
 239 REG_FUNC_MUX_CTRL_0:            /* 32 bits */
 240         .word 0xfffe1000
 241 REG_FUNC_MUX_CTRL_1:            /* 32 bits */
 242         .word 0xfffe1004
 243 REG_FUNC_MUX_CTRL_2:            /* 32 bits */
 244         .word 0xfffe1008
 245 REG_COMP_MODE_CTRL_0:           /* 32 bits */
 246         .word 0xfffe100c
 247 REG_FUNC_MUX_CTRL_3:            /* 32 bits */
 248         .word 0xfffe1010
 249 REG_FUNC_MUX_CTRL_4:            /* 32 bits */
 250         .word 0xfffe1014
 251 REG_FUNC_MUX_CTRL_5:            /* 32 bits */
 252         .word 0xfffe1018
 253 REG_FUNC_MUX_CTRL_6:            /* 32 bits */
 254         .word 0xfffe101c
 255 REG_FUNC_MUX_CTRL_7:            /* 32 bits */
 256         .word 0xfffe1020
 257 REG_FUNC_MUX_CTRL_8:            /* 32 bits */
 258         .word 0xfffe1024
 259 REG_FUNC_MUX_CTRL_9:            /* 32 bits */
 260         .word 0xfffe1028
 261 REG_FUNC_MUX_CTRL_A:            /* 32 bits */
 262         .word 0xfffe102C
 263 REG_FUNC_MUX_CTRL_B:            /* 32 bits */
 264         .word 0xfffe1030
 265 REG_FUNC_MUX_CTRL_C:            /* 32 bits */
 266         .word 0xfffe1034
 267 REG_FUNC_MUX_CTRL_D:            /* 32 bits */
 268         .word 0xfffe1038
 269 REG_PULL_DWN_CTRL_0:            /* 32 bits */
 270         .word 0xfffe1040
 271 REG_PULL_DWN_CTRL_1:            /* 32 bits */
 272         .word 0xfffe1044
 273 REG_PULL_DWN_CTRL_2:            /* 32 bits */
 274         .word 0xfffe1048
 275 REG_PULL_DWN_CTRL_3:            /* 32 bits */
 276         .word 0xfffe104c
 277 REG_VOLTAGE_CTRL_0:             /* 32 bits */
 278         .word 0xfffe1060
 279 REG_TEST_DBG_CTRL_0:            /* 32 bits */
 280         .word 0xfffe1070
 281 REG_MOD_CONF_CTRL_0:            /* 32 bits */
 282         .word 0xfffe1080
 283 REG_TC_IMIF_PRIO:               /* 32 bits */
 284         .word 0xfffecc00
 285 REG_TC_EMIFS_PRIO:              /* 32 bits */
 286         .word 0xfffecc04
 287 REG_TC_EMIFF_PRIO:              /* 32 bits */
 288         .word 0xfffecc08
 289 REG_TC_EMIFS_CONFIG:            /* 32 bits */
 290         .word 0xfffecc0c
 291 REG_TC_EMIFS_CS0_CONFIG:        /* 32 bits */
 292         .word 0xfffecc10
 293 REG_TC_EMIFS_CS1_CONFIG:        /* 32 bits */
 294         .word 0xfffecc14
 295 REG_TC_EMIFS_CS2_CONFIG:        /* 32 bits */
 296         .word 0xfffecc18
 297 REG_TC_EMIFS_CS3_CONFIG:        /* 32 bits */
 298         .word 0xfffecc1c
 299 REG_TC_EMIFF_SDRAM_CONFIG:      /* 32 bits */
 300         .word 0xfffecc20
 301 REG_TC_EMIFF_MRS:               /* 32 bits */
 302         .word 0xfffecc24
 303 /* MPU clock/reset/power mode control registers */
 304 REG_ARM_CKCTL:                  /* 16 bits */
 305         .word 0xfffece00
 306 REG_ARM_IDLECT2:                /* 16 bits */
 307         .word 0xfffece08
 308 REG_ARM_RSTCT2:                 /* 16 bits */
 309         .word 0xfffece14
 310 REG_ARM_SYSST:                  /* 16 bits */
 311         .word 0xfffece18
 312 /* DPLL control registers */
 313 REG_DPLL1_CTL:                  /* 16 bits */
 314         .word 0xfffecf00
 315 /* identification code register */
 316 REG_IDCODE:                     /* 32 bits */
 317         .word 0xfffed404
 318
 319 /* SX1 specific */
 320 _GPIO_PIN_CONTROL_REG:
 321         .word GPIO_PIN_CONTROL_REG
 322 _GPIO_DIR_CONTROL_REG:
 323         .word GPIO_DIR_CONTROL_REG
 324 _GPIO_DATA_OUTPUT_REG:
 325         .word GPIO_DATA_OUTPUT_REG
 326
 327 VAL_COMP_MODE_CTRL_0:
 328         .word 0x0000eaef
 329 VAL_FUNC_MUX_CTRL_4:
 330         .word 0x00000000
 331 VAL_FUNC_MUX_CTRL_5:
 332         .word 0x00000000
 333 VAL_FUNC_MUX_CTRL_6:
 334         .word 0x00000001
 335 VAL_FUNC_MUX_CTRL_7:
 336         .word 0x00001000
 337 VAL_FUNC_MUX_CTRL_8:
 338         .word 0x00001240       /*[Knoller]  Value of Symbian Image Wing B2*/
 339 VAL_FUNC_MUX_CTRL_9:
 340         .word 0x00201008
 341 VAL_FUNC_MUX_CTRL_A:
 342         .word 0x00001000
 343 VAL_FUNC_MUX_CTRL_B:
 344         .word 0x00000000
 345 VAL_FUNC_MUX_CTRL_C:
 346         .word 0x09008001       /*[Knoller]  Value of Symbian Image Wing B2*/
 347 VAL_FUNC_MUX_CTRL_D:
 348         .word 0x00000000
 349 VAL_PULL_DWN_CTRL_0:
 350         .word 0xfffeffff
 351 VAL_PULL_DWN_CTRL_1:
 352         .word 0xd1ffffec
 353 VAL_PULL_DWN_CTRL_2:
 354         .word 0xffa80c5b
 355 VAL_PULL_DWN_CTRL_3:
 356         .word 0xffffc0fe
 357 VAL_VOLTAGE_CTRL_0:
 358         .word 0x00000007
 359 VAL_TEST_DBG_CTRL_0:
 360         /* The OMAP5910 TRM says this register must be 0, but HelenConfRegs
 361          * says to write a 7.  Don't know what the right thing is to do, so
 362          * I'm leaving it at 7 since that's what was already here.
 363          */
 364         .word 0x00000007
 365 VAL_MOD_CONF_CTRL_0:
 366         .word 0x0da20000       /*[Knoller]  Value of Symbian Image Wing B2*/
 367
 368 VAL_ARM_CKCTL:
 369         .word 0x010D
 370
 371 VAL_DPLL1_CTL:
 372         .word 0x3A33   /*[Hertle] Value of Symbian Image*/
 373
 374 VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
 375         .word 0x00001149
 376
 377 VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
 378         .word 0x00004158
 379
 380 VAL_TC_EMIFS_CS0_CONFIG:
 381         .word 0x00213090       /*[Knoller]  Value of Symbian Image Wing B2*/
 382
 383 VAL_TC_EMIFS_CS1_CONFIG:
 384         .word 0x00215070       /*[Knoller]  Value of Symbian Image Wing B2*/
 385
 386 VAL_TC_EMIFS_CS2_CONFIG:
 387         .word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
 388
 389 VAL_TC_EMIFS_CS3_CONFIG:
 390         .word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
 391
 392 VAL_TC_EMIFF_SDRAM_CONFIG:
 393         .word 0x0105f0b4       /*[Knoller]  Value of Symbian Image Wing B2*/
 394
 395
 396 VAL_TC_EMIFF_MRS:
 397         .word 0x00000027       /*[Knoller]  Value of Symbian Image Wing B2*/