board/sysam/amcore/amcore.c

   1 /*
   2  * Board functions for Sysam AMCORE (MCF5307 based) board
   3  *
   4  * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  *
   8  * This file copies memory testdram() from sandburst/common/sb_common.c
   9  */
  10
  11 #include <common.h>
  12 #include <asm/immap.h>
  13 #include <asm/io.h>
  14 #include <dm.h>
  15 #include <dm/platform_data/serial_coldfire.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 void init_lcd(void)
  20 {
  21         /* setup for possible K0108 lcd connected on the parallel port */
  22         sim_t *sim = (sim_t *)(MMAP_SIM);
  23
  24         out_be16(&sim->par, 0x300);
  25
  26         gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
  27
  28         out_be16(&gpio->paddr, 0xfcff);
  29         out_be16(&gpio->padat, 0x0c00);
  30 }
  31
  32 int checkboard(void)
  33 {
  34         puts("Board: ");
  35         puts("AMCORE v.001(alpha)\n");
  36
  37         init_lcd();
  38
  39         return 0;
  40 }
  41
  42 /*
  43  * in initdram we are here executing from flash
  44  * case 1:
  45  * is with no ACR/flash cache enabled
  46  * nop = 40ns (scope measured)
  47  */
  48 void fudelay(int usec)
  49 {
  50         while (usec--)
  51                 asm volatile ("nop");
  52 }
  53
  54 int initdram(void)
  55 {
  56         u32 dramsize, RC;
  57
  58         sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
  59
  60         /*
  61          * SDRAM  MT48LC4M32B2 details
  62          * Memory block 0: 16 MB of SDRAM at address $00000000
  63          * Port size: 32-bit port
  64          *
  65          * Memory block 0 wired as follows:
  66          * CPU   : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
  67          * SDRAM :  A0  A1  A2  A3  A4  A5  A6 A7  A8  A9 A10 A11 BA0 BA1
  68          *
  69          * Ensure that there is a delay of at least 100 microseconds from
  70          * processor reset to the following code so that the SDRAM is ready
  71          * for commands.
  72          */
  73         fudelay(100);
  74
  75         /*
  76          * DCR
  77          * set proper  RC as per specification
  78          */
  79         RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
  80         RC = (RC * 15) >> 4;
  81
  82         /* 0x8000 is the faster option */
  83         out_be16(&dc->dcr, 0x8200 | RC);
  84
  85         /*
  86          * DACR0, page mode continuous, CMD on A20 0x0300
  87          */
  88         out_be32(&dc->dacr0, 0x00003304);
  89
  90         dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
  91         out_be32(&dc->dmr0,  dramsize|1);
  92
  93         /* issue a PRECHARGE ALL */
  94         out_be32(&dc->dacr0, 0x0000330c);
  95         out_be32((u32 *)0x00000004, 0xbeaddeed);
  96         /* issue AUTOREFRESH */
  97         out_be32(&dc->dacr0, 0x0000b304);
  98         /* let refresh occur */
  99         fudelay(1);
 100
 101         out_be32(&dc->dacr0, 0x0000b344);
 102         out_be32((u32 *)0x00000c00, 0xbeaddeed);
 103
 104         gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
 105                                     CONFIG_SYS_SDRAM_SIZE);
 106
 107         return 0;
 108 }
 109
 110 static struct coldfire_serial_platdata mcf5307_serial_plat = {
 111         .base = CONFIG_SYS_UART_BASE,
 112         .port = 0,
 113         .baudrate = CONFIG_BAUDRATE,
 114 };
 115
 116 U_BOOT_DEVICE(coldfire_serial) = {
 117         .name = "serial_coldfire",
 118         .platdata = &mcf5307_serial_plat,
 119 };