board/t3corp/t3corp.c

   1 /*
   2  * (C) Copyright 2010
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/ppc440.h>
  10 #include <libfdt.h>
  11 #include <fdt_support.h>
  12 #include <i2c.h>
  13 #include <mtd/cfi_flash.h>
  14 #include <asm/processor.h>
  15 #include <asm/io.h>
  16 #include <asm/mmu.h>
  17 #include <asm/4xx_pcie.h>
  18 #include <asm/ppc4xx-gpio.h>
  19
  20 int board_early_init_f(void)
  21 {
  22         /*
  23          * Setup the interrupt controller polarities, triggers, etc.
  24          */
  25         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  26         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  27         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
  28         mtdcr(UIC0PR, 0xffffffff);      /* per ref-board manual */
  29         mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
  30         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
  31         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  32
  33         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  34         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  35         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  36         mtdcr(UIC1PR, 0x7fffffff);      /* per ref-board manual */
  37         mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
  38         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
  39         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  40
  41         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  42         mtdcr(UIC2ER, 0x00000000);      /* disable all */
  43         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
  44         mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
  45         mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
  46         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
  47         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  48
  49         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
  50         mtdcr(UIC3ER, 0x00000000);      /* disable all */
  51         mtdcr(UIC3CR, 0x00000000);      /* all non-critical */
  52         mtdcr(UIC3PR, 0xffffffff);      /* per ref-board manual */
  53         mtdcr(UIC3TR, 0x00000000);      /* per ref-board manual */
  54         mtdcr(UIC3VR, 0x00000000);      /* int31 highest, base=0x000 */
  55         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
  56
  57         /*
  58          * Configure PFC (Pin Function Control) registers
  59          * enable GPIO 49-63
  60          * UART0: 4 pins
  61          */
  62         mtsdr(SDR0_PFC0, 0x00007fff);
  63         mtsdr(SDR0_PFC1, 0x00040000);
  64
  65         /* Enable PCI host functionality in SDR0_PCI0 */
  66         mtsdr(SDR0_PCI0, 0xe0000000);
  67
  68         mtsdr(SDR0_SRST1, 0);   /* Pull AHB out of reset default=1 */
  69
  70         /* Setup PLB4-AHB bridge based on the system address map */
  71         mtdcr(AHB_TOP, 0x8000004B);
  72         mtdcr(AHB_BOT, 0x8000004B);
  73
  74         return 0;
  75 }
  76
  77 int checkboard(void)
  78 {
  79         char buf[64];
  80         int i = getenv_f("serial#", buf, sizeof(buf));
  81
  82         printf("Board: T3CORP");
  83
  84         if (i > 0) {
  85                 puts(", serial# ");
  86                 puts(buf);
  87         }
  88         putc('\n');
  89
  90         return 0;
  91 }
  92
  93 int board_early_init_r(void)
  94 {
  95         /*
  96          * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
  97          * boot EBC mapping only supports a maximum of 16MBytes
  98          * (4.ff00.0000 - 4.ffff.ffff).
  99          * To solve this problem, the flash has to get remapped to another
 100          * EBC address which accepts bigger regions:
 101          *
 102          * 0xfn00.0000 -> 4.cn00.0000
 103          */
 104
 105         /* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */
 106         mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB |
 107               EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 108
 109         /* Remove TLB entry of boot EBC mapping */
 110         remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
 111
 112         /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
 113         program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
 114                     CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
 115
 116         /*
 117          * Now accessing of the whole 64Mbytes of NOR flash at virtual address
 118          * 0xfc00.0000 is possible
 119          */
 120
 121         /*
 122          * Clear potential errors resulting from auto-calibration.
 123          * If not done, then we could get an interrupt later on when
 124          * exceptions are enabled.
 125          */
 126         set_mcsr(get_mcsr());
 127
 128         return 0;
 129 }
 130
 131 int misc_init_r(void)
 132 {
 133         u32 sdr0_srst1 = 0;
 134         u32 eth_cfg;
 135
 136         /*
 137          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 138          * This is board specific, so let's do it here.
 139          */
 140         mfsdr(SDR0_ETH_CFG, eth_cfg);
 141         /* disable SGMII mode */
 142         eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
 143                      SDR0_ETH_CFG_SGMII1_ENABLE |
 144                      SDR0_ETH_CFG_SGMII0_ENABLE);
 145         /* Set the for 2 RGMII mode */
 146         /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 147         eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
 148         eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 149         mtsdr(SDR0_ETH_CFG, eth_cfg);
 150
 151         /*
 152          * The AHB Bridge core is held in reset after power-on or reset
 153          * so enable it now
 154          */
 155         mfsdr(SDR0_SRST1, sdr0_srst1);
 156         sdr0_srst1 &= ~SDR0_SRST1_AHB;
 157         mtsdr(SDR0_SRST1, sdr0_srst1);
 158
 159         return 0;
 160 }
 161
 162 int board_pcie_last(void)
 163 {
 164         /*
 165          * Only PCIe0 for now, PCIe1 hangs on this board
 166          */
 167         return 0;
 168 }
 169
 170 /*
 171  * Board specific WRDTR and CLKTR values used by the auto-
 172  * calibration code (4xx_ibm_ddr2_autocalib.c).
 173  */
 174 static struct sdram_timing board_scan_options[] = {
 175         {1, 2},
 176         {-1, -1}
 177 };
 178
 179 struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
 180 {
 181         return board_scan_options;
 182 }
 183
 184 /*
 185  * Accessor functions replacing the "weak" functions in
 186  * drivers/mtd/cfi_flash.c
 187  *
 188  * The NOR flash devices "behind" the FPGA's (Xilinx DS617)
 189  * can only be read correctly in 16bit mode. We need to emulate
 190  * 8bit and 32bit reads here in the board specific code.
 191  */
 192 u8 flash_read8(void *addr)
 193 {
 194         u16 val = __raw_readw((void *)((u32)addr & ~1));
 195
 196         if ((u32)addr & 1)
 197                 return val;
 198
 199         return val >> 8;
 200 }
 201
 202 u32 flash_read32(void *addr)
 203 {
 204         return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
 205 }
 206
 207 void flash_cmd_reset(flash_info_t *info)
 208 {
 209         /*
 210          * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
 211          * needs the Spansion type reset commands. The other flash chip
 212          * is located behind a FPGA (Xilinx DS617) and needs the Intel type
 213          * reset command.
 214          */
 215         if (info->start[0] == CONFIG_SYS_FLASH_BASE)
 216                 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
 217         else
 218                 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
 219 }