3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <fdt_support.h>
26 #include <asm/processor.h>
29 #include <asm/4xx_pcie.h>
32 int board_early_init_f(void)
35 * Setup the interrupt controller polarities, triggers, etc.
37 mtdcr(UIC0SR
, 0xffffffff); /* clear all */
38 mtdcr(UIC0ER
, 0x00000000); /* disable all */
39 mtdcr(UIC0CR
, 0x00000005); /* ATI & UIC1 crit are critical */
40 mtdcr(UIC0PR
, 0xffffffff); /* per ref-board manual */
41 mtdcr(UIC0TR
, 0x00000000); /* per ref-board manual */
42 mtdcr(UIC0VR
, 0x00000000); /* int31 highest, base=0x000 */
43 mtdcr(UIC0SR
, 0xffffffff); /* clear all */
45 mtdcr(UIC1SR
, 0xffffffff); /* clear all */
46 mtdcr(UIC1ER
, 0x00000000); /* disable all */
47 mtdcr(UIC1CR
, 0x00000000); /* all non-critical */
48 mtdcr(UIC1PR
, 0x7fffffff); /* per ref-board manual */
49 mtdcr(UIC1TR
, 0x00000000); /* per ref-board manual */
50 mtdcr(UIC1VR
, 0x00000000); /* int31 highest, base=0x000 */
51 mtdcr(UIC1SR
, 0xffffffff); /* clear all */
53 mtdcr(UIC2SR
, 0xffffffff); /* clear all */
54 mtdcr(UIC2ER
, 0x00000000); /* disable all */
55 mtdcr(UIC2CR
, 0x00000000); /* all non-critical */
56 mtdcr(UIC2PR
, 0xffffffff); /* per ref-board manual */
57 mtdcr(UIC2TR
, 0x00000000); /* per ref-board manual */
58 mtdcr(UIC2VR
, 0x00000000); /* int31 highest, base=0x000 */
59 mtdcr(UIC2SR
, 0xffffffff); /* clear all */
61 mtdcr(UIC3SR
, 0xffffffff); /* clear all */
62 mtdcr(UIC3ER
, 0x00000000); /* disable all */
63 mtdcr(UIC3CR
, 0x00000000); /* all non-critical */
64 mtdcr(UIC3PR
, 0xffffffff); /* per ref-board manual */
65 mtdcr(UIC3TR
, 0x00000000); /* per ref-board manual */
66 mtdcr(UIC3VR
, 0x00000000); /* int31 highest, base=0x000 */
67 mtdcr(UIC3SR
, 0xffffffff); /* clear all */
70 * Configure PFC (Pin Function Control) registers
74 mtsdr(SDR0_PFC0
, 0x00007fff);
75 mtsdr(SDR0_PFC1
, 0x00040000);
77 /* Enable PCI host functionality in SDR0_PCI0 */
78 mtsdr(SDR0_PCI0
, 0xe0000000);
80 mtsdr(SDR0_SRST1
, 0); /* Pull AHB out of reset default=1 */
82 /* Setup PLB4-AHB bridge based on the system address map */
83 mtdcr(AHB_TOP
, 0x8000004B);
84 mtdcr(AHB_BOT
, 0x8000004B);
91 char *s
= getenv("serial#");
93 printf("Board: T3CORP");
104 int board_early_init_r(void)
107 * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
108 * boot EBC mapping only supports a maximum of 16MBytes
109 * (4.ff00.0000 - 4.ffff.ffff).
110 * To solve this problem, the flash has to get remapped to another
111 * EBC address which accepts bigger regions:
113 * 0xfn00.0000 -> 4.cn00.0000
116 /* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */
117 mtebc(PB0CR
, CONFIG_SYS_FLASH_BASE_PHYS_L
| EBC_BXCR_BS_64MB
|
118 EBC_BXCR_BU_RW
| EBC_BXCR_BW_16BIT
);
120 /* Remove TLB entry of boot EBC mapping */
121 remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR
, 16 << 20);
123 /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
124 program_tlb(CONFIG_SYS_FLASH_BASE_PHYS
, CONFIG_SYS_FLASH_BASE
,
125 CONFIG_SYS_FLASH_SIZE
, TLB_WORD2_I_ENABLE
);
128 * Now accessing of the whole 64Mbytes of NOR flash at virtual address
129 * 0xfc00.0000 is possible
133 * Clear potential errors resulting from auto-calibration.
134 * If not done, then we could get an interrupt later on when
135 * exceptions are enabled.
137 set_mcsr(get_mcsr());
142 int misc_init_r(void)
148 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
149 * This is board specific, so let's do it here.
151 mfsdr(SDR0_ETH_CFG
, eth_cfg
);
152 /* disable SGMII mode */
153 eth_cfg
&= ~(SDR0_ETH_CFG_SGMII2_ENABLE
|
154 SDR0_ETH_CFG_SGMII1_ENABLE
|
155 SDR0_ETH_CFG_SGMII0_ENABLE
);
156 /* Set the for 2 RGMII mode */
157 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
158 eth_cfg
&= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL
;
159 eth_cfg
&= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL
;
160 mtsdr(SDR0_ETH_CFG
, eth_cfg
);
163 * The AHB Bridge core is held in reset after power-on or reset
166 mfsdr(SDR0_SRST1
, sdr0_srst1
);
167 sdr0_srst1
&= ~SDR0_SRST1_AHB
;
168 mtsdr(SDR0_SRST1
, sdr0_srst1
);
173 int board_pcie_last(void)
176 * Only PCIe0 for now, PCIe1 hangs on this board
182 * Board specific WRDTR and CLKTR values used by the auto-
183 * calibration code (4xx_ibm_ddr2_autocalib.c).
185 static struct sdram_timing board_scan_options
[] = {
190 struct sdram_timing
*ddr_scan_option(struct sdram_timing
*default_val
)
192 return board_scan_options
;