board/technexion/pico-imx6ul/pico-imx6ul.c

   1 /*
   2  * Copyright (C) 2015 Technexion Ltd.
   3  *
   4  * Author: Richard Hu <richard.hu@technexion.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/mxc_i2c.h>
  18 #include <asm/io.h>
  19 #include <common.h>
  20 #include <miiphy.h>
  21 #include <netdev.h>
  22 #include <fsl_esdhc.h>
  23 #include <i2c.h>
  24 #include <linux/sizes.h>
  25 #include <usb.h>
  26 #include <power/pmic.h>
  27 #include <power/pfuze3000_pmic.h>
  28 #include "../../freescale/common/pfuze.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  33         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  34         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  37         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  38         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  41         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  42         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  43         PAD_CTL_ODE)
  44
  45 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  46         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  47         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  50         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  51
  52 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  53         PAD_CTL_SPEED_HIGH   |                                   \
  54         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  55
  56 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  57
  58 #define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
  59
  60 #ifdef CONFIG_SYS_I2C_MXC
  61 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  62 /* I2C2 for PMIC */
  63 struct i2c_pads_info i2c_pad_info1 = {
  64         .scl = {
  65                 .i2c_mode =  MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
  66                 .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
  67                 .gp = IMX_GPIO_NR(1, 2),
  68         },
  69         .sda = {
  70                 .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
  71                 .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
  72                 .gp = IMX_GPIO_NR(1, 3),
  73         },
  74 };
  75 #endif
  76
  77 static iomux_v3_cfg_t const fec_pads[] = {
  78         MX6_PAD_ENET1_TX_EN__ENET2_MDC          | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  79         MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO      | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  80         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2    | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  83         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_UART4_TX_DATA__GPIO1_IO28       | MUX_PAD_CTRL(NO_PAD_CTRL),
  89 };
  90
  91 static void setup_iomux_fec(void)
  92 {
  93         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  94 }
  95
  96 int board_eth_init(bd_t *bis)
  97 {
  98         setup_iomux_fec();
  99
 100         gpio_direction_output(RMII_PHY_RESET, 0);
 101         /*
 102          * According to KSZ8081MNX-RNB manual:
 103          * For warm reset, the reset (RST#) pin should be asserted low for a
 104          * minimum of 500μs.  The strap-in pin values are read and updated
 105          * at the de-assertion of reset.
 106          */
 107         udelay(500);
 108
 109         gpio_direction_output(RMII_PHY_RESET, 1);
 110         /*
 111          * According to KSZ8081MNX-RNB manual:
 112          * After the de-assertion of reset, wait a minimum of 100μs before
 113          * starting programming on the MIIM (MDC/MDIO) interface.
 114          */
 115         udelay(100);
 116
 117         return fecmxc_initialize(bis);
 118 }
 119
 120 static int setup_fec(void)
 121 {
 122         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 123         int ret;
 124
 125         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 126                         IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 127
 128         ret = enable_fec_anatop_clock(1, ENET_50MHZ);
 129         if (ret)
 130                 return ret;
 131
 132         enable_enet_clk(1);
 133
 134         return 0;
 135 }
 136
 137 int board_phy_config(struct phy_device *phydev)
 138 {
 139         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
 140
 141         if (phydev->drv->config)
 142                 phydev->drv->config(phydev);
 143
 144         return 0;
 145 }
 146
 147 int dram_init(void)
 148 {
 149         gd->ram_size = imx_ddr_size();
 150
 151         return 0;
 152 }
 153
 154 static iomux_v3_cfg_t const uart6_pads[] = {
 155         MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 156         MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 157 };
 158
 159 static iomux_v3_cfg_t const usdhc1_pads[] = {
 160         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 161         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169         MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 170 };
 171
 172 #define USB_OTHERREGS_OFFSET    0x800
 173 #define UCTRL_PWR_POL           (1 << 9)
 174
 175 static iomux_v3_cfg_t const usb_otg_pad[] = {
 176         MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
 177 };
 178
 179 static void setup_iomux_uart(void)
 180 {
 181         imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
 182 }
 183
 184 static void setup_usb(void)
 185 {
 186         imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
 187 }
 188
 189 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 190         {USDHC1_BASE_ADDR},
 191 };
 192
 193 int board_mmc_getcd(struct mmc *mmc)
 194 {
 195         return 1;
 196 }
 197
 198 int board_mmc_init(bd_t *bis)
 199 {
 200         imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 201         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 202         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 203 }
 204
 205 int board_early_init_f(void)
 206 {
 207         setup_iomux_uart();
 208
 209         return 0;
 210 }
 211
 212 #ifdef CONFIG_POWER
 213 #define I2C_PMIC       0
 214 static struct pmic *pfuze;
 215 int power_init_board(void)
 216 {
 217         int ret;
 218         unsigned int reg, rev_id;
 219
 220         ret = power_pfuze3000_init(I2C_PMIC);
 221         if (ret)
 222                 return ret;
 223
 224         pfuze = pmic_get("PFUZE3000");
 225         ret = pmic_probe(pfuze);
 226         if (ret)
 227                 return ret;
 228
 229         pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
 230         pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
 231         printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
 232
 233         /* disable Low Power Mode during standby mode */
 234         pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
 235
 236         /* SW1B step ramp up time from 2us to 4us/25mV */
 237         pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40);
 238
 239         /* SW1B mode to APS/PFM */
 240         pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, 0xc);
 241
 242         /* SW1B standby voltage set to 0.975V */
 243         pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, 0xb);
 244
 245         return 0;
 246 }
 247 #endif
 248
 249 int board_usb_phy_mode(int port)
 250 {
 251         if (port == 1)
 252                 return USB_INIT_HOST;
 253         else
 254                 return USB_INIT_DEVICE;
 255 }
 256
 257 int board_ehci_hcd_init(int port)
 258 {
 259         u32 *usbnc_usb_ctrl;
 260
 261         if (port > 1)
 262                 return -EINVAL;
 263
 264         usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
 265                                  port * 4);
 266
 267         /* Set Power polarity */
 268         setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 269
 270         return 0;
 271 }
 272
 273 int board_init(void)
 274 {
 275         /* Address of boot parameters */
 276         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 277
 278         #ifdef CONFIG_SYS_I2C_MXC
 279                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 280         #endif
 281
 282         setup_fec();
 283         setup_usb();
 284
 285         return 0;
 286 }
 287
 288 int checkboard(void)
 289 {
 290         puts("Board: PICO-IMX6UL-EMMC\n");
 291
 292         return 0;
 293 }