3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * Copyright (C) 2009 TechNexion Ltd.
7 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/mem.h>
17 #include <asm/arch/mux.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/omap_gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/dss.h>
22 #include <asm/arch/clock.h>
26 #ifdef CONFIG_USB_EHCI_HCD
28 #include <asm/ehci-omap.h>
30 #include "mt_ventoux.h"
32 DECLARE_GLOBAL_DATA_PTR
;
40 #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
51 #define LCD_PON_PIN 139
53 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
57 } panel_resolution
[] = {
62 static struct panel_config lcd_cfg
[] = {
64 .timing_h
= PANEL_TIMING_H(40, 5, 2),
65 .timing_v
= PANEL_TIMING_V(8, 8, 2),
66 .pol_freq
= 0x00003000, /* Pol Freq */
67 .divisor
= 0x00010033, /* 9 Mhz Pixel Clock */
68 .panel_type
= 0x01, /* TFT */
69 .data_lines
= 0x03, /* 24 Bit RGB */
70 .load_mode
= 0x02, /* Frame Mode */
72 .gfx_format
= GFXFORMAT_RGB24_UNPACKED
,
75 .timing_h
= PANEL_TIMING_H(20, 192, 4),
76 .timing_v
= PANEL_TIMING_V(2, 20, 10),
77 .pol_freq
= 0x00004000, /* Pol Freq */
78 .divisor
= 0x0001000E, /* 36Mhz Pixel Clock */
79 .panel_type
= 0x01, /* TFT */
80 .data_lines
= 0x03, /* 24 Bit RGB */
81 .load_mode
= 0x02, /* Frame Mode */
83 .gfx_format
= GFXFORMAT_RGB24_UNPACKED
,
88 /* Timing definitions for FPGA */
89 static const u32 gpmc_fpga
[] = {
98 #ifdef CONFIG_USB_EHCI_HCD
99 static struct omap_usbhs_board_data usbhs_bdata
= {
100 .port_mode
[0] = OMAP_EHCI_PORT_MODE_PHY
,
101 .port_mode
[1] = OMAP_EHCI_PORT_MODE_PHY
,
102 .port_mode
[2] = OMAP_USBHS_PORT_MODE_UNUSED
,
105 int ehci_hcd_init(int index
, enum usb_init_type init
,
106 struct ehci_hccr
**hccr
, struct ehci_hcor
**hcor
)
108 return omap_ehci_hcd_init(index
, &usbhs_bdata
, hccr
, hcor
);
111 int ehci_hcd_stop(int index
)
113 return omap_ehci_hcd_stop();
118 static inline void fpga_reset(int nassert
)
120 gpio_set_value(FPGA_RESET
, !nassert
);
123 int fpga_pgm_fn(int nassert
, int nflush
, int cookie
)
125 debug("%s:%d: FPGA PROGRAM ", __func__
, __LINE__
);
127 gpio_set_value(FPGA_PROG
, !nassert
);
132 int fpga_init_fn(int cookie
)
134 return !gpio_get_value(FPGA_INIT
);
137 int fpga_done_fn(int cookie
)
139 return gpio_get_value(FPGA_DONE
);
142 int fpga_pre_config_fn(int cookie
)
144 debug("%s:%d: FPGA pre-configuration\n", __func__
, __LINE__
);
146 /* Setting GPIOs for programming Mode */
147 gpio_request(FPGA_RESET
, "FPGA_RESET");
148 gpio_direction_output(FPGA_RESET
, 1);
149 gpio_request(FPGA_PROG
, "FPGA_PROG");
150 gpio_direction_output(FPGA_PROG
, 1);
151 gpio_request(FPGA_CCLK
, "FPGA_CCLK");
152 gpio_direction_output(FPGA_CCLK
, 1);
153 gpio_request(FPGA_DIN
, "FPGA_DIN");
154 gpio_direction_output(FPGA_DIN
, 0);
155 gpio_request(FPGA_INIT
, "FPGA_INIT");
156 gpio_direction_input(FPGA_INIT
);
157 gpio_request(FPGA_DONE
, "FPGA_DONE");
158 gpio_direction_input(FPGA_DONE
);
160 /* Be sure that signal are deasserted */
161 gpio_set_value(FPGA_RESET
, 1);
162 gpio_set_value(FPGA_PROG
, 1);
167 int fpga_post_config_fn(int cookie
)
169 debug("%s:%d: FPGA post-configuration\n", __func__
, __LINE__
);
178 /* Write program to the FPGA */
179 int fpga_wr_fn(int nassert_write
, int flush
, int cookie
)
181 gpio_set_value(FPGA_DIN
, nassert_write
);
183 return nassert_write
;
186 int fpga_clk_fn(int assert_clk
, int flush
, int cookie
)
188 gpio_set_value(FPGA_CCLK
, assert_clk
);
193 xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns
= {
203 xilinx_desc fpga
= XILINX_XC6SLX4_DESC(slave_serial
,
204 (void *)&mt_ventoux_fpga_fns
, 0);
206 /* Initialize the FPGA */
207 static void mt_ventoux_init_fpga(void)
209 fpga_pre_config_fn(0);
211 /* Setting CS1 for FPGA access */
212 enable_gpmc_cs_config(gpmc_fpga
, &gpmc_cfg
->cs
[1],
213 FPGA_BASE_ADDR
, GPMC_SIZE_128M
);
216 fpga_add(fpga_xilinx
, &fpga
);
220 * Routine: board_init
221 * Description: Early hardware init.
225 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
227 /* boot param addr */
228 gd
->bd
->bi_boot_params
= (OMAP34XX_SDRC_CS0
+ 0x100);
230 mt_ventoux_init_fpga();
232 /* GPIO_140: speaker #mute */
233 MUX_VAL(CP(MCBSP3_DX
), (IEN
| PTU
| EN
| M4
))
234 /* GPIO_141: Buzz Hi */
235 MUX_VAL(CP(MCBSP3_DR
), (IEN
| PTU
| EN
| M4
))
237 /* Turning off the buzzer */
238 gpio_request(BUZZER
, "BUZZER_MUTE");
239 gpio_request(SPEAKER
, "SPEAKER");
240 gpio_direction_output(BUZZER
, 0);
241 gpio_direction_output(SPEAKER
, 0);
243 /* Activate USB power */
244 gpio_request(USB1_PWR
, "USB1_PWR");
245 gpio_request(USB2_PWR
, "USB2_PWR");
246 gpio_direction_output(USB1_PWR
, 1);
247 gpio_direction_output(USB2_PWR
, 1);
252 #ifndef CONFIG_SPL_BUILD
253 int misc_init_r(void)
256 struct tam3517_module_info info
;
259 TAM3517_READ_EEPROM(&info
, ret
);
260 omap_die_id_display();
264 eth_addr
= env_get("ethaddr");
266 TAM3517_READ_MAC_FROM_EEPROM(&info
);
268 TAM3517_PRINT_SOM_INFO(&info
);
274 * Routine: set_muxconf_regs
275 * Description: Setting up the configuration Mux registers specific to the
276 * hardware. Many pins need to be moved from protect to primary
279 void set_muxconf_regs(void)
285 * Initializes on-chip ethernet controllers.
286 * to override, implement board_eth_init()
288 int board_eth_init(bd_t
*bis
)
290 davinci_emac_initialize();
294 #if defined(CONFIG_MMC_OMAP_HS) && \
295 !defined(CONFIG_SPL_BUILD)
296 int board_mmc_init(bd_t
*bis
)
298 return omap_mmc_init(0, 0, 0, -1, -1);
302 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
303 int board_video_init(void)
305 struct prcm
*prcm_base
= (struct prcm
*)PRCM_BASE
;
306 struct panel_config
*panel
= &lcd_cfg
[0];
312 fb
= (void *)0x88000000;
314 s
= env_get("panel");
316 index
= simple_strtoul(s
, NULL
, 10);
317 if (index
< ARRAY_SIZE(lcd_cfg
))
318 panel
= &lcd_cfg
[index
];
323 panel
->frame_buffer
= fb
;
324 printf("Panel: %dx%d\n", panel_resolution
[index
].xres
,
325 panel_resolution
[index
].yres
);
326 panel
->lcd_size
= (panel_resolution
[index
].yres
- 1) << 16 |
327 (panel_resolution
[index
].xres
- 1);
329 gpio_request(LCD_PWR
, "LCD Power");
330 gpio_request(LCD_PON_PIN
, "LCD Pon");
331 gpio_direction_output(LCD_PWR
, 0);
332 gpio_direction_output(LCD_PON_PIN
, 1);
335 setbits_le32(&prcm_base
->fclken_dss
, FCK_DSS_ON
);
336 setbits_le32(&prcm_base
->iclken_dss
, ICK_DSS_ON
);
338 omap3_dss_panel_config(panel
);