board/ti/am43xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM43XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <i2c.h>
  13 #include <linux/errno.h>
  14 #include <spl.h>
  15 #include <usb.h>
  16 #include <asm/omap_sec_common.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/mux.h>
  20 #include <asm/arch/ddr_defs.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/emif.h>
  23 #include <asm/omap_common.h>
  24 #include "../common/board_detect.h"
  25 #include "board.h"
  26 #include <power/pmic.h>
  27 #include <power/tps65218.h>
  28 #include <power/tps62362.h>
  29 #include <miiphy.h>
  30 #include <cpsw.h>
  31 #include <linux/usb/gadget.h>
  32 #include <dwc3-uboot.h>
  33 #include <dwc3-omap-uboot.h>
  34 #include <ti-usb-phy-uboot.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  39
  40 /*
  41  * Read header information from EEPROM into global structure.
  42  */
  43 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  44 void do_board_detect(void)
  45 {
  46         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  47                                  CONFIG_EEPROM_CHIP_ADDRESS))
  48                 printf("ti_i2c_eeprom_init failed\n");
  49 }
  50 #endif
  51
  52 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  53
  54 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
  55         {       /* 19.2 MHz */
  56                 {125, 3, 2, -1, -1, -1, -1},    /* OPP 50 */
  57                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  58                 {125, 3, 1, -1, -1, -1, -1},    /* OPP 100 */
  59                 {150, 3, 1, -1, -1, -1, -1},    /* OPP 120 */
  60                 {125, 2, 1, -1, -1, -1, -1},    /* OPP TB */
  61                 {625, 11, 1, -1, -1, -1, -1}    /* OPP NT */
  62         },
  63         {       /* 24 MHz */
  64                 {300, 23, 1, -1, -1, -1, -1},   /* OPP 50 */
  65                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  66                 {600, 23, 1, -1, -1, -1, -1},   /* OPP 100 */
  67                 {720, 23, 1, -1, -1, -1, -1},   /* OPP 120 */
  68                 {800, 23, 1, -1, -1, -1, -1},   /* OPP TB */
  69                 {1000, 23, 1, -1, -1, -1, -1}   /* OPP NT */
  70         },
  71         {       /* 25 MHz */
  72                 {300, 24, 1, -1, -1, -1, -1},   /* OPP 50 */
  73                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  74                 {600, 24, 1, -1, -1, -1, -1},   /* OPP 100 */
  75                 {720, 24, 1, -1, -1, -1, -1},   /* OPP 120 */
  76                 {800, 24, 1, -1, -1, -1, -1},   /* OPP TB */
  77                 {1000, 24, 1, -1, -1, -1, -1}   /* OPP NT */
  78         },
  79         {       /* 26 MHz */
  80                 {300, 25, 1, -1, -1, -1, -1},   /* OPP 50 */
  81                 {-1, -1, -1, -1, -1, -1, -1},   /* OPP RESERVED */
  82                 {600, 25, 1, -1, -1, -1, -1},   /* OPP 100 */
  83                 {720, 25, 1, -1, -1, -1, -1},   /* OPP 120 */
  84                 {800, 25, 1, -1, -1, -1, -1},   /* OPP TB */
  85                 {1000, 25, 1, -1, -1, -1, -1}   /* OPP NT */
  86         },
  87 };
  88
  89 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
  90                 {625, 11, -1, -1, 10, 8, 4},    /* 19.2 MHz */
  91                 {1000, 23, -1, -1, 10, 8, 4},   /* 24 MHz */
  92                 {1000, 24, -1, -1, 10, 8, 4},   /* 25 MHz */
  93                 {1000, 25, -1, -1, 10, 8, 4}    /* 26 MHz */
  94 };
  95
  96 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
  97                 {400, 7, 5, -1, -1, -1, -1},    /* 19.2 MHz */
  98                 {400, 9, 5, -1, -1, -1, -1},    /* 24 MHz */
  99                 {384, 9, 5, -1, -1, -1, -1},    /* 25 MHz */
 100                 {480, 12, 5, -1, -1, -1, -1}    /* 26 MHz */
 101 };
 102
 103 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
 104                 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
 105                 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
 106                 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
 107                 {133, 12, 1, -1, 4, -1, -1}  /* 26 MHz */
 108 };
 109
 110 const struct dpll_params gp_evm_dpll_ddr = {
 111                 50, 2, 1, -1, 2, -1, -1};
 112
 113 static const struct dpll_params idk_dpll_ddr = {
 114         400, 23, 1, -1, 2, -1, -1
 115 };
 116
 117 static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 118         0x00500050,
 119         0x00350035,
 120         0x00350035,
 121         0x00350035,
 122         0x00350035,
 123         0x00350035,
 124         0x00000000,
 125         0x00000000,
 126         0x00000000,
 127         0x00000000,
 128         0x00000000,
 129         0x00000000,
 130         0x00000000,
 131         0x00000000,
 132         0x00000000,
 133         0x00000000,
 134         0x00000000,
 135         0x00000000,
 136         0x40001000,
 137         0x08102040
 138 };
 139
 140 const struct ctrl_ioregs ioregs_lpddr2 = {
 141         .cm0ioctl               = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
 142         .cm1ioctl               = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
 143         .cm2ioctl               = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
 144         .dt0ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 145         .dt1ioctl               = LPDDR2_DATA0_IOCTRL_VALUE,
 146         .dt2ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 147         .dt3ioctrl              = LPDDR2_DATA0_IOCTRL_VALUE,
 148         .emif_sdram_config_ext  = 0x1,
 149 };
 150
 151 const struct emif_regs emif_regs_lpddr2 = {
 152         .sdram_config                   = 0x808012BA,
 153         .ref_ctrl                       = 0x0000040D,
 154         .sdram_tim1                     = 0xEA86B411,
 155         .sdram_tim2                     = 0x103A094A,
 156         .sdram_tim3                     = 0x0F6BA37F,
 157         .read_idle_ctrl                 = 0x00050000,
 158         .zq_config                      = 0x50074BE4,
 159         .temp_alert_config              = 0x0,
 160         .emif_rd_wr_lvl_rmp_win         = 0x0,
 161         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 162         .emif_rd_wr_lvl_ctl             = 0x0,
 163         .emif_ddr_phy_ctlr_1            = 0x0E284006,
 164         .emif_rd_wr_exec_thresh         = 0x80000405,
 165         .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
 166         .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
 167         .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
 168         .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
 169         .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
 170         .emif_prio_class_serv_map       = 0x80000001,
 171         .emif_connect_id_serv_1_map     = 0x80000094,
 172         .emif_connect_id_serv_2_map     = 0x00000000,
 173         .emif_cos_config                        = 0x000FFFFF
 174 };
 175
 176 const struct ctrl_ioregs ioregs_ddr3 = {
 177         .cm0ioctl               = DDR3_ADDRCTRL_IOCTRL_VALUE,
 178         .cm1ioctl               = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
 179         .cm2ioctl               = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
 180         .dt0ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 181         .dt1ioctl               = DDR3_DATA0_IOCTRL_VALUE,
 182         .dt2ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 183         .dt3ioctrl              = DDR3_DATA0_IOCTRL_VALUE,
 184         .emif_sdram_config_ext  = 0xc163,
 185 };
 186
 187 const struct emif_regs ddr3_emif_regs_400Mhz = {
 188         .sdram_config                   = 0x638413B2,
 189         .ref_ctrl                       = 0x00000C30,
 190         .sdram_tim1                     = 0xEAAAD4DB,
 191         .sdram_tim2                     = 0x266B7FDA,
 192         .sdram_tim3                     = 0x107F8678,
 193         .read_idle_ctrl                 = 0x00050000,
 194         .zq_config                      = 0x50074BE4,
 195         .temp_alert_config              = 0x0,
 196         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 197         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 198         .emif_ddr_ext_phy_ctrl_2        = 0x00400040,
 199         .emif_ddr_ext_phy_ctrl_3        = 0x00400040,
 200         .emif_ddr_ext_phy_ctrl_4        = 0x00400040,
 201         .emif_ddr_ext_phy_ctrl_5        = 0x00400040,
 202         .emif_rd_wr_lvl_rmp_win         = 0x0,
 203         .emif_rd_wr_lvl_rmp_ctl         = 0x0,
 204         .emif_rd_wr_lvl_ctl             = 0x0,
 205         .emif_rd_wr_exec_thresh         = 0x80000405,
 206         .emif_prio_class_serv_map       = 0x80000001,
 207         .emif_connect_id_serv_1_map     = 0x80000094,
 208         .emif_connect_id_serv_2_map     = 0x00000000,
 209         .emif_cos_config                = 0x000FFFFF
 210 };
 211
 212 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
 213 const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
 214         .sdram_config                   = 0x638413B2,
 215         .ref_ctrl                       = 0x00000C30,
 216         .sdram_tim1                     = 0xEAAAD4DB,
 217         .sdram_tim2                     = 0x266B7FDA,
 218         .sdram_tim3                     = 0x107F8678,
 219         .read_idle_ctrl                 = 0x00050000,
 220         .zq_config                      = 0x50074BE4,
 221         .temp_alert_config              = 0x0,
 222         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 223         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 224         .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
 225         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 226         .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
 227         .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
 228         .emif_rd_wr_exec_thresh         = 0x80000405,
 229         .emif_prio_class_serv_map       = 0x80000001,
 230         .emif_connect_id_serv_1_map     = 0x80000094,
 231         .emif_connect_id_serv_2_map     = 0x00000000,
 232         .emif_cos_config                = 0x000FFFFF
 233 };
 234
 235 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
 236 const struct emif_regs ddr3_emif_regs_400Mhz_production = {
 237         .sdram_config                   = 0x638413B2,
 238         .ref_ctrl                       = 0x00000C30,
 239         .sdram_tim1                     = 0xEAAAD4DB,
 240         .sdram_tim2                     = 0x266B7FDA,
 241         .sdram_tim3                     = 0x107F8678,
 242         .read_idle_ctrl                 = 0x00050000,
 243         .zq_config                      = 0x50074BE4,
 244         .temp_alert_config              = 0x0,
 245         .emif_ddr_phy_ctlr_1            = 0x0E004008,
 246         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 247         .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
 248         .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
 249         .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
 250         .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
 251         .emif_rd_wr_exec_thresh         = 0x80000405,
 252         .emif_prio_class_serv_map       = 0x80000001,
 253         .emif_connect_id_serv_1_map     = 0x80000094,
 254         .emif_connect_id_serv_2_map     = 0x00000000,
 255         .emif_cos_config                = 0x000FFFFF
 256 };
 257
 258 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 259         .sdram_config                   = 0x638413b2,
 260         .sdram_config2                  = 0x00000000,
 261         .ref_ctrl                       = 0x00000c30,
 262         .sdram_tim1                     = 0xeaaad4db,
 263         .sdram_tim2                     = 0x266b7fda,
 264         .sdram_tim3                     = 0x107f8678,
 265         .read_idle_ctrl                 = 0x00050000,
 266         .zq_config                      = 0x50074be4,
 267         .temp_alert_config              = 0x0,
 268         .emif_ddr_phy_ctlr_1            = 0x0e084008,
 269         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 270         .emif_ddr_ext_phy_ctrl_2        = 0x89,
 271         .emif_ddr_ext_phy_ctrl_3        = 0x90,
 272         .emif_ddr_ext_phy_ctrl_4        = 0x8e,
 273         .emif_ddr_ext_phy_ctrl_5        = 0x8d,
 274         .emif_rd_wr_lvl_rmp_win         = 0x0,
 275         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 276         .emif_rd_wr_lvl_ctl             = 0x00000000,
 277         .emif_rd_wr_exec_thresh         = 0x80000000,
 278         .emif_prio_class_serv_map       = 0x80000001,
 279         .emif_connect_id_serv_1_map     = 0x80000094,
 280         .emif_connect_id_serv_2_map     = 0x00000000,
 281         .emif_cos_config                = 0x000FFFFF
 282 };
 283
 284 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
 285         .sdram_config                   = 0x61a11b32,
 286         .sdram_config2                  = 0x00000000,
 287         .ref_ctrl                       = 0x00000c30,
 288         .sdram_tim1                     = 0xeaaad4db,
 289         .sdram_tim2                     = 0x266b7fda,
 290         .sdram_tim3                     = 0x107f8678,
 291         .read_idle_ctrl                 = 0x00050000,
 292         .zq_config                      = 0x50074be4,
 293         .temp_alert_config              = 0x00000000,
 294         .emif_ddr_phy_ctlr_1            = 0x00008009,
 295         .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
 296         .emif_ddr_ext_phy_ctrl_2        = 0x00000040,
 297         .emif_ddr_ext_phy_ctrl_3        = 0x0000003e,
 298         .emif_ddr_ext_phy_ctrl_4        = 0x00000051,
 299         .emif_ddr_ext_phy_ctrl_5        = 0x00000051,
 300         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 301         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 302         .emif_rd_wr_lvl_ctl             = 0x00000000,
 303         .emif_rd_wr_exec_thresh         = 0x00000405,
 304         .emif_prio_class_serv_map       = 0x00000000,
 305         .emif_connect_id_serv_1_map     = 0x00000000,
 306         .emif_connect_id_serv_2_map     = 0x00000000,
 307         .emif_cos_config                = 0x00ffffff
 308 };
 309
 310 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 311 {
 312         if (board_is_eposevm()) {
 313                 *regs = ext_phy_ctrl_const_base_lpddr2;
 314                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
 315         }
 316
 317         return;
 318 }
 319
 320 const struct dpll_params *get_dpll_ddr_params(void)
 321 {
 322         int ind = get_sys_clk_index();
 323
 324         if (board_is_eposevm())
 325                 return &epos_evm_dpll_ddr[ind];
 326         else if (board_is_evm() || board_is_sk())
 327                 return &gp_evm_dpll_ddr;
 328         else if (board_is_idk())
 329                 return &idk_dpll_ddr;
 330
 331         printf(" Board '%s' not supported\n", board_ti_get_name());
 332         return NULL;
 333 }
 334
 335
 336 /*
 337  * get_opp_offset:
 338  * Returns the index for safest OPP of the device to boot.
 339  * max_off:     Index of the MAX OPP in DEV ATTRIBUTE register.
 340  * min_off:     Index of the MIN OPP in DEV ATTRIBUTE register.
 341  * This data is read from dev_attribute register which is e-fused.
 342  * A'1' in bit indicates OPP disabled and not available, a '0' indicates
 343  * OPP available. Lowest OPP starts with min_off. So returning the
 344  * bit with rightmost '0'.
 345  */
 346 static int get_opp_offset(int max_off, int min_off)
 347 {
 348         struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
 349         int opp, offset, i;
 350
 351         /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
 352         opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
 353
 354         for (i = max_off; i >= min_off; i--) {
 355                 offset = opp & (1 << i);
 356                 if (!offset)
 357                         return i;
 358         }
 359
 360         return min_off;
 361 }
 362
 363 const struct dpll_params *get_dpll_mpu_params(void)
 364 {
 365         int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
 366         u32 ind = get_sys_clk_index();
 367
 368         return &dpll_mpu[ind][opp];
 369 }
 370
 371 const struct dpll_params *get_dpll_core_params(void)
 372 {
 373         int ind = get_sys_clk_index();
 374
 375         return &dpll_core[ind];
 376 }
 377
 378 const struct dpll_params *get_dpll_per_params(void)
 379 {
 380         int ind = get_sys_clk_index();
 381
 382         return &dpll_per[ind];
 383 }
 384
 385 void scale_vcores_generic(u32 m)
 386 {
 387         int mpu_vdd;
 388
 389         if (i2c_probe(TPS65218_CHIP_PM))
 390                 return;
 391
 392         switch (m) {
 393         case 1000:
 394                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
 395                 break;
 396         case 800:
 397                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
 398                 break;
 399         case 720:
 400                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
 401                 break;
 402         case 600:
 403                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
 404                 break;
 405         case 300:
 406                 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
 407                 break;
 408         default:
 409                 puts("Unknown MPU clock, not scaling\n");
 410                 return;
 411         }
 412
 413         /* Set DCDC1 (CORE) voltage to 1.1V */
 414         if (tps65218_voltage_update(TPS65218_DCDC1,
 415                                     TPS65218_DCDC_VOLT_SEL_1100MV)) {
 416                 printf("%s failure\n", __func__);
 417                 return;
 418         }
 419
 420         /* Set DCDC2 (MPU) voltage */
 421         if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
 422                 printf("%s failure\n", __func__);
 423                 return;
 424         }
 425
 426         /* Set DCDC3 (DDR) voltage */
 427         if (tps65218_voltage_update(TPS65218_DCDC3,
 428             TPS65218_DCDC3_VOLT_SEL_1350MV)) {
 429                 printf("%s failure\n", __func__);
 430                 return;
 431         }
 432 }
 433
 434 void scale_vcores_idk(u32 m)
 435 {
 436         int mpu_vdd;
 437
 438         if (i2c_probe(TPS62362_I2C_ADDR))
 439                 return;
 440
 441         switch (m) {
 442         case 1000:
 443                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 444                 break;
 445         case 800:
 446                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
 447                 break;
 448         case 720:
 449                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
 450                 break;
 451         case 600:
 452                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
 453                 break;
 454         case 300:
 455                 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
 456                 break;
 457         default:
 458                 puts("Unknown MPU clock, not scaling\n");
 459                 return;
 460         }
 461
 462         /* Set VDD_MPU voltage */
 463         if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
 464                 printf("%s failure\n", __func__);
 465                 return;
 466         }
 467 }
 468
 469 void gpi2c_init(void)
 470 {
 471         /* When needed to be invoked prior to BSS initialization */
 472         static bool first_time = true;
 473
 474         if (first_time) {
 475                 enable_i2c0_pin_mux();
 476                 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
 477                          CONFIG_SYS_OMAP24_I2C_SLAVE);
 478                 first_time = false;
 479         }
 480 }
 481
 482 void scale_vcores(void)
 483 {
 484         const struct dpll_params *mpu_params;
 485
 486         /* Ensure I2C is initialized for PMIC configuration */
 487         gpi2c_init();
 488
 489         /* Get the frequency */
 490         mpu_params = get_dpll_mpu_params();
 491
 492         if (board_is_idk())
 493                 scale_vcores_idk(mpu_params->m);
 494         else
 495                 scale_vcores_generic(mpu_params->m);
 496 }
 497
 498 void set_uart_mux_conf(void)
 499 {
 500         enable_uart0_pin_mux();
 501 }
 502
 503 void set_mux_conf_regs(void)
 504 {
 505         enable_board_pin_mux();
 506 }
 507
 508 static void enable_vtt_regulator(void)
 509 {
 510         u32 temp;
 511
 512         /* enable module */
 513         writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
 514
 515         /* enable output for GPIO5_7 */
 516         writel(GPIO_SETDATAOUT(7),
 517                AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
 518         temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 519         temp = temp & ~(GPIO_OE_ENABLE(7));
 520         writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
 521 }
 522
 523 void sdram_init(void)
 524 {
 525         /*
 526          * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 527          * GP EMV has 1GB DDR3 connected to EMIF
 528          * along with VTT regulator.
 529          */
 530         if (board_is_eposevm()) {
 531                 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
 532         } else if (board_is_evm_14_or_later()) {
 533                 enable_vtt_regulator();
 534                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 535                            &ddr3_emif_regs_400Mhz_production, 0);
 536         } else if (board_is_evm_12_or_later()) {
 537                 enable_vtt_regulator();
 538                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 539                            &ddr3_emif_regs_400Mhz_beta, 0);
 540         } else if (board_is_evm()) {
 541                 enable_vtt_regulator();
 542                 config_ddr(0, &ioregs_ddr3, NULL, NULL,
 543                            &ddr3_emif_regs_400Mhz, 0);
 544         } else if (board_is_sk()) {
 545                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 546                            &ddr3_sk_emif_regs_400Mhz, 0);
 547         } else if (board_is_idk()) {
 548                 config_ddr(400, &ioregs_ddr3, NULL, NULL,
 549                            &ddr3_idk_emif_regs_400Mhz, 0);
 550         }
 551 }
 552 #endif
 553
 554 /* setup board specific PMIC */
 555 int power_init_board(void)
 556 {
 557         struct pmic *p;
 558
 559         if (board_is_idk()) {
 560                 power_tps62362_init(I2C_PMIC);
 561                 p = pmic_get("TPS62362");
 562                 if (p && !pmic_probe(p))
 563                         puts("PMIC:  TPS62362\n");
 564         } else {
 565                 power_tps65218_init(I2C_PMIC);
 566                 p = pmic_get("TPS65218_PMIC");
 567                 if (p && !pmic_probe(p))
 568                         puts("PMIC:  TPS65218\n");
 569         }
 570
 571         return 0;
 572 }
 573
 574 int board_init(void)
 575 {
 576         struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 577         u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 578             modena_init0_bw_integer, modena_init0_watermark_0;
 579
 580         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 581         gpmc_init();
 582
 583         /*
 584          * Call this to initialize *ctrl again
 585          */
 586         hw_data_init();
 587
 588         /* Clear all important bits for DSS errata that may need to be tweaked*/
 589         mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 590                            MREQPRIO_0_SAB_INIT0_MASK;
 591
 592         mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 593
 594         modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 595                                            BW_LIMITER_BW_FRAC_MASK;
 596
 597         modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 598                                         BW_LIMITER_BW_INT_MASK;
 599
 600         modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 601                                          BW_LIMITER_BW_WATERMARK_MASK;
 602
 603         /* Setting MReq Priority of the DSS*/
 604         mreqprio_0 |= 0x77;
 605
 606         /*
 607          * Set L3 Fast Configuration Register
 608          * Limiting bandwith for ARM core to 700 MBPS
 609          */
 610         modena_init0_bw_fractional |= 0x10;
 611         modena_init0_bw_integer |= 0x3;
 612
 613         writel(mreqprio_0, &cdev->mreqprio_0);
 614         writel(mreqprio_1, &cdev->mreqprio_1);
 615
 616         writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 617         writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 618         writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 619
 620         return 0;
 621 }
 622
 623 #ifdef CONFIG_BOARD_LATE_INIT
 624 int board_late_init(void)
 625 {
 626 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 627         set_board_info_env(NULL);
 628
 629         /*
 630          * Default FIT boot on HS devices. Non FIT images are not allowed
 631          * on HS devices.
 632          */
 633         if (get_device_type() == HS_DEVICE)
 634                 env_set("boot_fit", "1");
 635 #endif
 636         return 0;
 637 }
 638 #endif
 639
 640 #ifdef CONFIG_USB_DWC3
 641 static struct dwc3_device usb_otg_ss1 = {
 642         .maximum_speed = USB_SPEED_HIGH,
 643         .base = USB_OTG_SS1_BASE,
 644         .tx_fifo_resize = false,
 645         .index = 0,
 646 };
 647
 648 static struct dwc3_omap_device usb_otg_ss1_glue = {
 649         .base = (void *)USB_OTG_SS1_GLUE_BASE,
 650         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 651         .index = 0,
 652 };
 653
 654 static struct ti_usb_phy_device usb_phy1_device = {
 655         .usb2_phy_power = (void *)USB2_PHY1_POWER,
 656         .index = 0,
 657 };
 658
 659 static struct dwc3_device usb_otg_ss2 = {
 660         .maximum_speed = USB_SPEED_HIGH,
 661         .base = USB_OTG_SS2_BASE,
 662         .tx_fifo_resize = false,
 663         .index = 1,
 664 };
 665
 666 static struct dwc3_omap_device usb_otg_ss2_glue = {
 667         .base = (void *)USB_OTG_SS2_GLUE_BASE,
 668         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 669         .index = 1,
 670 };
 671
 672 static struct ti_usb_phy_device usb_phy2_device = {
 673         .usb2_phy_power = (void *)USB2_PHY2_POWER,
 674         .index = 1,
 675 };
 676
 677 int usb_gadget_handle_interrupts(int index)
 678 {
 679         u32 status;
 680
 681         status = dwc3_omap_uboot_interrupt_status(index);
 682         if (status)
 683                 dwc3_uboot_handle_interrupt(index);
 684
 685         return 0;
 686 }
 687 #endif /* CONFIG_USB_DWC3 */
 688
 689 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 690 int board_usb_init(int index, enum usb_init_type init)
 691 {
 692         enable_usb_clocks(index);
 693 #ifdef CONFIG_USB_DWC3
 694         switch (index) {
 695         case 0:
 696                 if (init == USB_INIT_DEVICE) {
 697                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 698                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 699                         dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 700                         ti_usb_phy_uboot_init(&usb_phy1_device);
 701                         dwc3_uboot_init(&usb_otg_ss1);
 702                 }
 703                 break;
 704         case 1:
 705                 if (init == USB_INIT_DEVICE) {
 706                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 707                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 708                         ti_usb_phy_uboot_init(&usb_phy2_device);
 709                         dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 710                         dwc3_uboot_init(&usb_otg_ss2);
 711                 }
 712                 break;
 713         default:
 714                 printf("Invalid Controller Index\n");
 715         }
 716 #endif
 717
 718         return 0;
 719 }
 720
 721 int board_usb_cleanup(int index, enum usb_init_type init)
 722 {
 723 #ifdef CONFIG_USB_DWC3
 724         switch (index) {
 725         case 0:
 726         case 1:
 727                 if (init == USB_INIT_DEVICE) {
 728                         ti_usb_phy_uboot_exit(index);
 729                         dwc3_uboot_exit(index);
 730                         dwc3_omap_uboot_exit(index);
 731                 }
 732                 break;
 733         default:
 734                 printf("Invalid Controller Index\n");
 735         }
 736 #endif
 737         disable_usb_clocks(index);
 738
 739         return 0;
 740 }
 741 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 742
 743 #ifdef CONFIG_DRIVER_TI_CPSW
 744
 745 static void cpsw_control(int enabled)
 746 {
 747         /* Additional controls can be added here */
 748         return;
 749 }
 750
 751 static struct cpsw_slave_data cpsw_slaves[] = {
 752         {
 753                 .slave_reg_ofs  = 0x208,
 754                 .sliver_reg_ofs = 0xd80,
 755                 .phy_addr       = 16,
 756         },
 757         {
 758                 .slave_reg_ofs  = 0x308,
 759                 .sliver_reg_ofs = 0xdc0,
 760                 .phy_addr       = 1,
 761         },
 762 };
 763
 764 static struct cpsw_platform_data cpsw_data = {
 765         .mdio_base              = CPSW_MDIO_BASE,
 766         .cpsw_base              = CPSW_BASE,
 767         .mdio_div               = 0xff,
 768         .channels               = 8,
 769         .cpdma_reg_ofs          = 0x800,
 770         .slaves                 = 1,
 771         .slave_data             = cpsw_slaves,
 772         .ale_reg_ofs            = 0xd00,
 773         .ale_entries            = 1024,
 774         .host_port_reg_ofs      = 0x108,
 775         .hw_stats_reg_ofs       = 0x900,
 776         .bd_ram_ofs             = 0x2000,
 777         .mac_control            = (1 << 5),
 778         .control                = cpsw_control,
 779         .host_port_num          = 0,
 780         .version                = CPSW_CTRL_VERSION_2,
 781 };
 782
 783 int board_eth_init(bd_t *bis)
 784 {
 785         int rv;
 786         uint8_t mac_addr[6];
 787         uint32_t mac_hi, mac_lo;
 788
 789         /* try reading mac address from efuse */
 790         mac_lo = readl(&cdev->macid0l);
 791         mac_hi = readl(&cdev->macid0h);
 792         mac_addr[0] = mac_hi & 0xFF;
 793         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 794         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 795         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 796         mac_addr[4] = mac_lo & 0xFF;
 797         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 798
 799         if (!env_get("ethaddr")) {
 800                 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
 801                 if (is_valid_ethaddr(mac_addr))
 802                         eth_env_set_enetaddr("ethaddr", mac_addr);
 803         }
 804
 805         mac_lo = readl(&cdev->macid1l);
 806         mac_hi = readl(&cdev->macid1h);
 807         mac_addr[0] = mac_hi & 0xFF;
 808         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 809         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 810         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 811         mac_addr[4] = mac_lo & 0xFF;
 812         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 813
 814         if (!env_get("eth1addr")) {
 815                 if (is_valid_ethaddr(mac_addr))
 816                         eth_env_set_enetaddr("eth1addr", mac_addr);
 817         }
 818
 819         if (board_is_eposevm()) {
 820                 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 821                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
 822                 cpsw_slaves[0].phy_addr = 16;
 823         } else if (board_is_sk()) {
 824                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 825                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 826                 cpsw_slaves[0].phy_addr = 4;
 827                 cpsw_slaves[1].phy_addr = 5;
 828         } else if (board_is_idk()) {
 829                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 830                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 831                 cpsw_slaves[0].phy_addr = 0;
 832         } else {
 833                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 834                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
 835                 cpsw_slaves[0].phy_addr = 0;
 836         }
 837
 838         rv = cpsw_register(&cpsw_data);
 839         if (rv < 0)
 840                 printf("Error %d registering CPSW switch\n", rv);
 841
 842         return rv;
 843 }
 844 #endif
 845
 846 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 847 int ft_board_setup(void *blob, bd_t *bd)
 848 {
 849         ft_cpu_setup(blob, bd);
 850
 851         return 0;
 852 }
 853 #endif
 854
 855 #ifdef CONFIG_SPL_LOAD_FIT
 856 int board_fit_config_name_match(const char *name)
 857 {
 858         if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
 859                 return 0;
 860         else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
 861                 return 0;
 862         else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
 863                 return 0;
 864         else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
 865                 return 0;
 866         else
 867                 return -1;
 868 }
 869 #endif
 870
 871 #ifdef CONFIG_TI_SECURE_DEVICE
 872 void board_fit_image_post_process(void **p_image, size_t *p_size)
 873 {
 874         secure_boot_verify_image(p_image, p_size);
 875 }
 876
 877 void board_tee_image_process(ulong tee_image, size_t tee_size)
 878 {
 879         secure_tee_install((u32)tee_image);
 880 }
 881
 882 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 883 #endif