2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
16 #include <asm/omap_sec_common.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/dra7xx_iodelay.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sata.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/omap.h>
27 #include <environment.h>
29 #include <linux/usb/gadget.h>
30 #include <dwc3-uboot.h>
31 #include <dwc3-omap-uboot.h>
32 #include <ti-usb-phy-uboot.h>
34 #include "../common/board_detect.h"
37 #define board_is_x15() board_ti_is("BBRDX15_")
38 #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
39 !strncmp("B.10", board_ti_get_rev(), 3))
40 #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
41 !strncmp("C.00", board_ti_get_rev(), 3))
42 #define board_is_am572x_evm() board_ti_is("AM572PM_")
43 #define board_is_am572x_evm_reva3() \
44 (board_ti_is("AM572PM_") && \
45 !strncmp("A.30", board_ti_get_rev(), 3))
46 #define board_is_am574x_idk() board_ti_is("AM574IDK")
47 #define board_is_am572x_idk() board_ti_is("AM572IDK")
48 #define board_is_am571x_idk() board_ti_is("AM571IDK")
50 #ifdef CONFIG_DRIVER_TI_CPSW
54 DECLARE_GLOBAL_DATA_PTR
;
56 #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
58 #define GPIO_DDR_VTT_EN 203
60 /* Touch screen controller to identify the LCD */
61 #define OSD_TS_FT_BUS_ADDRESS 0
62 #define OSD_TS_FT_CHIP_ADDRESS 0x38
63 #define OSD_TS_FT_REG_ID 0xA3
65 * Touchscreen IDs for various OSD panels
66 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
68 /* Used on newer osd101t2587 Panels */
69 #define OSD_TS_FT_ID_5x46 0x54
70 /* Used on older osd101t2045 Panels */
71 #define OSD_TS_FT_ID_5606 0x08
73 #define SYSINFO_BOARD_NAME_MAX_LEN 45
75 #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
76 #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
78 const struct omap_sysinfo sysinfo
= {
79 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
82 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs
= {
83 .dmm_lisa_map_3
= 0x80740300,
87 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs
= {
88 .dmm_lisa_map_3
= 0x80640100,
92 static const struct dmm_lisa_map_regs am574x_idk_lisa_regs
= {
93 .dmm_lisa_map_2
= 0xc0600200,
94 .dmm_lisa_map_3
= 0x80600100,
98 void emif_get_dmm_regs(const struct dmm_lisa_map_regs
**dmm_lisa_regs
)
100 if (board_is_am571x_idk())
101 *dmm_lisa_regs
= &am571x_idk_lisa_regs
;
102 else if (board_is_am574x_idk())
103 *dmm_lisa_regs
= &am574x_idk_lisa_regs
;
105 *dmm_lisa_regs
= &beagle_x15_lisa_regs
;
108 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs
= {
109 .sdram_config_init
= 0x61851b32,
110 .sdram_config
= 0x61851b32,
111 .sdram_config2
= 0x08000000,
112 .ref_ctrl
= 0x000040F1,
113 .ref_ctrl_final
= 0x00001035,
114 .sdram_tim1
= 0xcccf36ab,
115 .sdram_tim2
= 0x308f7fda,
116 .sdram_tim3
= 0x409f88a8,
117 .read_idle_ctrl
= 0x00050000,
118 .zq_config
= 0x5007190b,
119 .temp_alert_config
= 0x00000000,
120 .emif_ddr_phy_ctlr_1_init
= 0x0024400b,
121 .emif_ddr_phy_ctlr_1
= 0x0e24400b,
122 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
123 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
124 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
125 .emif_ddr_ext_phy_ctrl_4
= 0x009b009b,
126 .emif_ddr_ext_phy_ctrl_5
= 0x009e009e,
127 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
128 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
129 .emif_rd_wr_lvl_ctl
= 0x00000000,
130 .emif_rd_wr_exec_thresh
= 0x00000305
133 /* Ext phy ctrl regs 1-35 */
134 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
[] = {
172 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs
= {
173 .sdram_config_init
= 0x61851b32,
174 .sdram_config
= 0x61851b32,
175 .sdram_config2
= 0x08000000,
176 .ref_ctrl
= 0x000040F1,
177 .ref_ctrl_final
= 0x00001035,
178 .sdram_tim1
= 0xcccf36b3,
179 .sdram_tim2
= 0x308f7fda,
180 .sdram_tim3
= 0x407f88a8,
181 .read_idle_ctrl
= 0x00050000,
182 .zq_config
= 0x5007190b,
183 .temp_alert_config
= 0x00000000,
184 .emif_ddr_phy_ctlr_1_init
= 0x0024400b,
185 .emif_ddr_phy_ctlr_1
= 0x0e24400b,
186 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
187 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
188 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
189 .emif_ddr_ext_phy_ctrl_4
= 0x009b009b,
190 .emif_ddr_ext_phy_ctrl_5
= 0x009e009e,
191 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
192 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
193 .emif_rd_wr_lvl_ctl
= 0x00000000,
194 .emif_rd_wr_exec_thresh
= 0x00000305
197 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
[] = {
235 static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs
= {
236 .sdram_config_init
= 0x61863332,
237 .sdram_config
= 0x61863332,
238 .sdram_config2
= 0x08000000,
239 .ref_ctrl
= 0x0000514d,
240 .ref_ctrl_final
= 0x0000144a,
241 .sdram_tim1
= 0xd333887c,
242 .sdram_tim2
= 0x30b37fe3,
243 .sdram_tim3
= 0x409f8ad8,
244 .read_idle_ctrl
= 0x00050000,
245 .zq_config
= 0x5007190b,
246 .temp_alert_config
= 0x00000000,
247 .emif_ddr_phy_ctlr_1_init
= 0x0024400f,
248 .emif_ddr_phy_ctlr_1
= 0x0e24400f,
249 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
250 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
251 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
252 .emif_ddr_ext_phy_ctrl_4
= 0x009b009b,
253 .emif_ddr_ext_phy_ctrl_5
= 0x009e009e,
254 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
255 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
256 .emif_rd_wr_lvl_ctl
= 0x00000000,
257 .emif_rd_wr_exec_thresh
= 0x00000305
260 static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs
= {
261 .sdram_config_init
= 0x61863332,
262 .sdram_config
= 0x61863332,
263 .sdram_config2
= 0x08000000,
264 .ref_ctrl
= 0x0000514d,
265 .ref_ctrl_final
= 0x0000144a,
266 .sdram_tim1
= 0xd333887c,
267 .sdram_tim2
= 0x30b37fe3,
268 .sdram_tim3
= 0x409f8ad8,
269 .read_idle_ctrl
= 0x00050000,
270 .zq_config
= 0x5007190b,
271 .temp_alert_config
= 0x00000000,
272 .emif_ddr_phy_ctlr_1_init
= 0x0024400f,
273 .emif_ddr_phy_ctlr_1
= 0x0e24400f,
274 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
275 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
276 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
277 .emif_ddr_ext_phy_ctrl_4
= 0x009b009b,
278 .emif_ddr_ext_phy_ctrl_5
= 0x009e009e,
279 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
280 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
281 .emif_rd_wr_lvl_ctl
= 0x00000000,
282 .emif_rd_wr_exec_thresh
= 0x00000305,
283 .emif_ecc_ctrl_reg
= 0xD0000001,
284 .emif_ecc_address_range_1
= 0x3FFF0000,
285 .emif_ecc_address_range_2
= 0x00000000
288 void emif_get_reg_dump(u32 emif_nr
, const struct emif_regs
**regs
)
292 if (board_is_am571x_idk())
293 *regs
= &am571x_emif1_ddr3_666mhz_emif_regs
;
294 else if (board_is_am574x_idk())
295 *regs
= &am574x_emif1_ddr3_666mhz_emif_ecc_regs
;
297 *regs
= &beagle_x15_emif1_ddr3_532mhz_emif_regs
;
300 if (board_is_am574x_idk())
301 *regs
= &am571x_emif1_ddr3_666mhz_emif_regs
;
303 *regs
= &beagle_x15_emif2_ddr3_532mhz_emif_regs
;
308 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr
, const u32
**regs
, u32
*size
)
312 *regs
= beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
;
313 *size
= ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
);
316 *regs
= beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
;
317 *size
= ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
);
322 struct vcores_data beagle_x15_volts
= {
323 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
324 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
325 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
326 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
327 .mpu
.pmic
= &tps659038
,
328 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
330 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
331 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
332 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
333 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
334 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
335 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
336 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
337 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
338 .eve
.pmic
= &tps659038
,
339 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
341 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
342 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
343 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
344 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
345 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
346 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
347 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
348 .gpu
.addr
= TPS659038_REG_ADDR_SMPS45
,
349 .gpu
.pmic
= &tps659038
,
350 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
352 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
353 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
354 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
355 .core
.addr
= TPS659038_REG_ADDR_SMPS6
,
356 .core
.pmic
= &tps659038
,
358 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
359 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
360 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
361 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
362 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
363 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
364 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
365 .iva
.addr
= TPS659038_REG_ADDR_SMPS45
,
366 .iva
.pmic
= &tps659038
,
367 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
370 struct vcores_data am572x_idk_volts
= {
371 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
372 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
373 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
374 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
375 .mpu
.pmic
= &tps659038
,
376 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
378 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
379 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
380 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
381 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
382 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
383 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
384 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
385 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
386 .eve
.pmic
= &tps659038
,
387 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
389 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
390 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
391 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
392 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
393 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
394 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
395 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
396 .gpu
.addr
= TPS659038_REG_ADDR_SMPS6
,
397 .gpu
.pmic
= &tps659038
,
398 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
400 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
401 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
402 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
403 .core
.addr
= TPS659038_REG_ADDR_SMPS7
,
404 .core
.pmic
= &tps659038
,
406 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
407 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
408 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
409 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
410 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
411 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
412 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
413 .iva
.addr
= TPS659038_REG_ADDR_SMPS8
,
414 .iva
.pmic
= &tps659038
,
415 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
418 struct vcores_data am571x_idk_volts
= {
419 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
420 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
421 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
422 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
423 .mpu
.pmic
= &tps659038
,
424 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
426 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
427 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
428 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
429 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
430 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
431 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
432 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
433 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
434 .eve
.pmic
= &tps659038
,
435 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
437 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
438 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
439 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
440 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
441 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
442 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
443 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
444 .gpu
.addr
= TPS659038_REG_ADDR_SMPS6
,
445 .gpu
.pmic
= &tps659038
,
446 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
448 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
449 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
450 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
451 .core
.addr
= TPS659038_REG_ADDR_SMPS7
,
452 .core
.pmic
= &tps659038
,
454 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
455 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
456 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
457 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
458 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
459 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
460 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
461 .iva
.addr
= TPS659038_REG_ADDR_SMPS45
,
462 .iva
.pmic
= &tps659038
,
463 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
466 int get_voltrail_opp(int rail_offset
)
470 switch (rail_offset
) {
481 opp
= DRA7_DSPEVE_OPP
;
494 #ifdef CONFIG_SPL_BUILD
495 /* No env to setup for SPL */
496 static inline void setup_board_eeprom_env(void) { }
498 /* Override function to read eeprom information */
499 void do_board_detect(void)
503 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
504 CONFIG_EEPROM_CHIP_ADDRESS
);
506 printf("ti_i2c_eeprom_init failed %d\n", rc
);
509 #else /* CONFIG_SPL_BUILD */
511 /* Override function to read eeprom information: actual i2c read done by SPL*/
512 void do_board_detect(void)
517 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
518 CONFIG_EEPROM_CHIP_ADDRESS
);
520 printf("ti_i2c_eeprom_init failed %d\n", rc
);
523 bname
= "BeagleBoard X15";
524 else if (board_is_am572x_evm())
525 bname
= "AM572x EVM";
526 else if (board_is_am574x_idk())
527 bname
= "AM574x IDK";
528 else if (board_is_am572x_idk())
529 bname
= "AM572x IDK";
530 else if (board_is_am571x_idk())
531 bname
= "AM571x IDK";
534 snprintf(sysinfo
.board_string
, SYSINFO_BOARD_NAME_MAX_LEN
,
535 "Board: %s REV %s\n", bname
, board_ti_get_rev());
538 static void setup_board_eeprom_env(void)
540 char *name
= "beagle_x15";
543 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
544 CONFIG_EEPROM_CHIP_ADDRESS
);
548 if (board_is_x15()) {
549 if (board_is_x15_revb1())
550 name
= "beagle_x15_revb1";
551 else if (board_is_x15_revc())
552 name
= "beagle_x15_revc";
555 } else if (board_is_am572x_evm()) {
556 if (board_is_am572x_evm_reva3())
557 name
= "am57xx_evm_reva3";
560 } else if (board_is_am574x_idk()) {
562 } else if (board_is_am572x_idk()) {
564 } else if (board_is_am571x_idk()) {
567 printf("Unidentified board claims %s in eeprom header\n",
568 board_ti_get_name());
572 set_board_info_env(name
);
575 #endif /* CONFIG_SPL_BUILD */
577 void vcores_init(void)
579 if (board_is_am572x_idk() || board_is_am574x_idk())
580 *omap_vcores
= &am572x_idk_volts
;
581 else if (board_is_am571x_idk())
582 *omap_vcores
= &am571x_idk_volts
;
584 *omap_vcores
= &beagle_x15_volts
;
587 void hw_data_init(void)
589 *prcm
= &dra7xx_prcm
;
591 *dplls_data
= &dra72x_dplls
;
592 else if (is_dra76x())
593 *dplls_data
= &dra76x_dplls
;
595 *dplls_data
= &dra7xx_dplls
;
596 *ctrl
= &dra7xx_ctrl
;
599 bool am571x_idk_needs_lcd(void)
603 gpio_request(GPIO_ETH_LCD
, "nLCD_Detect");
604 if (gpio_get_value(GPIO_ETH_LCD
))
609 gpio_free(GPIO_ETH_LCD
);
617 gd
->bd
->bi_boot_params
= (CONFIG_SYS_SDRAM_BASE
+ 0x100);
622 void am57x_idk_lcd_detect(void)
625 char *idk_lcd
= "no";
628 /* Only valid for IDKs */
629 if (board_is_x15() || board_is_am572x_evm())
632 /* Only AM571x IDK has gpio control detect.. so check that */
633 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
636 r
= i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS
);
638 printf("%s: Failed to set bus address to %d: %d\n",
639 __func__
, OSD_TS_FT_BUS_ADDRESS
, r
);
642 r
= i2c_probe(OSD_TS_FT_CHIP_ADDRESS
);
644 /* AM572x IDK has no explicit settings for optional LCD kit */
645 if (board_is_am571x_idk()) {
646 printf("%s: Touch screen detect failed: %d!\n",
653 r
= i2c_read(OSD_TS_FT_CHIP_ADDRESS
, OSD_TS_FT_REG_ID
, 1, &buf
, 1);
655 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
656 __func__
, OSD_TS_FT_BUS_ADDRESS
, OSD_TS_FT_CHIP_ADDRESS
,
657 OSD_TS_FT_REG_ID
, r
);
662 case OSD_TS_FT_ID_5606
:
663 idk_lcd
= "osd101t2045";
665 case OSD_TS_FT_ID_5x46
:
666 idk_lcd
= "osd101t2587";
669 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
671 /* we will let default be "no lcd" */
674 env_set("idk_lcd", idk_lcd
);
678 int board_late_init(void)
680 setup_board_eeprom_env();
684 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
685 * This is the POWERHOLD-in-Low behavior.
687 palmas_i2c_write_u8(TPS65903X_CHIP_P1
, 0xA0, 0x1);
690 * Default FIT boot on HS devices. Non FIT images are not allowed
693 if (get_device_type() == HS_DEVICE
)
694 env_set("boot_fit", "1");
697 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
698 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
699 * PMIC Power off. So to be on the safer side set it back
700 * to POWERHOLD mode irrespective of the current state.
702 palmas_i2c_read_u8(TPS65903X_CHIP_P1
, TPS65903X_PRIMARY_SECONDARY_PAD2
,
704 val
= val
| TPS65903X_PAD2_POWERHOLD_MASK
;
705 palmas_i2c_write_u8(TPS65903X_CHIP_P1
, TPS65903X_PRIMARY_SECONDARY_PAD2
,
708 omap_die_id_serial();
709 omap_set_fastboot_vars();
711 am57x_idk_lcd_detect();
713 #if !defined(CONFIG_SPL_BUILD)
714 board_ti_set_ethaddr(2);
720 void set_muxconf_regs(void)
722 do_set_mux32((*ctrl
)->control_padconf_core_base
,
723 early_padconf
, ARRAY_SIZE(early_padconf
));
726 #ifdef CONFIG_IODELAY_RECALIBRATION
727 void recalibrate_iodelay(void)
729 const struct pad_conf_entry
*pconf
;
730 const struct iodelay_cfg_entry
*iod
, *delta_iod
;
731 int pconf_sz
, iod_sz
, delta_iod_sz
= 0;
734 if (board_is_am572x_idk()) {
735 pconf
= core_padconf_array_essential_am572x_idk
;
736 pconf_sz
= ARRAY_SIZE(core_padconf_array_essential_am572x_idk
);
737 iod
= iodelay_cfg_array_am572x_idk
;
738 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_am572x_idk
);
739 } else if (board_is_am574x_idk()) {
740 pconf
= core_padconf_array_essential_am574x_idk
;
741 pconf_sz
= ARRAY_SIZE(core_padconf_array_essential_am574x_idk
);
742 iod
= iodelay_cfg_array_am574x_idk
;
743 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_am574x_idk
);
744 } else if (board_is_am571x_idk()) {
745 pconf
= core_padconf_array_essential_am571x_idk
;
746 pconf_sz
= ARRAY_SIZE(core_padconf_array_essential_am571x_idk
);
747 iod
= iodelay_cfg_array_am571x_idk
;
748 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_am571x_idk
);
750 /* Common for X15/GPEVM */
751 pconf
= core_padconf_array_essential_x15
;
752 pconf_sz
= ARRAY_SIZE(core_padconf_array_essential_x15
);
753 /* There never was an SR1.0 X15.. So.. */
754 if (omap_revision() == DRA752_ES1_1
) {
755 iod
= iodelay_cfg_array_x15_sr1_1
;
756 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1
);
758 /* Since full production should switch to SR2.0 */
759 iod
= iodelay_cfg_array_x15_sr2_0
;
760 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0
);
764 /* Setup I/O isolation */
765 ret
= __recalibrate_iodelay_start();
769 /* Do the muxing here */
770 do_set_mux32((*ctrl
)->control_padconf_core_base
, pconf
, pconf_sz
);
772 /* Now do the weird minor deltas that should be safe */
773 if (board_is_x15() || board_is_am572x_evm()) {
774 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
775 board_is_x15_revc()) {
776 pconf
= core_padconf_array_delta_x15_sr2_0
;
777 pconf_sz
= ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0
);
779 pconf
= core_padconf_array_delta_x15_sr1_1
;
780 pconf_sz
= ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1
);
782 do_set_mux32((*ctrl
)->control_padconf_core_base
, pconf
, pconf_sz
);
785 if (board_is_am571x_idk()) {
786 if (am571x_idk_needs_lcd()) {
787 pconf
= core_padconf_array_vout_am571x_idk
;
788 pconf_sz
= ARRAY_SIZE(core_padconf_array_vout_am571x_idk
);
789 delta_iod
= iodelay_cfg_array_am571x_idk_4port
;
790 delta_iod_sz
= ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port
);
793 pconf
= core_padconf_array_icss1eth_am571x_idk
;
794 pconf_sz
= ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk
);
796 do_set_mux32((*ctrl
)->control_padconf_core_base
, pconf
, pconf_sz
);
799 /* Setup IOdelay configuration */
800 ret
= do_set_iodelay((*ctrl
)->iodelay_config_base
, iod
, iod_sz
);
802 ret
= do_set_iodelay((*ctrl
)->iodelay_config_base
, delta_iod
,
806 /* Closeup.. remove isolation */
807 __recalibrate_iodelay_end(ret
);
811 #if defined(CONFIG_MMC)
812 int board_mmc_init(bd_t
*bis
)
814 omap_mmc_init(0, 0, 0, -1, -1);
815 omap_mmc_init(1, 0, 0, -1, -1);
820 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
821 int spl_start_uboot(void)
823 /* break into full u-boot on 'c' */
824 if (serial_tstc() && serial_getc() == 'c')
827 #ifdef CONFIG_SPL_ENV_SUPPORT
830 if (env_get_yesno("boot_os") != 1)
838 #ifdef CONFIG_USB_DWC3
839 static struct dwc3_device usb_otg_ss2
= {
840 .maximum_speed
= USB_SPEED_HIGH
,
841 .base
= DRA7_USB_OTG_SS2_BASE
,
842 .tx_fifo_resize
= false,
846 static struct dwc3_omap_device usb_otg_ss2_glue
= {
847 .base
= (void *)DRA7_USB_OTG_SS2_GLUE_BASE
,
848 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
852 static struct ti_usb_phy_device usb_phy2_device
= {
853 .usb2_phy_power
= (void *)DRA7_USB2_PHY2_POWER
,
857 int usb_gadget_handle_interrupts(int index
)
861 status
= dwc3_omap_uboot_interrupt_status(index
);
863 dwc3_uboot_handle_interrupt(index
);
867 #endif /* CONFIG_USB_DWC3 */
869 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
870 int omap_xhci_board_usb_init(int index
, enum usb_init_type init
)
872 enable_usb_clocks(index
);
875 if (init
== USB_INIT_DEVICE
) {
876 printf("port %d can't be used as device\n", index
);
877 disable_usb_clocks(index
);
882 if (init
== USB_INIT_DEVICE
) {
883 #ifdef CONFIG_USB_DWC3
884 usb_otg_ss2
.dr_mode
= USB_DR_MODE_PERIPHERAL
;
885 usb_otg_ss2_glue
.vbus_id_status
= OMAP_DWC3_VBUS_VALID
;
886 ti_usb_phy_uboot_init(&usb_phy2_device
);
887 dwc3_omap_uboot_init(&usb_otg_ss2_glue
);
888 dwc3_uboot_init(&usb_otg_ss2
);
891 printf("port %d can't be used as host\n", index
);
892 disable_usb_clocks(index
);
898 printf("Invalid Controller Index\n");
904 int omap_xhci_board_usb_cleanup(int index
, enum usb_init_type init
)
906 #ifdef CONFIG_USB_DWC3
910 if (init
== USB_INIT_DEVICE
) {
911 ti_usb_phy_uboot_exit(index
);
912 dwc3_uboot_exit(index
);
913 dwc3_omap_uboot_exit(index
);
917 printf("Invalid Controller Index\n");
920 disable_usb_clocks(index
);
923 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
925 #ifdef CONFIG_DRIVER_TI_CPSW
927 /* Delay value to add to calibrated value */
928 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
929 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
930 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
931 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
932 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
933 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
934 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
935 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
936 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
937 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
939 static void cpsw_control(int enabled
)
941 /* VTP can be added here */
944 static struct cpsw_slave_data cpsw_slaves
[] = {
946 .slave_reg_ofs
= 0x208,
947 .sliver_reg_ofs
= 0xd80,
951 .slave_reg_ofs
= 0x308,
952 .sliver_reg_ofs
= 0xdc0,
957 static struct cpsw_platform_data cpsw_data
= {
958 .mdio_base
= CPSW_MDIO_BASE
,
959 .cpsw_base
= CPSW_BASE
,
962 .cpdma_reg_ofs
= 0x800,
964 .slave_data
= cpsw_slaves
,
965 .ale_reg_ofs
= 0xd00,
967 .host_port_reg_ofs
= 0x108,
968 .hw_stats_reg_ofs
= 0x900,
969 .bd_ram_ofs
= 0x2000,
970 .mac_control
= (1 << 5),
971 .control
= cpsw_control
,
973 .version
= CPSW_CTRL_VERSION_2
,
976 static u64
mac_to_u64(u8 mac
[6])
981 for (i
= 0; i
< 6; i
++) {
989 static void u64_to_mac(u64 addr
, u8 mac
[6])
999 int board_eth_init(bd_t
*bis
)
1002 uint8_t mac_addr
[6];
1003 uint32_t mac_hi
, mac_lo
;
1007 u8 mac_addr1
[6], mac_addr2
[6];
1010 /* try reading mac address from efuse */
1011 mac_lo
= readl((*ctrl
)->control_core_mac_id_0_lo
);
1012 mac_hi
= readl((*ctrl
)->control_core_mac_id_0_hi
);
1013 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
1014 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
1015 mac_addr
[2] = mac_hi
& 0xFF;
1016 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
1017 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
1018 mac_addr
[5] = mac_lo
& 0xFF;
1020 if (!env_get("ethaddr")) {
1021 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1023 if (is_valid_ethaddr(mac_addr
))
1024 eth_env_set_enetaddr("ethaddr", mac_addr
);
1027 mac_lo
= readl((*ctrl
)->control_core_mac_id_1_lo
);
1028 mac_hi
= readl((*ctrl
)->control_core_mac_id_1_hi
);
1029 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
1030 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
1031 mac_addr
[2] = mac_hi
& 0xFF;
1032 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
1033 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
1034 mac_addr
[5] = mac_lo
& 0xFF;
1036 if (!env_get("eth1addr")) {
1037 if (is_valid_ethaddr(mac_addr
))
1038 eth_env_set_enetaddr("eth1addr", mac_addr
);
1041 ctrl_val
= readl((*ctrl
)->control_core_control_io1
) & (~0x33);
1043 writel(ctrl_val
, (*ctrl
)->control_core_control_io1
);
1045 /* The phy address for the AM57xx IDK are different than x15 */
1046 if (board_is_am572x_idk() || board_is_am571x_idk() ||
1047 board_is_am574x_idk()) {
1048 cpsw_data
.slave_data
[0].phy_addr
= 0;
1049 cpsw_data
.slave_data
[1].phy_addr
= 1;
1052 ret
= cpsw_register(&cpsw_data
);
1054 printf("Error %d registering CPSW switch\n", ret
);
1057 * Export any Ethernet MAC addresses from EEPROM.
1058 * On AM57xx the 2 MAC addresses define the address range
1060 board_ti_get_eth_mac_addr(0, mac_addr1
);
1061 board_ti_get_eth_mac_addr(1, mac_addr2
);
1063 if (is_valid_ethaddr(mac_addr1
) && is_valid_ethaddr(mac_addr2
)) {
1064 mac1
= mac_to_u64(mac_addr1
);
1065 mac2
= mac_to_u64(mac_addr2
);
1067 /* must contain an address range */
1068 num_macs
= mac2
- mac1
+ 1;
1069 /* <= 50 to protect against user programming error */
1070 if (num_macs
> 0 && num_macs
<= 50) {
1071 for (i
= 0; i
< num_macs
; i
++) {
1072 u64_to_mac(mac1
+ i
, mac_addr
);
1073 if (is_valid_ethaddr(mac_addr
)) {
1074 eth_env_set_enetaddr_by_index("eth",
1086 #ifdef CONFIG_BOARD_EARLY_INIT_F
1087 /* VTT regulator enable */
1088 static inline void vtt_regulator_enable(void)
1090 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL
)
1093 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
1094 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
1097 int board_early_init_f(void)
1099 vtt_regulator_enable();
1104 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1105 int ft_board_setup(void *blob
, bd_t
*bd
)
1107 ft_cpu_setup(blob
, bd
);
1113 #ifdef CONFIG_SPL_LOAD_FIT
1114 int board_fit_config_name_match(const char *name
)
1116 if (board_is_x15()) {
1117 if (board_is_x15_revb1()) {
1118 if (!strcmp(name
, "am57xx-beagle-x15-revb1"))
1120 } else if (board_is_x15_revc()) {
1121 if (!strcmp(name
, "am57xx-beagle-x15-revc"))
1123 } else if (!strcmp(name
, "am57xx-beagle-x15")) {
1126 } else if (board_is_am572x_evm() &&
1127 !strcmp(name
, "am57xx-beagle-x15")) {
1129 } else if (board_is_am572x_idk() && !strcmp(name
, "am572x-idk")) {
1131 } else if (board_is_am574x_idk() && !strcmp(name
, "am574x-idk")) {
1133 } else if (board_is_am571x_idk() && !strcmp(name
, "am571x-idk")) {
1141 #ifdef CONFIG_TI_SECURE_DEVICE
1142 void board_fit_image_post_process(void **p_image
, size_t *p_size
)
1144 secure_boot_verify_image(p_image
, p_size
);
1147 void board_tee_image_process(ulong tee_image
, size_t tee_size
)
1149 secure_tee_install((u32
)tee_image
);
1152 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE
, board_tee_image_process
);