2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
16 #include <asm/omap_sec_common.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/dra7xx_iodelay.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sata.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/omap.h>
27 #include <environment.h>
29 #include <linux/usb/gadget.h>
30 #include <dwc3-uboot.h>
31 #include <dwc3-omap-uboot.h>
32 #include <ti-usb-phy-uboot.h>
34 #include "../common/board_detect.h"
37 #define board_is_x15() board_ti_is("BBRDX15_")
38 #define board_is_am572x_evm() board_ti_is("AM572PM_")
39 #define board_is_am572x_evm_reva3() \
40 (board_ti_is("AM572PM_") && \
41 (strncmp("A.30", board_ti_get_rev(), 3) <= 0))
42 #define board_is_am572x_idk() board_ti_is("AM572IDK")
44 #ifdef CONFIG_DRIVER_TI_CPSW
48 DECLARE_GLOBAL_DATA_PTR
;
51 #define GPIO_DDR_VTT_EN 203
53 #define SYSINFO_BOARD_NAME_MAX_LEN 45
55 const struct omap_sysinfo sysinfo
= {
56 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
59 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs
= {
60 .dmm_lisa_map_3
= 0x80740300,
64 void emif_get_dmm_regs(const struct dmm_lisa_map_regs
**dmm_lisa_regs
)
66 *dmm_lisa_regs
= &beagle_x15_lisa_regs
;
69 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs
= {
70 .sdram_config_init
= 0x61851b32,
71 .sdram_config
= 0x61851b32,
72 .sdram_config2
= 0x08000000,
73 .ref_ctrl
= 0x000040F1,
74 .ref_ctrl_final
= 0x00001035,
75 .sdram_tim1
= 0xcccf36ab,
76 .sdram_tim2
= 0x308f7fda,
77 .sdram_tim3
= 0x409f88a8,
78 .read_idle_ctrl
= 0x00050000,
79 .zq_config
= 0x5007190b,
80 .temp_alert_config
= 0x00000000,
81 .emif_ddr_phy_ctlr_1_init
= 0x0024400b,
82 .emif_ddr_phy_ctlr_1
= 0x0e24400b,
83 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
84 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
85 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
86 .emif_ddr_ext_phy_ctrl_4
= 0x009b009b,
87 .emif_ddr_ext_phy_ctrl_5
= 0x009e009e,
88 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
89 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
90 .emif_rd_wr_lvl_ctl
= 0x00000000,
91 .emif_rd_wr_exec_thresh
= 0x00000305
94 /* Ext phy ctrl regs 1-35 */
95 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
[] = {
133 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs
= {
134 .sdram_config_init
= 0x61851b32,
135 .sdram_config
= 0x61851b32,
136 .sdram_config2
= 0x08000000,
137 .ref_ctrl
= 0x000040F1,
138 .ref_ctrl_final
= 0x00001035,
139 .sdram_tim1
= 0xcccf36b3,
140 .sdram_tim2
= 0x308f7fda,
141 .sdram_tim3
= 0x407f88a8,
142 .read_idle_ctrl
= 0x00050000,
143 .zq_config
= 0x5007190b,
144 .temp_alert_config
= 0x00000000,
145 .emif_ddr_phy_ctlr_1_init
= 0x0024400b,
146 .emif_ddr_phy_ctlr_1
= 0x0e24400b,
147 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
148 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
149 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
150 .emif_ddr_ext_phy_ctrl_4
= 0x009b009b,
151 .emif_ddr_ext_phy_ctrl_5
= 0x009e009e,
152 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
153 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
154 .emif_rd_wr_lvl_ctl
= 0x00000000,
155 .emif_rd_wr_exec_thresh
= 0x00000305
158 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
[] = {
196 void emif_get_reg_dump(u32 emif_nr
, const struct emif_regs
**regs
)
200 *regs
= &beagle_x15_emif1_ddr3_532mhz_emif_regs
;
203 *regs
= &beagle_x15_emif2_ddr3_532mhz_emif_regs
;
208 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr
, const u32
**regs
, u32
*size
)
212 *regs
= beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
;
213 *size
= ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs
);
216 *regs
= beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
;
217 *size
= ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs
);
222 struct vcores_data beagle_x15_volts
= {
223 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
224 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
225 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
226 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
227 .mpu
.pmic
= &tps659038
,
228 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
230 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
231 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
232 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
233 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
234 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
235 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
236 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
237 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
238 .eve
.pmic
= &tps659038
,
239 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
241 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
242 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
243 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
244 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
245 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
246 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
247 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
248 .gpu
.addr
= TPS659038_REG_ADDR_SMPS45
,
249 .gpu
.pmic
= &tps659038
,
250 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
252 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
253 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
254 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
255 .core
.addr
= TPS659038_REG_ADDR_SMPS6
,
256 .core
.pmic
= &tps659038
,
258 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
259 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
260 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
261 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
262 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
263 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
264 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
265 .iva
.addr
= TPS659038_REG_ADDR_SMPS45
,
266 .iva
.pmic
= &tps659038
,
267 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
270 struct vcores_data am572x_idk_volts
= {
271 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
272 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
273 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
274 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
275 .mpu
.pmic
= &tps659038
,
276 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
278 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
279 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
280 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
281 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
282 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
283 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
284 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
285 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
286 .eve
.pmic
= &tps659038
,
287 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
289 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
290 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
291 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
292 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
293 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
294 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
295 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
296 .gpu
.addr
= TPS659038_REG_ADDR_SMPS6
,
297 .gpu
.pmic
= &tps659038
,
298 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
300 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
301 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
302 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
303 .core
.addr
= TPS659038_REG_ADDR_SMPS7
,
304 .core
.pmic
= &tps659038
,
306 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
307 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
308 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
309 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
310 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
311 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
312 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
313 .iva
.addr
= TPS659038_REG_ADDR_SMPS8
,
314 .iva
.pmic
= &tps659038
,
315 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
318 int get_voltrail_opp(int rail_offset
)
322 switch (rail_offset
) {
333 opp
= DRA7_DSPEVE_OPP
;
346 #ifdef CONFIG_SPL_BUILD
347 /* No env to setup for SPL */
348 static inline void setup_board_eeprom_env(void) { }
350 /* Override function to read eeprom information */
351 void do_board_detect(void)
355 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
356 CONFIG_EEPROM_CHIP_ADDRESS
);
358 printf("ti_i2c_eeprom_init failed %d\n", rc
);
361 #else /* CONFIG_SPL_BUILD */
363 /* Override function to read eeprom information: actual i2c read done by SPL*/
364 void do_board_detect(void)
369 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
370 CONFIG_EEPROM_CHIP_ADDRESS
);
372 printf("ti_i2c_eeprom_init failed %d\n", rc
);
375 bname
= "BeagleBoard X15";
376 else if (board_is_am572x_evm())
377 bname
= "AM572x EVM";
378 else if (board_is_am572x_idk())
379 bname
= "AM572x IDK";
382 snprintf(sysinfo
.board_string
, SYSINFO_BOARD_NAME_MAX_LEN
,
383 "Board: %s REV %s\n", bname
, board_ti_get_rev());
386 static void setup_board_eeprom_env(void)
388 char *name
= "beagle_x15";
391 rc
= ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS
,
392 CONFIG_EEPROM_CHIP_ADDRESS
);
396 if (board_is_x15()) {
398 } else if (board_is_am572x_evm()) {
399 if (board_is_am572x_evm_reva3())
400 name
= "am57xx_evm_reva3";
403 } else if (board_is_am572x_idk()) {
406 printf("Unidentified board claims %s in eeprom header\n",
407 board_ti_get_name());
411 set_board_info_env(name
);
414 #endif /* CONFIG_SPL_BUILD */
416 void vcores_init(void)
418 if (board_is_am572x_idk())
419 *omap_vcores
= &am572x_idk_volts
;
421 *omap_vcores
= &beagle_x15_volts
;
424 void hw_data_init(void)
426 *prcm
= &dra7xx_prcm
;
427 *dplls_data
= &dra7xx_dplls
;
428 *ctrl
= &dra7xx_ctrl
;
434 gd
->bd
->bi_boot_params
= (CONFIG_SYS_SDRAM_BASE
+ 0x100);
439 int board_late_init(void)
441 setup_board_eeprom_env();
444 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
445 * This is the POWERHOLD-in-Low behavior.
447 palmas_i2c_write_u8(TPS65903X_CHIP_P1
, 0xA0, 0x1);
450 * Default FIT boot on HS devices. Non FIT images are not allowed
453 if (get_device_type() == HS_DEVICE
)
454 setenv("boot_fit", "1");
459 void set_muxconf_regs(void)
461 do_set_mux32((*ctrl
)->control_padconf_core_base
,
462 early_padconf
, ARRAY_SIZE(early_padconf
));
465 #ifdef CONFIG_IODELAY_RECALIBRATION
466 void recalibrate_iodelay(void)
468 const struct pad_conf_entry
*pconf
;
469 const struct iodelay_cfg_entry
*iod
;
470 int pconf_sz
, iod_sz
;
472 if (board_is_am572x_idk()) {
473 pconf
= core_padconf_array_essential_am572x_idk
;
474 pconf_sz
= ARRAY_SIZE(core_padconf_array_essential_am572x_idk
);
475 iod
= iodelay_cfg_array_am572x_idk
;
476 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_am572x_idk
);
478 /* Common for X15/GPEVM */
479 pconf
= core_padconf_array_essential_x15
;
480 pconf_sz
= ARRAY_SIZE(core_padconf_array_essential_x15
);
481 iod
= iodelay_cfg_array_x15
;
482 iod_sz
= ARRAY_SIZE(iodelay_cfg_array_x15
);
485 __recalibrate_iodelay(pconf
, pconf_sz
, iod
, iod_sz
);
489 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
490 int board_mmc_init(bd_t
*bis
)
492 omap_mmc_init(0, 0, 0, -1, -1);
493 omap_mmc_init(1, 0, 0, -1, -1);
498 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
499 int spl_start_uboot(void)
501 /* break into full u-boot on 'c' */
502 if (serial_tstc() && serial_getc() == 'c')
505 #ifdef CONFIG_SPL_ENV_SUPPORT
508 if (getenv_yesno("boot_os") != 1)
516 #ifdef CONFIG_USB_DWC3
517 static struct dwc3_device usb_otg_ss2
= {
518 .maximum_speed
= USB_SPEED_HIGH
,
519 .base
= DRA7_USB_OTG_SS2_BASE
,
520 .tx_fifo_resize
= false,
524 static struct dwc3_omap_device usb_otg_ss2_glue
= {
525 .base
= (void *)DRA7_USB_OTG_SS2_GLUE_BASE
,
526 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
530 static struct ti_usb_phy_device usb_phy2_device
= {
531 .usb2_phy_power
= (void *)DRA7_USB2_PHY2_POWER
,
535 int usb_gadget_handle_interrupts(int index
)
539 status
= dwc3_omap_uboot_interrupt_status(index
);
541 dwc3_uboot_handle_interrupt(index
);
545 #endif /* CONFIG_USB_DWC3 */
547 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
548 int board_usb_init(int index
, enum usb_init_type init
)
550 enable_usb_clocks(index
);
553 if (init
== USB_INIT_DEVICE
) {
554 printf("port %d can't be used as device\n", index
);
555 disable_usb_clocks(index
);
560 if (init
== USB_INIT_DEVICE
) {
561 #ifdef CONFIG_USB_DWC3
562 usb_otg_ss2
.dr_mode
= USB_DR_MODE_PERIPHERAL
;
563 usb_otg_ss2_glue
.vbus_id_status
= OMAP_DWC3_VBUS_VALID
;
564 ti_usb_phy_uboot_init(&usb_phy2_device
);
565 dwc3_omap_uboot_init(&usb_otg_ss2_glue
);
566 dwc3_uboot_init(&usb_otg_ss2
);
569 printf("port %d can't be used as host\n", index
);
570 disable_usb_clocks(index
);
576 printf("Invalid Controller Index\n");
582 int board_usb_cleanup(int index
, enum usb_init_type init
)
584 #ifdef CONFIG_USB_DWC3
588 if (init
== USB_INIT_DEVICE
) {
589 ti_usb_phy_uboot_exit(index
);
590 dwc3_uboot_exit(index
);
591 dwc3_omap_uboot_exit(index
);
595 printf("Invalid Controller Index\n");
598 disable_usb_clocks(index
);
601 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
603 #ifdef CONFIG_DRIVER_TI_CPSW
605 /* Delay value to add to calibrated value */
606 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
607 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
608 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
609 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
610 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
611 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
612 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
613 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
614 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
615 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
617 static void cpsw_control(int enabled
)
619 /* VTP can be added here */
622 static struct cpsw_slave_data cpsw_slaves
[] = {
624 .slave_reg_ofs
= 0x208,
625 .sliver_reg_ofs
= 0xd80,
629 .slave_reg_ofs
= 0x308,
630 .sliver_reg_ofs
= 0xdc0,
635 static struct cpsw_platform_data cpsw_data
= {
636 .mdio_base
= CPSW_MDIO_BASE
,
637 .cpsw_base
= CPSW_BASE
,
640 .cpdma_reg_ofs
= 0x800,
642 .slave_data
= cpsw_slaves
,
643 .ale_reg_ofs
= 0xd00,
645 .host_port_reg_ofs
= 0x108,
646 .hw_stats_reg_ofs
= 0x900,
647 .bd_ram_ofs
= 0x2000,
648 .mac_control
= (1 << 5),
649 .control
= cpsw_control
,
651 .version
= CPSW_CTRL_VERSION_2
,
654 static u64
mac_to_u64(u8 mac
[6])
659 for (i
= 0; i
< 6; i
++) {
667 static void u64_to_mac(u64 addr
, u8 mac
[6])
677 int board_eth_init(bd_t
*bis
)
681 uint32_t mac_hi
, mac_lo
;
685 u8 mac_addr1
[6], mac_addr2
[6];
688 /* try reading mac address from efuse */
689 mac_lo
= readl((*ctrl
)->control_core_mac_id_0_lo
);
690 mac_hi
= readl((*ctrl
)->control_core_mac_id_0_hi
);
691 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
692 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
693 mac_addr
[2] = mac_hi
& 0xFF;
694 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
695 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
696 mac_addr
[5] = mac_lo
& 0xFF;
698 if (!getenv("ethaddr")) {
699 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
701 if (is_valid_ethaddr(mac_addr
))
702 eth_setenv_enetaddr("ethaddr", mac_addr
);
705 mac_lo
= readl((*ctrl
)->control_core_mac_id_1_lo
);
706 mac_hi
= readl((*ctrl
)->control_core_mac_id_1_hi
);
707 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
708 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
709 mac_addr
[2] = mac_hi
& 0xFF;
710 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
711 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
712 mac_addr
[5] = mac_lo
& 0xFF;
714 if (!getenv("eth1addr")) {
715 if (is_valid_ethaddr(mac_addr
))
716 eth_setenv_enetaddr("eth1addr", mac_addr
);
719 ctrl_val
= readl((*ctrl
)->control_core_control_io1
) & (~0x33);
721 writel(ctrl_val
, (*ctrl
)->control_core_control_io1
);
723 /* The phy address for the AM572x IDK are different than x15 */
724 if (board_is_am572x_idk()) {
725 cpsw_data
.slave_data
[0].phy_addr
= 0;
726 cpsw_data
.slave_data
[1].phy_addr
= 1;
729 ret
= cpsw_register(&cpsw_data
);
731 printf("Error %d registering CPSW switch\n", ret
);
734 * Export any Ethernet MAC addresses from EEPROM.
735 * On AM57xx the 2 MAC addresses define the address range
737 board_ti_get_eth_mac_addr(0, mac_addr1
);
738 board_ti_get_eth_mac_addr(1, mac_addr2
);
740 if (is_valid_ethaddr(mac_addr1
) && is_valid_ethaddr(mac_addr2
)) {
741 mac1
= mac_to_u64(mac_addr1
);
742 mac2
= mac_to_u64(mac_addr2
);
744 /* must contain an address range */
745 num_macs
= mac2
- mac1
+ 1;
746 /* <= 50 to protect against user programming error */
747 if (num_macs
> 0 && num_macs
<= 50) {
748 for (i
= 0; i
< num_macs
; i
++) {
749 u64_to_mac(mac1
+ i
, mac_addr
);
750 if (is_valid_ethaddr(mac_addr
)) {
751 eth_setenv_enetaddr_by_index("eth",
763 #ifdef CONFIG_BOARD_EARLY_INIT_F
764 /* VTT regulator enable */
765 static inline void vtt_regulator_enable(void)
767 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL
)
770 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
771 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
774 int board_early_init_f(void)
776 vtt_regulator_enable();
781 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
782 int ft_board_setup(void *blob
, bd_t
*bd
)
784 ft_cpu_setup(blob
, bd
);
790 #ifdef CONFIG_SPL_LOAD_FIT
791 int board_fit_config_name_match(const char *name
)
793 if (board_is_x15() && !strcmp(name
, "am57xx-beagle-x15"))
795 else if (board_is_am572x_evm() && !strcmp(name
, "am57xx-beagle-x15"))
797 else if (board_is_am572x_idk() && !strcmp(name
, "am572x-idk"))
804 #ifdef CONFIG_TI_SECURE_DEVICE
805 void board_fit_image_post_process(void **p_image
, size_t *p_size
)
807 secure_boot_verify_image(p_image
, p_size
);
810 void board_tee_image_process(ulong tee_image
, size_t tee_size
)
812 secure_tee_install((u32
)tee_image
);
815 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE
, board_tee_image_process
);