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ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1
[people/ms/u-boot.git] / board / ti / dra7xx / evm.c
1 /*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13 #include <common.h>
14 #include <palmas.h>
15 #include <sata.h>
16 #include <linux/string.h>
17 #include <asm/gpio.h>
18 #include <usb.h>
19 #include <linux/usb/gadget.h>
20 #include <asm/omap_common.h>
21 #include <asm/omap_sec_common.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/dra7xx_iodelay.h>
24 #include <asm/emif.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/sata.h>
28 #include <environment.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
32 #include <miiphy.h>
33
34 #include "mux_data.h"
35 #include "../common/board_detect.h"
36
37 #define board_is_dra76x_evm() board_ti_is("DRA76/7x")
38 #define board_is_dra74x_evm() board_ti_is("5777xCPU")
39 #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
40 #define board_is_dra71x_evm() board_ti_is("DRA79x,D")
41 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
42 (strncmp("H", board_ti_get_rev(), 1) <= 0))
43 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
44 (strncmp("C", board_ti_get_rev(), 1) <= 0))
45 #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
46 board_ti_get_emif2_size()
47
48 #ifdef CONFIG_DRIVER_TI_CPSW
49 #include <cpsw.h>
50 #endif
51
52 DECLARE_GLOBAL_DATA_PTR;
53
54 /* GPIO 7_11 */
55 #define GPIO_DDR_VTT_EN 203
56
57 #define SYSINFO_BOARD_NAME_MAX_LEN 37
58
59 const struct omap_sysinfo sysinfo = {
60 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
61 };
62
63 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
64 .sdram_config_init = 0x61851ab2,
65 .sdram_config = 0x61851ab2,
66 .sdram_config2 = 0x08000000,
67 .ref_ctrl = 0x000040F1,
68 .ref_ctrl_final = 0x00001035,
69 .sdram_tim1 = 0xCCCF36B3,
70 .sdram_tim2 = 0x308F7FDA,
71 .sdram_tim3 = 0x427F88A8,
72 .read_idle_ctrl = 0x00050000,
73 .zq_config = 0x0007190B,
74 .temp_alert_config = 0x00000000,
75 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
76 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
77 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
78 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
79 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
80 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
81 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
82 .emif_rd_wr_lvl_rmp_win = 0x00000000,
83 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
84 .emif_rd_wr_lvl_ctl = 0x00000000,
85 .emif_rd_wr_exec_thresh = 0x00000305
86 };
87
88 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
89 .sdram_config_init = 0x61851B32,
90 .sdram_config = 0x61851B32,
91 .sdram_config2 = 0x08000000,
92 .ref_ctrl = 0x000040F1,
93 .ref_ctrl_final = 0x00001035,
94 .sdram_tim1 = 0xCCCF36B3,
95 .sdram_tim2 = 0x308F7FDA,
96 .sdram_tim3 = 0x427F88A8,
97 .read_idle_ctrl = 0x00050000,
98 .zq_config = 0x0007190B,
99 .temp_alert_config = 0x00000000,
100 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
101 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
102 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
103 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
104 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
105 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
106 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
107 .emif_rd_wr_lvl_rmp_win = 0x00000000,
108 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
109 .emif_rd_wr_lvl_ctl = 0x00000000,
110 .emif_rd_wr_exec_thresh = 0x00000305
111 };
112
113 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
114 .sdram_config_init = 0x61862B32,
115 .sdram_config = 0x61862B32,
116 .sdram_config2 = 0x08000000,
117 .ref_ctrl = 0x0000514C,
118 .ref_ctrl_final = 0x0000144A,
119 .sdram_tim1 = 0xD113781C,
120 .sdram_tim2 = 0x30717FE3,
121 .sdram_tim3 = 0x409F86A8,
122 .read_idle_ctrl = 0x00050000,
123 .zq_config = 0x5007190B,
124 .temp_alert_config = 0x00000000,
125 .emif_ddr_phy_ctlr_1_init = 0x0024400D,
126 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
127 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
128 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
129 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
130 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
131 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
132 .emif_rd_wr_lvl_rmp_win = 0x00000000,
133 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
134 .emif_rd_wr_lvl_ctl = 0x00000000,
135 .emif_rd_wr_exec_thresh = 0x00000305
136 };
137
138 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
139 .sdram_config_init = 0x61862BB2,
140 .sdram_config = 0x61862BB2,
141 .sdram_config2 = 0x00000000,
142 .ref_ctrl = 0x0000514D,
143 .ref_ctrl_final = 0x0000144A,
144 .sdram_tim1 = 0xD1137824,
145 .sdram_tim2 = 0x30B37FE3,
146 .sdram_tim3 = 0x409F8AD8,
147 .read_idle_ctrl = 0x00050000,
148 .zq_config = 0x5007190B,
149 .temp_alert_config = 0x00000000,
150 .emif_ddr_phy_ctlr_1_init = 0x0824400E,
151 .emif_ddr_phy_ctlr_1 = 0x0E24400E,
152 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
153 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
154 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
155 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
156 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
157 .emif_rd_wr_lvl_rmp_win = 0x00000000,
158 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
159 .emif_rd_wr_lvl_ctl = 0x00000000,
160 .emif_rd_wr_exec_thresh = 0x00000305
161 };
162
163 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
164 .sdram_config_init = 0x61851ab2,
165 .sdram_config = 0x61851ab2,
166 .sdram_config2 = 0x08000000,
167 .ref_ctrl = 0x000040F1,
168 .ref_ctrl_final = 0x00001035,
169 .sdram_tim1 = 0xCCCF36B3,
170 .sdram_tim2 = 0x30BF7FDA,
171 .sdram_tim3 = 0x427F8BA8,
172 .read_idle_ctrl = 0x00050000,
173 .zq_config = 0x0007190B,
174 .temp_alert_config = 0x00000000,
175 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
176 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
177 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
178 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
179 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
180 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
181 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
182 .emif_rd_wr_lvl_rmp_win = 0x00000000,
183 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
184 .emif_rd_wr_lvl_ctl = 0x00000000,
185 .emif_rd_wr_exec_thresh = 0x00000305
186 };
187
188 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
189 .sdram_config_init = 0x61851B32,
190 .sdram_config = 0x61851B32,
191 .sdram_config2 = 0x08000000,
192 .ref_ctrl = 0x000040F1,
193 .ref_ctrl_final = 0x00001035,
194 .sdram_tim1 = 0xCCCF36B3,
195 .sdram_tim2 = 0x308F7FDA,
196 .sdram_tim3 = 0x427F88A8,
197 .read_idle_ctrl = 0x00050000,
198 .zq_config = 0x0007190B,
199 .temp_alert_config = 0x00000000,
200 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
201 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
202 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
203 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
204 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
205 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
206 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
207 .emif_rd_wr_lvl_rmp_win = 0x00000000,
208 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
209 .emif_rd_wr_lvl_ctl = 0x00000000,
210 .emif_rd_wr_exec_thresh = 0x00000305
211 };
212
213 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
214 .sdram_config_init = 0x61862B32,
215 .sdram_config = 0x61862B32,
216 .sdram_config2 = 0x00000000,
217 .ref_ctrl = 0x0000514C,
218 .ref_ctrl_final = 0x0000144A,
219 .sdram_tim1 = 0xD113783C,
220 .sdram_tim2 = 0x30B47FE3,
221 .sdram_tim3 = 0x409F8AD8,
222 .read_idle_ctrl = 0x00050000,
223 .zq_config = 0x5007190B,
224 .temp_alert_config = 0x00000000,
225 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
226 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
227 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
228 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
229 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
230 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
231 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
232 .emif_rd_wr_lvl_rmp_win = 0x00000000,
233 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
234 .emif_rd_wr_lvl_ctl = 0x00000000,
235 .emif_rd_wr_exec_thresh = 0x00000305
236 };
237
238 const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
239 .sdram_config_init = 0x61862B32,
240 .sdram_config = 0x61862B32,
241 .sdram_config2 = 0x00000000,
242 .ref_ctrl = 0x0000514C,
243 .ref_ctrl_final = 0x0000144A,
244 .sdram_tim1 = 0xD113781C,
245 .sdram_tim2 = 0x30B47FE3,
246 .sdram_tim3 = 0x409F8AD8,
247 .read_idle_ctrl = 0x00050000,
248 .zq_config = 0x5007190B,
249 .temp_alert_config = 0x00000000,
250 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
251 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
252 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
253 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
254 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
255 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
256 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
257 .emif_rd_wr_lvl_rmp_win = 0x00000000,
258 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
259 .emif_rd_wr_lvl_ctl = 0x00000000,
260 .emif_rd_wr_exec_thresh = 0x00000305
261 };
262
263 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
264 {
265 u64 ram_size;
266
267 ram_size = board_ti_get_emif_size();
268
269 switch (omap_revision()) {
270 case DRA752_ES1_0:
271 case DRA752_ES1_1:
272 case DRA752_ES2_0:
273 switch (emif_nr) {
274 case 1:
275 if (ram_size > CONFIG_MAX_MEM_MAPPED)
276 *regs = &emif1_ddr3_532_mhz_1cs_2G;
277 else
278 *regs = &emif1_ddr3_532_mhz_1cs;
279 break;
280 case 2:
281 if (ram_size > CONFIG_MAX_MEM_MAPPED)
282 *regs = &emif2_ddr3_532_mhz_1cs_2G;
283 else
284 *regs = &emif2_ddr3_532_mhz_1cs;
285 break;
286 }
287 break;
288 case DRA762_ABZ_ES1_0:
289 case DRA762_ACD_ES1_0:
290 case DRA762_ES1_0:
291 if (emif_nr == 1)
292 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
293 else
294 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
295 break;
296 case DRA722_ES1_0:
297 case DRA722_ES2_0:
298 case DRA722_ES2_1:
299 if (ram_size < CONFIG_MAX_MEM_MAPPED)
300 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
301 else
302 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
303 break;
304 default:
305 *regs = &emif1_ddr3_532_mhz_1cs;
306 }
307 }
308
309 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
310 .dmm_lisa_map_0 = 0x0,
311 .dmm_lisa_map_1 = 0x80640300,
312 .dmm_lisa_map_2 = 0xC0500220,
313 .dmm_lisa_map_3 = 0xFF020100,
314 .is_ma_present = 0x1
315 };
316
317 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
318 .dmm_lisa_map_0 = 0x0,
319 .dmm_lisa_map_1 = 0x0,
320 .dmm_lisa_map_2 = 0x80600100,
321 .dmm_lisa_map_3 = 0xFF020100,
322 .is_ma_present = 0x1
323 };
324
325 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
326 .dmm_lisa_map_0 = 0x0,
327 .dmm_lisa_map_1 = 0x0,
328 .dmm_lisa_map_2 = 0x80740300,
329 .dmm_lisa_map_3 = 0xFF020100,
330 .is_ma_present = 0x1
331 };
332
333 /*
334 * DRA722 EVM EMIF1 2GB CONFIGURATION
335 * EMIF1 4 devices of 512Mb x 8 Micron
336 */
337 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
338 .dmm_lisa_map_0 = 0x0,
339 .dmm_lisa_map_1 = 0x0,
340 .dmm_lisa_map_2 = 0x80700100,
341 .dmm_lisa_map_3 = 0xFF020100,
342 .is_ma_present = 0x1
343 };
344
345 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
346 {
347 u64 ram_size;
348
349 ram_size = board_ti_get_emif_size();
350
351 switch (omap_revision()) {
352 case DRA762_ABZ_ES1_0:
353 case DRA762_ACD_ES1_0:
354 case DRA762_ES1_0:
355 case DRA752_ES1_0:
356 case DRA752_ES1_1:
357 case DRA752_ES2_0:
358 if (ram_size > CONFIG_MAX_MEM_MAPPED)
359 *dmm_lisa_regs = &lisa_map_dra7_2GB;
360 else
361 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
362 break;
363 case DRA722_ES1_0:
364 case DRA722_ES2_0:
365 case DRA722_ES2_1:
366 default:
367 if (ram_size < CONFIG_MAX_MEM_MAPPED)
368 *dmm_lisa_regs = &lisa_map_2G_x_2;
369 else
370 *dmm_lisa_regs = &lisa_map_2G_x_4;
371 break;
372 }
373 }
374
375 struct vcores_data dra752_volts = {
376 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
377 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
378 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
379 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
380 .mpu.pmic = &tps659038,
381 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
382
383 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
384 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
385 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
386 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
387 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
388 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
389 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
390 .eve.addr = TPS659038_REG_ADDR_SMPS45,
391 .eve.pmic = &tps659038,
392 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
393
394 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
395 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
396 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
397 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
398 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
399 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
400 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
401 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
402 .gpu.pmic = &tps659038,
403 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
404
405 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
406 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
407 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
408 .core.addr = TPS659038_REG_ADDR_SMPS7,
409 .core.pmic = &tps659038,
410
411 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
412 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
413 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
414 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
415 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
416 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
417 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
418 .iva.addr = TPS659038_REG_ADDR_SMPS8,
419 .iva.pmic = &tps659038,
420 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
421 };
422
423 struct vcores_data dra76x_volts = {
424 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
425 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
426 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
427 .mpu.addr = LP87565_REG_ADDR_BUCK01,
428 .mpu.pmic = &lp87565,
429 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
430
431 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
432 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
433 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
434 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
435 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
436 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
437 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
438 .eve.addr = TPS65917_REG_ADDR_SMPS1,
439 .eve.pmic = &tps659038,
440 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
441
442 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
443 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
444 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
445 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
446 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
447 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
448 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
449 .gpu.addr = LP87565_REG_ADDR_BUCK23,
450 .gpu.pmic = &lp87565,
451 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
452
453 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
454 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
455 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
456 .core.addr = TPS65917_REG_ADDR_SMPS3,
457 .core.pmic = &tps659038,
458
459 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
460 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
461 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
462 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
463 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
464 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
465 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
466 .iva.addr = TPS65917_REG_ADDR_SMPS4,
467 .iva.pmic = &tps659038,
468 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
469 };
470
471 struct vcores_data dra722_volts = {
472 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
473 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
474 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
475 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
476 .mpu.pmic = &tps659038,
477 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
478
479 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
480 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
481 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
482 .core.addr = TPS65917_REG_ADDR_SMPS2,
483 .core.pmic = &tps659038,
484
485 /*
486 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
487 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
488 */
489 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
490 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
491 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
492 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
493 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
494 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
495 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
496 .gpu.addr = TPS65917_REG_ADDR_SMPS3,
497 .gpu.pmic = &tps659038,
498 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
499
500 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
501 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
502 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
503 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
504 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
505 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
506 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
507 .eve.addr = TPS65917_REG_ADDR_SMPS3,
508 .eve.pmic = &tps659038,
509 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
510
511 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
512 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
513 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
514 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
515 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
516 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
517 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
518 .iva.addr = TPS65917_REG_ADDR_SMPS3,
519 .iva.pmic = &tps659038,
520 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
521 };
522
523 struct vcores_data dra718_volts = {
524 /*
525 * In the case of dra71x GPU MPU and CORE
526 * are all powered up by BUCK0 of LP873X PMIC
527 */
528 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
529 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
530 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
531 .mpu.addr = LP873X_REG_ADDR_BUCK0,
532 .mpu.pmic = &lp8733,
533 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
534
535 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
536 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
537 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
538 .core.addr = LP873X_REG_ADDR_BUCK0,
539 .core.pmic = &lp8733,
540
541 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
542 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
543 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
544 .gpu.addr = LP873X_REG_ADDR_BUCK0,
545 .gpu.pmic = &lp8733,
546 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
547
548 /*
549 * The DSPEVE and IVA rails are grouped on DRA71x-evm
550 * and are powered by BUCK1 of LP873X PMIC
551 */
552 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
553 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
554 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
555 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
556 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
557 .eve.addr = LP873X_REG_ADDR_BUCK1,
558 .eve.pmic = &lp8733,
559 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
560
561 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
562 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
563 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
564 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
565 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
566 .iva.addr = LP873X_REG_ADDR_BUCK1,
567 .iva.pmic = &lp8733,
568 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
569 };
570
571 int get_voltrail_opp(int rail_offset)
572 {
573 int opp;
574
575 switch (rail_offset) {
576 case VOLT_MPU:
577 opp = DRA7_MPU_OPP;
578 /* DRA71x supports only OPP_NOM for MPU */
579 if (board_is_dra71x_evm())
580 opp = OPP_NOM;
581 break;
582 case VOLT_CORE:
583 opp = DRA7_CORE_OPP;
584 /* DRA71x supports only OPP_NOM for CORE */
585 if (board_is_dra71x_evm())
586 opp = OPP_NOM;
587 break;
588 case VOLT_GPU:
589 opp = DRA7_GPU_OPP;
590 /* DRA71x supports only OPP_NOM for GPU */
591 if (board_is_dra71x_evm())
592 opp = OPP_NOM;
593 break;
594 case VOLT_EVE:
595 opp = DRA7_DSPEVE_OPP;
596 /*
597 * DRA71x does not support OPP_OD for EVE.
598 * If OPP_OD is selected by menuconfig, fallback
599 * to OPP_NOM.
600 */
601 if (board_is_dra71x_evm() && opp == OPP_OD)
602 opp = OPP_NOM;
603 break;
604 case VOLT_IVA:
605 opp = DRA7_IVA_OPP;
606 /*
607 * DRA71x does not support OPP_OD for IVA.
608 * If OPP_OD is selected by menuconfig, fallback
609 * to OPP_NOM.
610 */
611 if (board_is_dra71x_evm() && opp == OPP_OD)
612 opp = OPP_NOM;
613 break;
614 default:
615 opp = OPP_NOM;
616 }
617
618 return opp;
619 }
620
621 /**
622 * @brief board_init
623 *
624 * @return 0
625 */
626 int board_init(void)
627 {
628 gpmc_init();
629 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
630
631 return 0;
632 }
633
634 int dram_init_banksize(void)
635 {
636 u64 ram_size;
637
638 ram_size = board_ti_get_emif_size();
639
640 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
641 gd->bd->bi_dram[0].size = get_effective_memsize();
642 if (ram_size > CONFIG_MAX_MEM_MAPPED) {
643 gd->bd->bi_dram[1].start = 0x200000000;
644 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
645 }
646
647 return 0;
648 }
649
650 int board_late_init(void)
651 {
652 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
653 char *name = "unknown";
654
655 if (is_dra72x()) {
656 if (board_is_dra72x_revc_or_later())
657 name = "dra72x-revc";
658 else if (board_is_dra71x_evm())
659 name = "dra71x";
660 else
661 name = "dra72x";
662 } else if (is_dra76x_abz()) {
663 name = "dra76x_abz";
664 } else if (is_dra76x_acd()) {
665 name = "dra76x_acd";
666 } else {
667 name = "dra7xx";
668 }
669
670 set_board_info_env(name);
671
672 /*
673 * Default FIT boot on HS devices. Non FIT images are not allowed
674 * on HS devices.
675 */
676 if (get_device_type() == HS_DEVICE)
677 env_set("boot_fit", "1");
678
679 omap_die_id_serial();
680 omap_set_fastboot_vars();
681
682 /*
683 * Hook the LDO1 regulator to EN pin. This applies only to LP8733
684 * Rest all regulators are hooked to EN Pin at reset.
685 */
686 if (board_is_dra71x_evm())
687 palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
688 #endif
689 return 0;
690 }
691
692 #ifdef CONFIG_SPL_BUILD
693 void do_board_detect(void)
694 {
695 int rc;
696
697 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
698 CONFIG_EEPROM_CHIP_ADDRESS);
699 if (rc)
700 printf("ti_i2c_eeprom_init failed %d\n", rc);
701 }
702
703 #else
704
705 void do_board_detect(void)
706 {
707 char *bname = NULL;
708 int rc;
709
710 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
711 CONFIG_EEPROM_CHIP_ADDRESS);
712 if (rc)
713 printf("ti_i2c_eeprom_init failed %d\n", rc);
714
715 if (board_is_dra74x_evm()) {
716 bname = "DRA74x EVM";
717 } else if (board_is_dra72x_evm()) {
718 bname = "DRA72x EVM";
719 } else if (board_is_dra71x_evm()) {
720 bname = "DRA71x EVM";
721 } else if (board_is_dra76x_evm()) {
722 bname = "DRA76x EVM";
723 } else {
724 /* If EEPROM is not populated */
725 if (is_dra72x())
726 bname = "DRA72x EVM";
727 else
728 bname = "DRA74x EVM";
729 }
730
731 if (bname)
732 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
733 "Board: %s REV %s\n", bname, board_ti_get_rev());
734 }
735 #endif /* CONFIG_SPL_BUILD */
736
737 void vcores_init(void)
738 {
739 if (board_is_dra74x_evm()) {
740 *omap_vcores = &dra752_volts;
741 } else if (board_is_dra72x_evm()) {
742 *omap_vcores = &dra722_volts;
743 } else if (board_is_dra71x_evm()) {
744 *omap_vcores = &dra718_volts;
745 } else if (board_is_dra76x_evm()) {
746 *omap_vcores = &dra76x_volts;
747 } else {
748 /* If EEPROM is not populated */
749 if (is_dra72x())
750 *omap_vcores = &dra722_volts;
751 else
752 *omap_vcores = &dra752_volts;
753 }
754 }
755
756 void set_muxconf_regs(void)
757 {
758 do_set_mux32((*ctrl)->control_padconf_core_base,
759 early_padconf, ARRAY_SIZE(early_padconf));
760 }
761
762 #ifdef CONFIG_IODELAY_RECALIBRATION
763 void recalibrate_iodelay(void)
764 {
765 struct pad_conf_entry const *pads, *delta_pads = NULL;
766 struct iodelay_cfg_entry const *iodelay;
767 int npads, niodelays, delta_npads = 0;
768 int ret;
769
770 switch (omap_revision()) {
771 case DRA722_ES1_0:
772 case DRA722_ES2_0:
773 case DRA722_ES2_1:
774 pads = dra72x_core_padconf_array_common;
775 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
776 if (board_is_dra71x_evm()) {
777 pads = dra71x_core_padconf_array;
778 npads = ARRAY_SIZE(dra71x_core_padconf_array);
779 iodelay = dra71_iodelay_cfg_array;
780 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
781 } else if (board_is_dra72x_revc_or_later()) {
782 delta_pads = dra72x_rgmii_padconf_array_revc;
783 delta_npads =
784 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
785 iodelay = dra72_iodelay_cfg_array_revc;
786 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
787 } else {
788 delta_pads = dra72x_rgmii_padconf_array_revb;
789 delta_npads =
790 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
791 iodelay = dra72_iodelay_cfg_array_revb;
792 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
793 }
794 break;
795 case DRA752_ES1_0:
796 case DRA752_ES1_1:
797 pads = dra74x_core_padconf_array;
798 npads = ARRAY_SIZE(dra74x_core_padconf_array);
799 iodelay = dra742_es1_1_iodelay_cfg_array;
800 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
801 break;
802 case DRA762_ACD_ES1_0:
803 case DRA762_ES1_0:
804 pads = dra76x_core_padconf_array;
805 npads = ARRAY_SIZE(dra76x_core_padconf_array);
806 iodelay = dra76x_es1_0_iodelay_cfg_array;
807 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
808 break;
809 default:
810 case DRA752_ES2_0:
811 case DRA762_ABZ_ES1_0:
812 pads = dra74x_core_padconf_array;
813 npads = ARRAY_SIZE(dra74x_core_padconf_array);
814 iodelay = dra742_es2_0_iodelay_cfg_array;
815 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
816 /* Setup port1 and port2 for rgmii with 'no-id' mode */
817 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
818 RGMII1_ID_MODE_N_MASK);
819 break;
820 }
821 /* Setup I/O isolation */
822 ret = __recalibrate_iodelay_start();
823 if (ret)
824 goto err;
825
826 /* Do the muxing here */
827 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
828
829 /* Now do the weird minor deltas that should be safe */
830 if (delta_npads)
831 do_set_mux32((*ctrl)->control_padconf_core_base,
832 delta_pads, delta_npads);
833
834 if (is_dra76x())
835 /* Set mux for MCAN instead of DCAN1 */
836 clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
837 MCAN_SEL_ALT_MASK, MCAN_SEL);
838
839 /* Setup IOdelay configuration */
840 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
841 err:
842 /* Closeup.. remove isolation */
843 __recalibrate_iodelay_end(ret);
844 }
845 #endif
846
847 #if defined(CONFIG_MMC)
848 int board_mmc_init(bd_t *bis)
849 {
850 omap_mmc_init(0, 0, 0, -1, -1);
851 omap_mmc_init(1, 0, 0, -1, -1);
852 return 0;
853 }
854
855 void board_mmc_poweron_ldo(uint voltage)
856 {
857 if (board_is_dra71x_evm()) {
858 if (voltage == LDO_VOLT_3V0)
859 voltage = 0x19;
860 else if (voltage == LDO_VOLT_1V8)
861 voltage = 0xa;
862 lp873x_mmc1_poweron_ldo(voltage);
863 } else if (board_is_dra76x_evm()) {
864 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
865 } else {
866 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
867 }
868 }
869
870 static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
871 .hw_rev = "rev11",
872 .unsupported_caps = MMC_CAP(MMC_HS_200) |
873 MMC_CAP(UHS_SDR104),
874 .max_freq = 96000000,
875 };
876
877 static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
878 .hw_rev = "rev11",
879 .unsupported_caps = MMC_CAP(MMC_HS_200) |
880 MMC_CAP(UHS_SDR104) |
881 MMC_CAP(UHS_SDR50),
882 .max_freq = 48000000,
883 };
884
885 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
886 {
887 switch (omap_revision()) {
888 case DRA752_ES1_0:
889 case DRA752_ES1_1:
890 if (addr == OMAP_HSMMC1_BASE)
891 return &dra7x_es1_1_mmc1_fixups;
892 else
893 return &dra7x_es1_1_mmc23_fixups;
894 default:
895 return NULL;
896 }
897 }
898 #endif
899
900 #ifdef CONFIG_USB_DWC3
901 static struct dwc3_device usb_otg_ss1 = {
902 .maximum_speed = USB_SPEED_SUPER,
903 .base = DRA7_USB_OTG_SS1_BASE,
904 .tx_fifo_resize = false,
905 .index = 0,
906 };
907
908 static struct dwc3_omap_device usb_otg_ss1_glue = {
909 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
910 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
911 .index = 0,
912 };
913
914 static struct ti_usb_phy_device usb_phy1_device = {
915 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
916 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
917 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
918 .index = 0,
919 };
920
921 static struct dwc3_device usb_otg_ss2 = {
922 .maximum_speed = USB_SPEED_SUPER,
923 .base = DRA7_USB_OTG_SS2_BASE,
924 .tx_fifo_resize = false,
925 .index = 1,
926 };
927
928 static struct dwc3_omap_device usb_otg_ss2_glue = {
929 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
930 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
931 .index = 1,
932 };
933
934 static struct ti_usb_phy_device usb_phy2_device = {
935 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
936 .index = 1,
937 };
938
939 int board_usb_init(int index, enum usb_init_type init)
940 {
941 enable_usb_clocks(index);
942 switch (index) {
943 case 0:
944 if (init == USB_INIT_DEVICE) {
945 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
946 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
947 } else {
948 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
949 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
950 }
951
952 ti_usb_phy_uboot_init(&usb_phy1_device);
953 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
954 dwc3_uboot_init(&usb_otg_ss1);
955 break;
956 case 1:
957 if (init == USB_INIT_DEVICE) {
958 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
959 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
960 } else {
961 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
962 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
963 }
964
965 ti_usb_phy_uboot_init(&usb_phy2_device);
966 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
967 dwc3_uboot_init(&usb_otg_ss2);
968 break;
969 default:
970 printf("Invalid Controller Index\n");
971 }
972
973 return 0;
974 }
975
976 int board_usb_cleanup(int index, enum usb_init_type init)
977 {
978 switch (index) {
979 case 0:
980 case 1:
981 ti_usb_phy_uboot_exit(index);
982 dwc3_uboot_exit(index);
983 dwc3_omap_uboot_exit(index);
984 break;
985 default:
986 printf("Invalid Controller Index\n");
987 }
988 disable_usb_clocks(index);
989 return 0;
990 }
991
992 int usb_gadget_handle_interrupts(int index)
993 {
994 u32 status;
995
996 status = dwc3_omap_uboot_interrupt_status(index);
997 if (status)
998 dwc3_uboot_handle_interrupt(index);
999
1000 return 0;
1001 }
1002 #endif
1003
1004 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
1005 int spl_start_uboot(void)
1006 {
1007 /* break into full u-boot on 'c' */
1008 if (serial_tstc() && serial_getc() == 'c')
1009 return 1;
1010
1011 #ifdef CONFIG_SPL_ENV_SUPPORT
1012 env_init();
1013 env_load();
1014 if (env_get_yesno("boot_os") != 1)
1015 return 1;
1016 #endif
1017
1018 return 0;
1019 }
1020 #endif
1021
1022 #ifdef CONFIG_DRIVER_TI_CPSW
1023 extern u32 *const omap_si_rev;
1024
1025 static void cpsw_control(int enabled)
1026 {
1027 /* VTP can be added here */
1028
1029 return;
1030 }
1031
1032 static struct cpsw_slave_data cpsw_slaves[] = {
1033 {
1034 .slave_reg_ofs = 0x208,
1035 .sliver_reg_ofs = 0xd80,
1036 .phy_addr = 2,
1037 },
1038 {
1039 .slave_reg_ofs = 0x308,
1040 .sliver_reg_ofs = 0xdc0,
1041 .phy_addr = 3,
1042 },
1043 };
1044
1045 static struct cpsw_platform_data cpsw_data = {
1046 .mdio_base = CPSW_MDIO_BASE,
1047 .cpsw_base = CPSW_BASE,
1048 .mdio_div = 0xff,
1049 .channels = 8,
1050 .cpdma_reg_ofs = 0x800,
1051 .slaves = 2,
1052 .slave_data = cpsw_slaves,
1053 .ale_reg_ofs = 0xd00,
1054 .ale_entries = 1024,
1055 .host_port_reg_ofs = 0x108,
1056 .hw_stats_reg_ofs = 0x900,
1057 .bd_ram_ofs = 0x2000,
1058 .mac_control = (1 << 5),
1059 .control = cpsw_control,
1060 .host_port_num = 0,
1061 .version = CPSW_CTRL_VERSION_2,
1062 };
1063
1064 int board_eth_init(bd_t *bis)
1065 {
1066 int ret;
1067 uint8_t mac_addr[6];
1068 uint32_t mac_hi, mac_lo;
1069 uint32_t ctrl_val;
1070
1071 /* try reading mac address from efuse */
1072 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
1073 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
1074 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1075 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1076 mac_addr[2] = mac_hi & 0xFF;
1077 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1078 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1079 mac_addr[5] = mac_lo & 0xFF;
1080
1081 if (!env_get("ethaddr")) {
1082 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1083
1084 if (is_valid_ethaddr(mac_addr))
1085 eth_env_set_enetaddr("ethaddr", mac_addr);
1086 }
1087
1088 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
1089 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
1090 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
1091 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1092 mac_addr[2] = mac_hi & 0xFF;
1093 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
1094 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
1095 mac_addr[5] = mac_lo & 0xFF;
1096
1097 if (!env_get("eth1addr")) {
1098 if (is_valid_ethaddr(mac_addr))
1099 eth_env_set_enetaddr("eth1addr", mac_addr);
1100 }
1101
1102 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1103 ctrl_val |= 0x22;
1104 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1105
1106 if (*omap_si_rev == DRA722_ES1_0)
1107 cpsw_data.active_slave = 1;
1108
1109 if (board_is_dra72x_revc_or_later()) {
1110 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
1111 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
1112 }
1113
1114 ret = cpsw_register(&cpsw_data);
1115 if (ret < 0)
1116 printf("Error %d registering CPSW switch\n", ret);
1117
1118 return ret;
1119 }
1120 #endif
1121
1122 #ifdef CONFIG_BOARD_EARLY_INIT_F
1123 /* VTT regulator enable */
1124 static inline void vtt_regulator_enable(void)
1125 {
1126 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1127 return;
1128
1129 /* Do not enable VTT for DRA722 or DRA76x */
1130 if (is_dra72x() || is_dra76x())
1131 return;
1132
1133 /*
1134 * EVM Rev G and later use gpio7_11 for DDR3 termination.
1135 * This is safe enough to do on older revs.
1136 */
1137 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1138 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1139 }
1140
1141 int board_early_init_f(void)
1142 {
1143 vtt_regulator_enable();
1144 return 0;
1145 }
1146 #endif
1147
1148 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1149 int ft_board_setup(void *blob, bd_t *bd)
1150 {
1151 ft_cpu_setup(blob, bd);
1152
1153 return 0;
1154 }
1155 #endif
1156
1157 #ifdef CONFIG_SPL_LOAD_FIT
1158 int board_fit_config_name_match(const char *name)
1159 {
1160 if (is_dra72x()) {
1161 if (board_is_dra71x_evm()) {
1162 if (!strcmp(name, "dra71-evm"))
1163 return 0;
1164 }else if(board_is_dra72x_revc_or_later()) {
1165 if (!strcmp(name, "dra72-evm-revc"))
1166 return 0;
1167 } else if (!strcmp(name, "dra72-evm")) {
1168 return 0;
1169 }
1170 } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
1171 return 0;
1172 } else if (!is_dra72x() && !is_dra76x_acd() &&
1173 !strcmp(name, "dra7-evm")) {
1174 return 0;
1175 }
1176
1177 return -1;
1178 }
1179 #endif
1180
1181 #ifdef CONFIG_TI_SECURE_DEVICE
1182 void board_fit_image_post_process(void **p_image, size_t *p_size)
1183 {
1184 secure_boot_verify_image(p_image, p_size);
1185 }
1186
1187 void board_tee_image_process(ulong tee_image, size_t tee_size)
1188 {
1189 secure_tee_install((u32)tee_image);
1190 }
1191
1192 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1193 #endif
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