3 * Texas Instruments Incorporated, <www.ti.com>
5 * Lokesh Vutla <lokeshvutla@ti.com>
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/string.h>
19 #include <linux/usb/gadget.h>
20 #include <asm/omap_common.h>
21 #include <asm/omap_sec_common.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/dra7xx_iodelay.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/sata.h>
28 #include <environment.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
35 #include "../common/board_detect.h"
37 #define board_is_dra76x_evm() board_ti_is("DRA76/7x")
38 #define board_is_dra74x_evm() board_ti_is("5777xCPU")
39 #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
40 #define board_is_dra71x_evm() board_ti_is("DRA79x,D")
41 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
42 (strncmp("H", board_ti_get_rev(), 1) <= 0))
43 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
44 (strncmp("C", board_ti_get_rev(), 1) <= 0))
45 #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
46 board_ti_get_emif2_size()
48 #ifdef CONFIG_DRIVER_TI_CPSW
52 DECLARE_GLOBAL_DATA_PTR
;
55 #define GPIO_DDR_VTT_EN 203
57 #define SYSINFO_BOARD_NAME_MAX_LEN 37
59 const struct omap_sysinfo sysinfo
= {
60 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
63 static const struct emif_regs emif1_ddr3_532_mhz_1cs
= {
64 .sdram_config_init
= 0x61851ab2,
65 .sdram_config
= 0x61851ab2,
66 .sdram_config2
= 0x08000000,
67 .ref_ctrl
= 0x000040F1,
68 .ref_ctrl_final
= 0x00001035,
69 .sdram_tim1
= 0xCCCF36B3,
70 .sdram_tim2
= 0x308F7FDA,
71 .sdram_tim3
= 0x427F88A8,
72 .read_idle_ctrl
= 0x00050000,
73 .zq_config
= 0x0007190B,
74 .temp_alert_config
= 0x00000000,
75 .emif_ddr_phy_ctlr_1_init
= 0x0024400B,
76 .emif_ddr_phy_ctlr_1
= 0x0E24400B,
77 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
78 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
79 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
80 .emif_ddr_ext_phy_ctrl_4
= 0x009B009B,
81 .emif_ddr_ext_phy_ctrl_5
= 0x009E009E,
82 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
83 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
84 .emif_rd_wr_lvl_ctl
= 0x00000000,
85 .emif_rd_wr_exec_thresh
= 0x00000305
88 static const struct emif_regs emif2_ddr3_532_mhz_1cs
= {
89 .sdram_config_init
= 0x61851B32,
90 .sdram_config
= 0x61851B32,
91 .sdram_config2
= 0x08000000,
92 .ref_ctrl
= 0x000040F1,
93 .ref_ctrl_final
= 0x00001035,
94 .sdram_tim1
= 0xCCCF36B3,
95 .sdram_tim2
= 0x308F7FDA,
96 .sdram_tim3
= 0x427F88A8,
97 .read_idle_ctrl
= 0x00050000,
98 .zq_config
= 0x0007190B,
99 .temp_alert_config
= 0x00000000,
100 .emif_ddr_phy_ctlr_1_init
= 0x0024400B,
101 .emif_ddr_phy_ctlr_1
= 0x0E24400B,
102 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
103 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
104 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
105 .emif_ddr_ext_phy_ctrl_4
= 0x009B009B,
106 .emif_ddr_ext_phy_ctrl_5
= 0x009E009E,
107 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
108 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
109 .emif_rd_wr_lvl_ctl
= 0x00000000,
110 .emif_rd_wr_exec_thresh
= 0x00000305
113 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1
= {
114 .sdram_config_init
= 0x61862B32,
115 .sdram_config
= 0x61862B32,
116 .sdram_config2
= 0x08000000,
117 .ref_ctrl
= 0x0000514C,
118 .ref_ctrl_final
= 0x0000144A,
119 .sdram_tim1
= 0xD113781C,
120 .sdram_tim2
= 0x30717FE3,
121 .sdram_tim3
= 0x409F86A8,
122 .read_idle_ctrl
= 0x00050000,
123 .zq_config
= 0x5007190B,
124 .temp_alert_config
= 0x00000000,
125 .emif_ddr_phy_ctlr_1_init
= 0x0024400D,
126 .emif_ddr_phy_ctlr_1
= 0x0E24400D,
127 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
128 .emif_ddr_ext_phy_ctrl_2
= 0x00A400A4,
129 .emif_ddr_ext_phy_ctrl_3
= 0x00A900A9,
130 .emif_ddr_ext_phy_ctrl_4
= 0x00B000B0,
131 .emif_ddr_ext_phy_ctrl_5
= 0x00B000B0,
132 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
133 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
134 .emif_rd_wr_lvl_ctl
= 0x00000000,
135 .emif_rd_wr_exec_thresh
= 0x00000305
138 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2
= {
139 .sdram_config_init
= 0x61862BB2,
140 .sdram_config
= 0x61862BB2,
141 .sdram_config2
= 0x00000000,
142 .ref_ctrl
= 0x0000514D,
143 .ref_ctrl_final
= 0x0000144A,
144 .sdram_tim1
= 0xD1137824,
145 .sdram_tim2
= 0x30B37FE3,
146 .sdram_tim3
= 0x409F8AD8,
147 .read_idle_ctrl
= 0x00050000,
148 .zq_config
= 0x5007190B,
149 .temp_alert_config
= 0x00000000,
150 .emif_ddr_phy_ctlr_1_init
= 0x0824400E,
151 .emif_ddr_phy_ctlr_1
= 0x0E24400E,
152 .emif_ddr_ext_phy_ctrl_1
= 0x04040100,
153 .emif_ddr_ext_phy_ctrl_2
= 0x006B009F,
154 .emif_ddr_ext_phy_ctrl_3
= 0x006B00A2,
155 .emif_ddr_ext_phy_ctrl_4
= 0x006B00A8,
156 .emif_ddr_ext_phy_ctrl_5
= 0x006B00A8,
157 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
158 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
159 .emif_rd_wr_lvl_ctl
= 0x00000000,
160 .emif_rd_wr_exec_thresh
= 0x00000305
163 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G
= {
164 .sdram_config_init
= 0x61851ab2,
165 .sdram_config
= 0x61851ab2,
166 .sdram_config2
= 0x08000000,
167 .ref_ctrl
= 0x000040F1,
168 .ref_ctrl_final
= 0x00001035,
169 .sdram_tim1
= 0xCCCF36B3,
170 .sdram_tim2
= 0x30BF7FDA,
171 .sdram_tim3
= 0x427F8BA8,
172 .read_idle_ctrl
= 0x00050000,
173 .zq_config
= 0x0007190B,
174 .temp_alert_config
= 0x00000000,
175 .emif_ddr_phy_ctlr_1_init
= 0x0024400B,
176 .emif_ddr_phy_ctlr_1
= 0x0E24400B,
177 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
178 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
179 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
180 .emif_ddr_ext_phy_ctrl_4
= 0x009B009B,
181 .emif_ddr_ext_phy_ctrl_5
= 0x009E009E,
182 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
183 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
184 .emif_rd_wr_lvl_ctl
= 0x00000000,
185 .emif_rd_wr_exec_thresh
= 0x00000305
188 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G
= {
189 .sdram_config_init
= 0x61851B32,
190 .sdram_config
= 0x61851B32,
191 .sdram_config2
= 0x08000000,
192 .ref_ctrl
= 0x000040F1,
193 .ref_ctrl_final
= 0x00001035,
194 .sdram_tim1
= 0xCCCF36B3,
195 .sdram_tim2
= 0x308F7FDA,
196 .sdram_tim3
= 0x427F88A8,
197 .read_idle_ctrl
= 0x00050000,
198 .zq_config
= 0x0007190B,
199 .temp_alert_config
= 0x00000000,
200 .emif_ddr_phy_ctlr_1_init
= 0x0024400B,
201 .emif_ddr_phy_ctlr_1
= 0x0E24400B,
202 .emif_ddr_ext_phy_ctrl_1
= 0x10040100,
203 .emif_ddr_ext_phy_ctrl_2
= 0x00910091,
204 .emif_ddr_ext_phy_ctrl_3
= 0x00950095,
205 .emif_ddr_ext_phy_ctrl_4
= 0x009B009B,
206 .emif_ddr_ext_phy_ctrl_5
= 0x009E009E,
207 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
208 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
209 .emif_rd_wr_lvl_ctl
= 0x00000000,
210 .emif_rd_wr_exec_thresh
= 0x00000305
213 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76
= {
214 .sdram_config_init
= 0x61862B32,
215 .sdram_config
= 0x61862B32,
216 .sdram_config2
= 0x00000000,
217 .ref_ctrl
= 0x0000514C,
218 .ref_ctrl_final
= 0x0000144A,
219 .sdram_tim1
= 0xD113783C,
220 .sdram_tim2
= 0x30B47FE3,
221 .sdram_tim3
= 0x409F8AD8,
222 .read_idle_ctrl
= 0x00050000,
223 .zq_config
= 0x5007190B,
224 .temp_alert_config
= 0x00000000,
225 .emif_ddr_phy_ctlr_1_init
= 0x0824400D,
226 .emif_ddr_phy_ctlr_1
= 0x0E24400D,
227 .emif_ddr_ext_phy_ctrl_1
= 0x04040100,
228 .emif_ddr_ext_phy_ctrl_2
= 0x006B009F,
229 .emif_ddr_ext_phy_ctrl_3
= 0x006B00A2,
230 .emif_ddr_ext_phy_ctrl_4
= 0x006B00A8,
231 .emif_ddr_ext_phy_ctrl_5
= 0x006B00A8,
232 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
233 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
234 .emif_rd_wr_lvl_ctl
= 0x00000000,
235 .emif_rd_wr_exec_thresh
= 0x00000305
238 const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76
= {
239 .sdram_config_init
= 0x61862B32,
240 .sdram_config
= 0x61862B32,
241 .sdram_config2
= 0x00000000,
242 .ref_ctrl
= 0x0000514C,
243 .ref_ctrl_final
= 0x0000144A,
244 .sdram_tim1
= 0xD113781C,
245 .sdram_tim2
= 0x30B47FE3,
246 .sdram_tim3
= 0x409F8AD8,
247 .read_idle_ctrl
= 0x00050000,
248 .zq_config
= 0x5007190B,
249 .temp_alert_config
= 0x00000000,
250 .emif_ddr_phy_ctlr_1_init
= 0x0824400D,
251 .emif_ddr_phy_ctlr_1
= 0x0E24400D,
252 .emif_ddr_ext_phy_ctrl_1
= 0x04040100,
253 .emif_ddr_ext_phy_ctrl_2
= 0x006B009F,
254 .emif_ddr_ext_phy_ctrl_3
= 0x006B00A2,
255 .emif_ddr_ext_phy_ctrl_4
= 0x006B00A8,
256 .emif_ddr_ext_phy_ctrl_5
= 0x006B00A8,
257 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
258 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
259 .emif_rd_wr_lvl_ctl
= 0x00000000,
260 .emif_rd_wr_exec_thresh
= 0x00000305
263 void emif_get_reg_dump(u32 emif_nr
, const struct emif_regs
**regs
)
267 ram_size
= board_ti_get_emif_size();
269 switch (omap_revision()) {
275 if (ram_size
> CONFIG_MAX_MEM_MAPPED
)
276 *regs
= &emif1_ddr3_532_mhz_1cs_2G
;
278 *regs
= &emif1_ddr3_532_mhz_1cs
;
281 if (ram_size
> CONFIG_MAX_MEM_MAPPED
)
282 *regs
= &emif2_ddr3_532_mhz_1cs_2G
;
284 *regs
= &emif2_ddr3_532_mhz_1cs
;
290 *regs
= &emif_1_regs_ddr3_666_mhz_1cs_dra76
;
292 *regs
= &emif_2_regs_ddr3_666_mhz_1cs_dra76
;
297 if (ram_size
< CONFIG_MAX_MEM_MAPPED
)
298 *regs
= &emif_1_regs_ddr3_666_mhz_1cs_dra_es1
;
300 *regs
= &emif_1_regs_ddr3_666_mhz_1cs_dra_es2
;
303 *regs
= &emif1_ddr3_532_mhz_1cs
;
307 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB
= {
308 .dmm_lisa_map_0
= 0x0,
309 .dmm_lisa_map_1
= 0x80640300,
310 .dmm_lisa_map_2
= 0xC0500220,
311 .dmm_lisa_map_3
= 0xFF020100,
315 static const struct dmm_lisa_map_regs lisa_map_2G_x_2
= {
316 .dmm_lisa_map_0
= 0x0,
317 .dmm_lisa_map_1
= 0x0,
318 .dmm_lisa_map_2
= 0x80600100,
319 .dmm_lisa_map_3
= 0xFF020100,
323 const struct dmm_lisa_map_regs lisa_map_dra7_2GB
= {
324 .dmm_lisa_map_0
= 0x0,
325 .dmm_lisa_map_1
= 0x0,
326 .dmm_lisa_map_2
= 0x80740300,
327 .dmm_lisa_map_3
= 0xFF020100,
332 * DRA722 EVM EMIF1 2GB CONFIGURATION
333 * EMIF1 4 devices of 512Mb x 8 Micron
335 const struct dmm_lisa_map_regs lisa_map_2G_x_4
= {
336 .dmm_lisa_map_0
= 0x0,
337 .dmm_lisa_map_1
= 0x0,
338 .dmm_lisa_map_2
= 0x80700100,
339 .dmm_lisa_map_3
= 0xFF020100,
343 void emif_get_dmm_regs(const struct dmm_lisa_map_regs
**dmm_lisa_regs
)
347 ram_size
= board_ti_get_emif_size();
349 switch (omap_revision()) {
354 if (ram_size
> CONFIG_MAX_MEM_MAPPED
)
355 *dmm_lisa_regs
= &lisa_map_dra7_2GB
;
357 *dmm_lisa_regs
= &lisa_map_dra7_1536MB
;
363 if (ram_size
< CONFIG_MAX_MEM_MAPPED
)
364 *dmm_lisa_regs
= &lisa_map_2G_x_2
;
366 *dmm_lisa_regs
= &lisa_map_2G_x_4
;
371 struct vcores_data dra752_volts
= {
372 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
373 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
374 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
375 .mpu
.addr
= TPS659038_REG_ADDR_SMPS12
,
376 .mpu
.pmic
= &tps659038
,
377 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
379 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
380 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
381 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
382 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
383 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
384 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
385 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
386 .eve
.addr
= TPS659038_REG_ADDR_SMPS45
,
387 .eve
.pmic
= &tps659038
,
388 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
390 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
391 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
392 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
393 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
394 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
395 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
396 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
397 .gpu
.addr
= TPS659038_REG_ADDR_SMPS6
,
398 .gpu
.pmic
= &tps659038
,
399 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
401 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
402 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
403 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
404 .core
.addr
= TPS659038_REG_ADDR_SMPS7
,
405 .core
.pmic
= &tps659038
,
407 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
408 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
409 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
410 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
411 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
412 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
413 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
414 .iva
.addr
= TPS659038_REG_ADDR_SMPS8
,
415 .iva
.pmic
= &tps659038
,
416 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
419 struct vcores_data dra76x_volts
= {
420 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
421 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
422 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
423 .mpu
.addr
= LP87565_REG_ADDR_BUCK01
,
424 .mpu
.pmic
= &lp87565
,
425 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
427 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
428 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
429 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
430 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
431 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
432 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
433 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
434 .eve
.addr
= TPS65917_REG_ADDR_SMPS1
,
435 .eve
.pmic
= &tps659038
,
436 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
438 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
439 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
440 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
441 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
442 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
443 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
444 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
445 .gpu
.addr
= LP87565_REG_ADDR_BUCK23
,
446 .gpu
.pmic
= &lp87565
,
447 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
449 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
450 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
451 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
452 .core
.addr
= TPS65917_REG_ADDR_SMPS3
,
453 .core
.pmic
= &tps659038
,
455 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
456 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
457 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
458 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
459 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
460 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
461 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
462 .iva
.addr
= TPS65917_REG_ADDR_SMPS4
,
463 .iva
.pmic
= &tps659038
,
464 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
467 struct vcores_data dra722_volts
= {
468 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
469 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
470 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
471 .mpu
.addr
= TPS65917_REG_ADDR_SMPS1
,
472 .mpu
.pmic
= &tps659038
,
473 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
475 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
476 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
477 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
478 .core
.addr
= TPS65917_REG_ADDR_SMPS2
,
479 .core
.pmic
= &tps659038
,
482 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
483 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
485 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
486 .gpu
.value
[OPP_OD
] = VDD_GPU_DRA7_OD
,
487 .gpu
.value
[OPP_HIGH
] = VDD_GPU_DRA7_HIGH
,
488 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
489 .gpu
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_GPU_OD
,
490 .gpu
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_GPU_HIGH
,
491 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
492 .gpu
.addr
= TPS65917_REG_ADDR_SMPS3
,
493 .gpu
.pmic
= &tps659038
,
494 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
496 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
497 .eve
.value
[OPP_OD
] = VDD_EVE_DRA7_OD
,
498 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
499 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
500 .eve
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_DSPEVE_OD
,
501 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
502 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
503 .eve
.addr
= TPS65917_REG_ADDR_SMPS3
,
504 .eve
.pmic
= &tps659038
,
505 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
507 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
508 .iva
.value
[OPP_OD
] = VDD_IVA_DRA7_OD
,
509 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
510 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
511 .iva
.efuse
.reg
[OPP_OD
] = STD_FUSE_OPP_VMIN_IVA_OD
,
512 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
513 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
514 .iva
.addr
= TPS65917_REG_ADDR_SMPS3
,
515 .iva
.pmic
= &tps659038
,
516 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
519 struct vcores_data dra718_volts
= {
521 * In the case of dra71x GPU MPU and CORE
522 * are all powered up by BUCK0 of LP873X PMIC
524 .mpu
.value
[OPP_NOM
] = VDD_MPU_DRA7_NOM
,
525 .mpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_MPU_NOM
,
526 .mpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
527 .mpu
.addr
= LP873X_REG_ADDR_BUCK0
,
529 .mpu
.abb_tx_done_mask
= OMAP_ABB_MPU_TXDONE_MASK
,
531 .core
.value
[OPP_NOM
] = VDD_CORE_DRA7_NOM
,
532 .core
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_CORE_NOM
,
533 .core
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
534 .core
.addr
= LP873X_REG_ADDR_BUCK0
,
535 .core
.pmic
= &lp8733
,
537 .gpu
.value
[OPP_NOM
] = VDD_GPU_DRA7_NOM
,
538 .gpu
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_GPU_NOM
,
539 .gpu
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
540 .gpu
.addr
= LP873X_REG_ADDR_BUCK0
,
542 .gpu
.abb_tx_done_mask
= OMAP_ABB_GPU_TXDONE_MASK
,
545 * The DSPEVE and IVA rails are grouped on DRA71x-evm
546 * and are powered by BUCK1 of LP873X PMIC
548 .eve
.value
[OPP_NOM
] = VDD_EVE_DRA7_NOM
,
549 .eve
.value
[OPP_HIGH
] = VDD_EVE_DRA7_HIGH
,
550 .eve
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_DSPEVE_NOM
,
551 .eve
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH
,
552 .eve
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
553 .eve
.addr
= LP873X_REG_ADDR_BUCK1
,
555 .eve
.abb_tx_done_mask
= OMAP_ABB_EVE_TXDONE_MASK
,
557 .iva
.value
[OPP_NOM
] = VDD_IVA_DRA7_NOM
,
558 .iva
.value
[OPP_HIGH
] = VDD_IVA_DRA7_HIGH
,
559 .iva
.efuse
.reg
[OPP_NOM
] = STD_FUSE_OPP_VMIN_IVA_NOM
,
560 .iva
.efuse
.reg
[OPP_HIGH
] = STD_FUSE_OPP_VMIN_IVA_HIGH
,
561 .iva
.efuse
.reg_bits
= DRA752_EFUSE_REGBITS
,
562 .iva
.addr
= LP873X_REG_ADDR_BUCK1
,
564 .iva
.abb_tx_done_mask
= OMAP_ABB_IVA_TXDONE_MASK
,
567 int get_voltrail_opp(int rail_offset
)
571 switch (rail_offset
) {
574 /* DRA71x supports only OPP_NOM for MPU */
575 if (board_is_dra71x_evm())
580 /* DRA71x supports only OPP_NOM for CORE */
581 if (board_is_dra71x_evm())
586 /* DRA71x supports only OPP_NOM for GPU */
587 if (board_is_dra71x_evm())
591 opp
= DRA7_DSPEVE_OPP
;
593 * DRA71x does not support OPP_OD for EVE.
594 * If OPP_OD is selected by menuconfig, fallback
597 if (board_is_dra71x_evm() && opp
== OPP_OD
)
603 * DRA71x does not support OPP_OD for IVA.
604 * If OPP_OD is selected by menuconfig, fallback
607 if (board_is_dra71x_evm() && opp
== OPP_OD
)
625 gd
->bd
->bi_boot_params
= (0x80000000 + 0x100); /* boot param addr */
630 int dram_init_banksize(void)
634 ram_size
= board_ti_get_emif_size();
636 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_SDRAM_BASE
;
637 gd
->bd
->bi_dram
[0].size
= get_effective_memsize();
638 if (ram_size
> CONFIG_MAX_MEM_MAPPED
) {
639 gd
->bd
->bi_dram
[1].start
= 0x200000000;
640 gd
->bd
->bi_dram
[1].size
= ram_size
- CONFIG_MAX_MEM_MAPPED
;
646 int board_late_init(void)
648 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
649 char *name
= "unknown";
652 if (board_is_dra72x_revc_or_later())
653 name
= "dra72x-revc";
654 else if (board_is_dra71x_evm())
658 } else if (is_dra76x()) {
664 set_board_info_env(name
);
667 * Default FIT boot on HS devices. Non FIT images are not allowed
670 if (get_device_type() == HS_DEVICE
)
671 env_set("boot_fit", "1");
673 omap_die_id_serial();
674 omap_set_fastboot_vars();
679 #ifdef CONFIG_SPL_BUILD
680 void do_board_detect(void)
684 rc
= ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS
,
685 CONFIG_EEPROM_CHIP_ADDRESS
);
687 printf("ti_i2c_eeprom_init failed %d\n", rc
);
692 void do_board_detect(void)
697 rc
= ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS
,
698 CONFIG_EEPROM_CHIP_ADDRESS
);
700 printf("ti_i2c_eeprom_init failed %d\n", rc
);
702 if (board_is_dra74x_evm()) {
703 bname
= "DRA74x EVM";
704 } else if (board_is_dra72x_evm()) {
705 bname
= "DRA72x EVM";
706 } else if (board_is_dra71x_evm()) {
707 bname
= "DRA71x EVM";
708 } else if (board_is_dra76x_evm()) {
709 bname
= "DRA76x EVM";
711 /* If EEPROM is not populated */
713 bname
= "DRA72x EVM";
715 bname
= "DRA74x EVM";
719 snprintf(sysinfo
.board_string
, SYSINFO_BOARD_NAME_MAX_LEN
,
720 "Board: %s REV %s\n", bname
, board_ti_get_rev());
722 #endif /* CONFIG_SPL_BUILD */
724 void vcores_init(void)
726 if (board_is_dra74x_evm()) {
727 *omap_vcores
= &dra752_volts
;
728 } else if (board_is_dra72x_evm()) {
729 *omap_vcores
= &dra722_volts
;
730 } else if (board_is_dra71x_evm()) {
731 *omap_vcores
= &dra718_volts
;
732 } else if (board_is_dra76x_evm()) {
733 *omap_vcores
= &dra76x_volts
;
735 /* If EEPROM is not populated */
737 *omap_vcores
= &dra722_volts
;
739 *omap_vcores
= &dra752_volts
;
743 void set_muxconf_regs(void)
745 do_set_mux32((*ctrl
)->control_padconf_core_base
,
746 early_padconf
, ARRAY_SIZE(early_padconf
));
749 #ifdef CONFIG_IODELAY_RECALIBRATION
750 void recalibrate_iodelay(void)
752 struct pad_conf_entry
const *pads
, *delta_pads
= NULL
;
753 struct iodelay_cfg_entry
const *iodelay
;
754 int npads
, niodelays
, delta_npads
= 0;
757 switch (omap_revision()) {
761 pads
= dra72x_core_padconf_array_common
;
762 npads
= ARRAY_SIZE(dra72x_core_padconf_array_common
);
763 if (board_is_dra71x_evm()) {
764 pads
= dra71x_core_padconf_array
;
765 npads
= ARRAY_SIZE(dra71x_core_padconf_array
);
766 iodelay
= dra71_iodelay_cfg_array
;
767 niodelays
= ARRAY_SIZE(dra71_iodelay_cfg_array
);
768 } else if (board_is_dra72x_revc_or_later()) {
769 delta_pads
= dra72x_rgmii_padconf_array_revc
;
771 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc
);
772 iodelay
= dra72_iodelay_cfg_array_revc
;
773 niodelays
= ARRAY_SIZE(dra72_iodelay_cfg_array_revc
);
775 delta_pads
= dra72x_rgmii_padconf_array_revb
;
777 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb
);
778 iodelay
= dra72_iodelay_cfg_array_revb
;
779 niodelays
= ARRAY_SIZE(dra72_iodelay_cfg_array_revb
);
784 pads
= dra74x_core_padconf_array
;
785 npads
= ARRAY_SIZE(dra74x_core_padconf_array
);
786 iodelay
= dra742_es1_1_iodelay_cfg_array
;
787 niodelays
= ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array
);
790 pads
= dra76x_core_padconf_array
;
791 npads
= ARRAY_SIZE(dra76x_core_padconf_array
);
792 iodelay
= dra76x_es1_0_iodelay_cfg_array
;
793 niodelays
= ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array
);
797 pads
= dra74x_core_padconf_array
;
798 npads
= ARRAY_SIZE(dra74x_core_padconf_array
);
799 iodelay
= dra742_es2_0_iodelay_cfg_array
;
800 niodelays
= ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array
);
801 /* Setup port1 and port2 for rgmii with 'no-id' mode */
802 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK
|
803 RGMII1_ID_MODE_N_MASK
);
806 /* Setup I/O isolation */
807 ret
= __recalibrate_iodelay_start();
811 /* Do the muxing here */
812 do_set_mux32((*ctrl
)->control_padconf_core_base
, pads
, npads
);
814 /* Now do the weird minor deltas that should be safe */
816 do_set_mux32((*ctrl
)->control_padconf_core_base
,
817 delta_pads
, delta_npads
);
819 /* Setup IOdelay configuration */
820 ret
= do_set_iodelay((*ctrl
)->iodelay_config_base
, iodelay
, niodelays
);
822 /* Closeup.. remove isolation */
823 __recalibrate_iodelay_end(ret
);
827 #if defined(CONFIG_MMC)
828 int board_mmc_init(bd_t
*bis
)
830 omap_mmc_init(0, 0, 0, -1, -1);
831 omap_mmc_init(1, 0, 0, -1, -1);
835 void board_mmc_poweron_ldo(uint voltage
)
837 if (board_is_dra71x_evm()) {
838 if (voltage
== LDO_VOLT_3V0
)
840 else if (voltage
== LDO_VOLT_1V8
)
842 lp873x_mmc1_poweron_ldo(voltage
);
843 } else if (board_is_dra76x_evm()) {
844 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE
, LDO4_CTRL
, voltage
);
846 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE
, LDO1_CTRL
, voltage
);
851 #ifdef CONFIG_USB_DWC3
852 static struct dwc3_device usb_otg_ss1
= {
853 .maximum_speed
= USB_SPEED_SUPER
,
854 .base
= DRA7_USB_OTG_SS1_BASE
,
855 .tx_fifo_resize
= false,
859 static struct dwc3_omap_device usb_otg_ss1_glue
= {
860 .base
= (void *)DRA7_USB_OTG_SS1_GLUE_BASE
,
861 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
865 static struct ti_usb_phy_device usb_phy1_device
= {
866 .pll_ctrl_base
= (void *)DRA7_USB3_PHY1_PLL_CTRL
,
867 .usb2_phy_power
= (void *)DRA7_USB2_PHY1_POWER
,
868 .usb3_phy_power
= (void *)DRA7_USB3_PHY1_POWER
,
872 static struct dwc3_device usb_otg_ss2
= {
873 .maximum_speed
= USB_SPEED_SUPER
,
874 .base
= DRA7_USB_OTG_SS2_BASE
,
875 .tx_fifo_resize
= false,
879 static struct dwc3_omap_device usb_otg_ss2_glue
= {
880 .base
= (void *)DRA7_USB_OTG_SS2_GLUE_BASE
,
881 .utmi_mode
= DWC3_OMAP_UTMI_MODE_SW
,
885 static struct ti_usb_phy_device usb_phy2_device
= {
886 .usb2_phy_power
= (void *)DRA7_USB2_PHY2_POWER
,
890 int omap_xhci_board_usb_init(int index
, enum usb_init_type init
)
892 enable_usb_clocks(index
);
895 if (init
== USB_INIT_DEVICE
) {
896 usb_otg_ss1
.dr_mode
= USB_DR_MODE_PERIPHERAL
;
897 usb_otg_ss1_glue
.vbus_id_status
= OMAP_DWC3_VBUS_VALID
;
899 usb_otg_ss1
.dr_mode
= USB_DR_MODE_HOST
;
900 usb_otg_ss1_glue
.vbus_id_status
= OMAP_DWC3_ID_GROUND
;
903 ti_usb_phy_uboot_init(&usb_phy1_device
);
904 dwc3_omap_uboot_init(&usb_otg_ss1_glue
);
905 dwc3_uboot_init(&usb_otg_ss1
);
908 if (init
== USB_INIT_DEVICE
) {
909 usb_otg_ss2
.dr_mode
= USB_DR_MODE_PERIPHERAL
;
910 usb_otg_ss2_glue
.vbus_id_status
= OMAP_DWC3_VBUS_VALID
;
912 usb_otg_ss2
.dr_mode
= USB_DR_MODE_HOST
;
913 usb_otg_ss2_glue
.vbus_id_status
= OMAP_DWC3_ID_GROUND
;
916 ti_usb_phy_uboot_init(&usb_phy2_device
);
917 dwc3_omap_uboot_init(&usb_otg_ss2_glue
);
918 dwc3_uboot_init(&usb_otg_ss2
);
921 printf("Invalid Controller Index\n");
927 int omap_xhci_board_usb_cleanup(int index
, enum usb_init_type init
)
932 ti_usb_phy_uboot_exit(index
);
933 dwc3_uboot_exit(index
);
934 dwc3_omap_uboot_exit(index
);
937 printf("Invalid Controller Index\n");
939 disable_usb_clocks(index
);
943 int usb_gadget_handle_interrupts(int index
)
947 status
= dwc3_omap_uboot_interrupt_status(index
);
949 dwc3_uboot_handle_interrupt(index
);
955 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
956 int spl_start_uboot(void)
958 /* break into full u-boot on 'c' */
959 if (serial_tstc() && serial_getc() == 'c')
962 #ifdef CONFIG_SPL_ENV_SUPPORT
965 if (env_get_yesno("boot_os") != 1)
973 #ifdef CONFIG_DRIVER_TI_CPSW
974 extern u32
*const omap_si_rev
;
976 static void cpsw_control(int enabled
)
978 /* VTP can be added here */
983 static struct cpsw_slave_data cpsw_slaves
[] = {
985 .slave_reg_ofs
= 0x208,
986 .sliver_reg_ofs
= 0xd80,
990 .slave_reg_ofs
= 0x308,
991 .sliver_reg_ofs
= 0xdc0,
996 static struct cpsw_platform_data cpsw_data
= {
997 .mdio_base
= CPSW_MDIO_BASE
,
998 .cpsw_base
= CPSW_BASE
,
1001 .cpdma_reg_ofs
= 0x800,
1003 .slave_data
= cpsw_slaves
,
1004 .ale_reg_ofs
= 0xd00,
1005 .ale_entries
= 1024,
1006 .host_port_reg_ofs
= 0x108,
1007 .hw_stats_reg_ofs
= 0x900,
1008 .bd_ram_ofs
= 0x2000,
1009 .mac_control
= (1 << 5),
1010 .control
= cpsw_control
,
1012 .version
= CPSW_CTRL_VERSION_2
,
1015 int board_eth_init(bd_t
*bis
)
1018 uint8_t mac_addr
[6];
1019 uint32_t mac_hi
, mac_lo
;
1022 /* try reading mac address from efuse */
1023 mac_lo
= readl((*ctrl
)->control_core_mac_id_0_lo
);
1024 mac_hi
= readl((*ctrl
)->control_core_mac_id_0_hi
);
1025 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
1026 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
1027 mac_addr
[2] = mac_hi
& 0xFF;
1028 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
1029 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
1030 mac_addr
[5] = mac_lo
& 0xFF;
1032 if (!env_get("ethaddr")) {
1033 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
1035 if (is_valid_ethaddr(mac_addr
))
1036 eth_env_set_enetaddr("ethaddr", mac_addr
);
1039 mac_lo
= readl((*ctrl
)->control_core_mac_id_1_lo
);
1040 mac_hi
= readl((*ctrl
)->control_core_mac_id_1_hi
);
1041 mac_addr
[0] = (mac_hi
& 0xFF0000) >> 16;
1042 mac_addr
[1] = (mac_hi
& 0xFF00) >> 8;
1043 mac_addr
[2] = mac_hi
& 0xFF;
1044 mac_addr
[3] = (mac_lo
& 0xFF0000) >> 16;
1045 mac_addr
[4] = (mac_lo
& 0xFF00) >> 8;
1046 mac_addr
[5] = mac_lo
& 0xFF;
1048 if (!env_get("eth1addr")) {
1049 if (is_valid_ethaddr(mac_addr
))
1050 eth_env_set_enetaddr("eth1addr", mac_addr
);
1053 ctrl_val
= readl((*ctrl
)->control_core_control_io1
) & (~0x33);
1055 writel(ctrl_val
, (*ctrl
)->control_core_control_io1
);
1057 if (*omap_si_rev
== DRA722_ES1_0
)
1058 cpsw_data
.active_slave
= 1;
1060 if (board_is_dra72x_revc_or_later()) {
1061 cpsw_slaves
[0].phy_if
= PHY_INTERFACE_MODE_RGMII_ID
;
1062 cpsw_slaves
[1].phy_if
= PHY_INTERFACE_MODE_RGMII_ID
;
1065 ret
= cpsw_register(&cpsw_data
);
1067 printf("Error %d registering CPSW switch\n", ret
);
1073 #ifdef CONFIG_BOARD_EARLY_INIT_F
1074 /* VTT regulator enable */
1075 static inline void vtt_regulator_enable(void)
1077 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL
)
1080 /* Do not enable VTT for DRA722 or DRA76x */
1081 if (is_dra72x() || is_dra76x())
1085 * EVM Rev G and later use gpio7_11 for DDR3 termination.
1086 * This is safe enough to do on older revs.
1088 gpio_request(GPIO_DDR_VTT_EN
, "ddr_vtt_en");
1089 gpio_direction_output(GPIO_DDR_VTT_EN
, 1);
1092 int board_early_init_f(void)
1094 vtt_regulator_enable();
1099 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1100 int ft_board_setup(void *blob
, bd_t
*bd
)
1102 ft_cpu_setup(blob
, bd
);
1108 #ifdef CONFIG_SPL_LOAD_FIT
1109 int board_fit_config_name_match(const char *name
)
1112 if (board_is_dra71x_evm()) {
1113 if (!strcmp(name
, "dra71-evm"))
1115 }else if(board_is_dra72x_revc_or_later()) {
1116 if (!strcmp(name
, "dra72-evm-revc"))
1118 } else if (!strcmp(name
, "dra72-evm")) {
1121 } else if (is_dra76x() && !strcmp(name
, "dra76-evm")) {
1123 } else if (!is_dra72x() && !is_dra76x() && !strcmp(name
, "dra7-evm")) {
1131 #ifdef CONFIG_TI_SECURE_DEVICE
1132 void board_fit_image_post_process(void **p_image
, size_t *p_size
)
1134 secure_boot_verify_image(p_image
, p_size
);
1137 void board_tee_image_process(ulong tee_image
, size_t tee_size
)
1139 secure_tee_install((u32
)tee_image
);
1142 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE
, board_tee_image_process
);