board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <linux/string.h>
  17 #include <asm/gpio.h>
  18 #include <usb.h>
  19 #include <linux/usb/gadget.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/dra7xx_iodelay.h>
  22 #include <asm/emif.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <asm/arch/mmc_host_def.h>
  25 #include <asm/arch/sata.h>
  26 #include <environment.h>
  27 #include <dwc3-uboot.h>
  28 #include <dwc3-omap-uboot.h>
  29 #include <ti-usb-phy-uboot.h>
  30 #include <miiphy.h>
  31
  32 #include "mux_data.h"
  33 #include "../common/board_detect.h"
  34
  35 #define board_is_dra74x_evm()           board_ti_is("5777xCPU")
  36 #define board_is_dra72x_evm()           board_ti_is("DRA72x-T")
  37 #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() &&        \
  38                                 (strncmp("H", board_ti_get_rev(), 1) <= 0)
  39 #define board_is_dra72x_revc_or_later() board_is_dra72x_evm() &&        \
  40                                 (strncmp("C", board_ti_get_rev(), 1) <= 0)
  41 #define board_ti_get_emif_size()        board_ti_get_emif1_size() +     \
  42                                         board_ti_get_emif2_size()
  43
  44 #ifdef CONFIG_DRIVER_TI_CPSW
  45 #include <cpsw.h>
  46 #endif
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 /* GPIO 7_11 */
  51 #define GPIO_DDR_VTT_EN 203
  52
  53 #define SYSINFO_BOARD_NAME_MAX_LEN      37
  54
  55 const struct omap_sysinfo sysinfo = {
  56         "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  57 };
  58
  59 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  60         .sdram_config_init              = 0x61851ab2,
  61         .sdram_config                   = 0x61851ab2,
  62         .sdram_config2                  = 0x08000000,
  63         .ref_ctrl                       = 0x000040F1,
  64         .ref_ctrl_final                 = 0x00001035,
  65         .sdram_tim1                     = 0xCCCF36B3,
  66         .sdram_tim2                     = 0x308F7FDA,
  67         .sdram_tim3                     = 0x427F88A8,
  68         .read_idle_ctrl                 = 0x00050000,
  69         .zq_config                      = 0x0007190B,
  70         .temp_alert_config              = 0x00000000,
  71         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  72         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  73         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  74         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
  75         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
  76         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
  77         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
  78         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
  79         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
  80         .emif_rd_wr_lvl_ctl             = 0x00000000,
  81         .emif_rd_wr_exec_thresh         = 0x00000305
  82 };
  83
  84 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  85         .sdram_config_init              = 0x61851B32,
  86         .sdram_config                   = 0x61851B32,
  87         .sdram_config2                  = 0x08000000,
  88         .ref_ctrl                       = 0x000040F1,
  89         .ref_ctrl_final                 = 0x00001035,
  90         .sdram_tim1                     = 0xCCCF36B3,
  91         .sdram_tim2                     = 0x308F7FDA,
  92         .sdram_tim3                     = 0x427F88A8,
  93         .read_idle_ctrl                 = 0x00050000,
  94         .zq_config                      = 0x0007190B,
  95         .temp_alert_config              = 0x00000000,
  96         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
  97         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
  98         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
  99         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 100         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 101         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 102         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 103         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 104         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 105         .emif_rd_wr_lvl_ctl             = 0x00000000,
 106         .emif_rd_wr_exec_thresh         = 0x00000305
 107 };
 108
 109 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 110         .sdram_config_init              = 0x61862B32,
 111         .sdram_config                   = 0x61862B32,
 112         .sdram_config2                  = 0x08000000,
 113         .ref_ctrl                       = 0x0000514C,
 114         .ref_ctrl_final                 = 0x0000144A,
 115         .sdram_tim1                     = 0xD113781C,
 116         .sdram_tim2                     = 0x30717FE3,
 117         .sdram_tim3                     = 0x409F86A8,
 118         .read_idle_ctrl                 = 0x00050000,
 119         .zq_config                      = 0x5007190B,
 120         .temp_alert_config              = 0x00000000,
 121         .emif_ddr_phy_ctlr_1_init       = 0x0024400D,
 122         .emif_ddr_phy_ctlr_1            = 0x0E24400D,
 123         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 124         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 125         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 126         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 127         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 128         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 129         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 130         .emif_rd_wr_lvl_ctl             = 0x00000000,
 131         .emif_rd_wr_exec_thresh         = 0x00000305
 132 };
 133
 134 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
 135         .sdram_config_init              = 0x61862BB2,
 136         .sdram_config                   = 0x61862BB2,
 137         .sdram_config2                  = 0x00000000,
 138         .ref_ctrl                       = 0x0000514D,
 139         .ref_ctrl_final                 = 0x0000144A,
 140         .sdram_tim1                     = 0xD1137824,
 141         .sdram_tim2                     = 0x30B37FE3,
 142         .sdram_tim3                     = 0x409F8AD8,
 143         .read_idle_ctrl                 = 0x00050000,
 144         .zq_config                      = 0x5007190B,
 145         .temp_alert_config              = 0x00000000,
 146         .emif_ddr_phy_ctlr_1_init       = 0x0824400E,
 147         .emif_ddr_phy_ctlr_1            = 0x0E24400E,
 148         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 149         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,
 150         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,
 151         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,
 152         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,
 153         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 154         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 155         .emif_rd_wr_lvl_ctl             = 0x00000000,
 156         .emif_rd_wr_exec_thresh         = 0x00000305
 157 };
 158
 159 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
 160         .sdram_config_init              = 0x61851ab2,
 161         .sdram_config                   = 0x61851ab2,
 162         .sdram_config2                  = 0x08000000,
 163         .ref_ctrl                       = 0x000040F1,
 164         .ref_ctrl_final                 = 0x00001035,
 165         .sdram_tim1                     = 0xCCCF36B3,
 166         .sdram_tim2                     = 0x30BF7FDA,
 167         .sdram_tim3                     = 0x427F8BA8,
 168         .read_idle_ctrl                 = 0x00050000,
 169         .zq_config                      = 0x0007190B,
 170         .temp_alert_config              = 0x00000000,
 171         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 172         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 173         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 174         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 175         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 176         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 177         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 178         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 179         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 180         .emif_rd_wr_lvl_ctl             = 0x00000000,
 181         .emif_rd_wr_exec_thresh         = 0x00000305
 182 };
 183
 184 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
 185         .sdram_config_init              = 0x61851B32,
 186         .sdram_config                   = 0x61851B32,
 187         .sdram_config2                  = 0x08000000,
 188         .ref_ctrl                       = 0x000040F1,
 189         .ref_ctrl_final                 = 0x00001035,
 190         .sdram_tim1                     = 0xCCCF36B3,
 191         .sdram_tim2                     = 0x308F7FDA,
 192         .sdram_tim3                     = 0x427F88A8,
 193         .read_idle_ctrl                 = 0x00050000,
 194         .zq_config                      = 0x0007190B,
 195         .temp_alert_config              = 0x00000000,
 196         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
 197         .emif_ddr_phy_ctlr_1            = 0x0E24400B,
 198         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 199         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
 200         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
 201         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
 202         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 203         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 204         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 205         .emif_rd_wr_lvl_ctl             = 0x00000000,
 206         .emif_rd_wr_exec_thresh         = 0x00000305
 207 };
 208
 209 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 210 {
 211         u64 ram_size;
 212
 213         ram_size = board_ti_get_emif_size();
 214
 215         switch (omap_revision()) {
 216         case DRA752_ES1_0:
 217         case DRA752_ES1_1:
 218         case DRA752_ES2_0:
 219                 switch (emif_nr) {
 220                 case 1:
 221                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 222                                 *regs = &emif1_ddr3_532_mhz_1cs_2G;
 223                         else
 224                                 *regs = &emif1_ddr3_532_mhz_1cs;
 225                         break;
 226                 case 2:
 227                         if (ram_size > CONFIG_MAX_MEM_MAPPED)
 228                                 *regs = &emif2_ddr3_532_mhz_1cs_2G;
 229                         else
 230                                 *regs = &emif2_ddr3_532_mhz_1cs;
 231                         break;
 232                 }
 233                 break;
 234         case DRA722_ES1_0:
 235         case DRA722_ES2_0:
 236                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 237                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 238                 else
 239                         *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
 240                 break;
 241         default:
 242                 *regs = &emif1_ddr3_532_mhz_1cs;
 243         }
 244 }
 245
 246 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
 247         .dmm_lisa_map_0 = 0x0,
 248         .dmm_lisa_map_1 = 0x80640300,
 249         .dmm_lisa_map_2 = 0xC0500220,
 250         .dmm_lisa_map_3 = 0xFF020100,
 251         .is_ma_present  = 0x1
 252 };
 253
 254 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 255         .dmm_lisa_map_0 = 0x0,
 256         .dmm_lisa_map_1 = 0x0,
 257         .dmm_lisa_map_2 = 0x80600100,
 258         .dmm_lisa_map_3 = 0xFF020100,
 259         .is_ma_present  = 0x1
 260 };
 261
 262 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
 263         .dmm_lisa_map_0 = 0x0,
 264         .dmm_lisa_map_1 = 0x0,
 265         .dmm_lisa_map_2 = 0x80740300,
 266         .dmm_lisa_map_3 = 0xFF020100,
 267         .is_ma_present  = 0x1
 268 };
 269
 270 /*
 271  * DRA722 EVM EMIF1 2GB CONFIGURATION
 272  * EMIF1 4 devices of 512Mb x 8 Micron
 273  */
 274 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
 275         .dmm_lisa_map_0 = 0x0,
 276         .dmm_lisa_map_1 = 0x0,
 277         .dmm_lisa_map_2 = 0x80700100,
 278         .dmm_lisa_map_3 = 0xFF020100,
 279         .is_ma_present  = 0x1
 280 };
 281
 282 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 283 {
 284         u64 ram_size;
 285
 286         ram_size = board_ti_get_emif_size();
 287
 288         switch (omap_revision()) {
 289         case DRA752_ES1_0:
 290         case DRA752_ES1_1:
 291         case DRA752_ES2_0:
 292                 if (ram_size > CONFIG_MAX_MEM_MAPPED)
 293                         *dmm_lisa_regs = &lisa_map_dra7_2GB;
 294                 else
 295                         *dmm_lisa_regs = &lisa_map_dra7_1536MB;
 296                 break;
 297         case DRA722_ES1_0:
 298         case DRA722_ES2_0:
 299         default:
 300                 if (ram_size < CONFIG_MAX_MEM_MAPPED)
 301                         *dmm_lisa_regs = &lisa_map_2G_x_2;
 302                 else
 303                         *dmm_lisa_regs = &lisa_map_2G_x_4;
 304                 break;
 305         }
 306 }
 307
 308 struct vcores_data dra752_volts = {
 309         .mpu.value      = VDD_MPU_DRA7,
 310         .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
 311         .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 312         .mpu.addr       = TPS659038_REG_ADDR_SMPS12,
 313         .mpu.pmic       = &tps659038,
 314         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 315
 316         .eve.value      = VDD_EVE_DRA7,
 317         .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
 318         .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 319         .eve.addr       = TPS659038_REG_ADDR_SMPS45,
 320         .eve.pmic       = &tps659038,
 321         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 322
 323         .gpu.value      = VDD_GPU_DRA7,
 324         .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
 325         .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 326         .gpu.addr       = TPS659038_REG_ADDR_SMPS6,
 327         .gpu.pmic       = &tps659038,
 328         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 329
 330         .core.value     = VDD_CORE_DRA7,
 331         .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
 332         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 333         .core.addr      = TPS659038_REG_ADDR_SMPS7,
 334         .core.pmic      = &tps659038,
 335
 336         .iva.value      = VDD_IVA_DRA7,
 337         .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
 338         .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 339         .iva.addr       = TPS659038_REG_ADDR_SMPS8,
 340         .iva.pmic       = &tps659038,
 341         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 342 };
 343
 344 struct vcores_data dra722_volts = {
 345         .mpu.value      = VDD_MPU_DRA7,
 346         .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU,
 347         .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 348         .mpu.addr       = TPS65917_REG_ADDR_SMPS1,
 349         .mpu.pmic       = &tps659038,
 350         .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 351
 352         .core.value     = VDD_CORE_DRA7,
 353         .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
 354         .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 355         .core.addr      = TPS65917_REG_ADDR_SMPS2,
 356         .core.pmic      = &tps659038,
 357
 358         /*
 359          * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 360          * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 361          */
 362         .gpu.value      = VDD_GPU_DRA7,
 363         .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU,
 364         .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 365         .gpu.addr       = TPS65917_REG_ADDR_SMPS3,
 366         .gpu.pmic       = &tps659038,
 367         .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 368
 369         .eve.value      = VDD_EVE_DRA7,
 370         .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE,
 371         .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 372         .eve.addr       = TPS65917_REG_ADDR_SMPS3,
 373         .eve.pmic       = &tps659038,
 374         .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 375
 376         .iva.value      = VDD_IVA_DRA7,
 377         .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA,
 378         .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 379         .iva.addr       = TPS65917_REG_ADDR_SMPS3,
 380         .iva.pmic       = &tps659038,
 381         .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 382 };
 383
 384 /**
 385  * @brief board_init
 386  *
 387  * @return 0
 388  */
 389 int board_init(void)
 390 {
 391         gpmc_init();
 392         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
 393
 394         return 0;
 395 }
 396
 397 void dram_init_banksize(void)
 398 {
 399         u64 ram_size;
 400
 401         ram_size = board_ti_get_emif_size();
 402
 403         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 404         gd->bd->bi_dram[0].size = get_effective_memsize();
 405         if (ram_size > CONFIG_MAX_MEM_MAPPED) {
 406                 gd->bd->bi_dram[1].start = 0x200000000;
 407                 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
 408         }
 409 }
 410
 411 int board_late_init(void)
 412 {
 413 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 414         char *name = "unknown";
 415
 416         if (is_dra72x())
 417                 name = "dra72x";
 418         else
 419                 name = "dra7xx";
 420
 421         set_board_info_env(name);
 422
 423         omap_die_id_serial();
 424 #endif
 425         return 0;
 426 }
 427
 428 #ifdef CONFIG_SPL_BUILD
 429 void do_board_detect(void)
 430 {
 431         int rc;
 432
 433         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 434                                     CONFIG_EEPROM_CHIP_ADDRESS);
 435         if (rc)
 436                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 437 }
 438
 439 #else
 440
 441 void do_board_detect(void)
 442 {
 443         char *bname = NULL;
 444         int rc;
 445
 446         rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
 447                                     CONFIG_EEPROM_CHIP_ADDRESS);
 448         if (rc)
 449                 printf("ti_i2c_eeprom_init failed %d\n", rc);
 450
 451         if (board_is_dra74x_evm()) {
 452                 bname = "DRA74x EVM";
 453         } else if (board_is_dra72x_evm()) {
 454                 bname = "DRA72x EVM";
 455         } else {
 456                 /* If EEPROM is not populated */
 457                 if (is_dra72x())
 458                         bname = "DRA72x EVM";
 459                 else
 460                         bname = "DRA74x EVM";
 461         }
 462
 463         if (bname)
 464                 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
 465                          "Board: %s REV %s\n", bname, board_ti_get_rev());
 466 }
 467 #endif  /* CONFIG_SPL_BUILD */
 468
 469 void vcores_init(void)
 470 {
 471         if (board_is_dra74x_evm()) {
 472                 *omap_vcores = &dra752_volts;
 473         } else if (board_is_dra72x_evm()) {
 474                 *omap_vcores = &dra722_volts;
 475         } else {
 476                 /* If EEPROM is not populated */
 477                 if (is_dra72x())
 478                         *omap_vcores = &dra722_volts;
 479                 else
 480                         *omap_vcores = &dra752_volts;
 481         }
 482 }
 483
 484 void set_muxconf_regs(void)
 485 {
 486         do_set_mux32((*ctrl)->control_padconf_core_base,
 487                      early_padconf, ARRAY_SIZE(early_padconf));
 488 }
 489
 490 #ifdef CONFIG_IODELAY_RECALIBRATION
 491 void recalibrate_iodelay(void)
 492 {
 493         struct pad_conf_entry const *pads, *delta_pads = NULL;
 494         struct iodelay_cfg_entry const *iodelay;
 495         int npads, niodelays, delta_npads = 0;
 496         int ret;
 497
 498         switch (omap_revision()) {
 499         case DRA722_ES1_0:
 500         case DRA722_ES2_0:
 501                 pads = dra72x_core_padconf_array_common;
 502                 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 503                 if (board_is_dra72x_revc_or_later()) {
 504                         delta_pads = dra72x_rgmii_padconf_array_revc;
 505                         delta_npads =
 506                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
 507                         iodelay = dra72_iodelay_cfg_array_revc;
 508                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
 509                 } else {
 510                         delta_pads = dra72x_rgmii_padconf_array_revb;
 511                         delta_npads =
 512                                 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
 513                         iodelay = dra72_iodelay_cfg_array_revb;
 514                         niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
 515                 }
 516                 break;
 517         case DRA752_ES1_0:
 518         case DRA752_ES1_1:
 519                 pads = dra74x_core_padconf_array;
 520                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 521                 iodelay = dra742_es1_1_iodelay_cfg_array;
 522                 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
 523                 break;
 524         default:
 525         case DRA752_ES2_0:
 526                 pads = dra74x_core_padconf_array;
 527                 npads = ARRAY_SIZE(dra74x_core_padconf_array);
 528                 iodelay = dra742_es2_0_iodelay_cfg_array;
 529                 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
 530                 /* Setup port1 and port2 for rgmii with 'no-id' mode */
 531                 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
 532                                       RGMII1_ID_MODE_N_MASK);
 533                 break;
 534         }
 535         /* Setup I/O isolation */
 536         ret = __recalibrate_iodelay_start();
 537         if (ret)
 538                 goto err;
 539
 540         /* Do the muxing here */
 541         do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
 542
 543         /* Now do the weird minor deltas that should be safe */
 544         if (delta_npads)
 545                 do_set_mux32((*ctrl)->control_padconf_core_base,
 546                              delta_pads, delta_npads);
 547
 548         /* Setup IOdelay configuration */
 549         ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
 550 err:
 551         /* Closeup.. remove isolation */
 552         __recalibrate_iodelay_end(ret);
 553 }
 554 #endif
 555
 556 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 557 int board_mmc_init(bd_t *bis)
 558 {
 559         omap_mmc_init(0, 0, 0, -1, -1);
 560         omap_mmc_init(1, 0, 0, -1, -1);
 561         return 0;
 562 }
 563 #endif
 564
 565 #ifdef CONFIG_USB_DWC3
 566 static struct dwc3_device usb_otg_ss1 = {
 567         .maximum_speed = USB_SPEED_SUPER,
 568         .base = DRA7_USB_OTG_SS1_BASE,
 569         .tx_fifo_resize = false,
 570         .index = 0,
 571 };
 572
 573 static struct dwc3_omap_device usb_otg_ss1_glue = {
 574         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 575         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 576         .index = 0,
 577 };
 578
 579 static struct ti_usb_phy_device usb_phy1_device = {
 580         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 581         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 582         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 583         .index = 0,
 584 };
 585
 586 static struct dwc3_device usb_otg_ss2 = {
 587         .maximum_speed = USB_SPEED_SUPER,
 588         .base = DRA7_USB_OTG_SS2_BASE,
 589         .tx_fifo_resize = false,
 590         .index = 1,
 591 };
 592
 593 static struct dwc3_omap_device usb_otg_ss2_glue = {
 594         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 595         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 596         .index = 1,
 597 };
 598
 599 static struct ti_usb_phy_device usb_phy2_device = {
 600         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 601         .index = 1,
 602 };
 603
 604 int board_usb_init(int index, enum usb_init_type init)
 605 {
 606         enable_usb_clocks(index);
 607         switch (index) {
 608         case 0:
 609                 if (init == USB_INIT_DEVICE) {
 610                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 611                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 612                 } else {
 613                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 614                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 615                 }
 616
 617                 ti_usb_phy_uboot_init(&usb_phy1_device);
 618                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 619                 dwc3_uboot_init(&usb_otg_ss1);
 620                 break;
 621         case 1:
 622                 if (init == USB_INIT_DEVICE) {
 623                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 624                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 625                 } else {
 626                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 627                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 628                 }
 629
 630                 ti_usb_phy_uboot_init(&usb_phy2_device);
 631                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 632                 dwc3_uboot_init(&usb_otg_ss2);
 633                 break;
 634         default:
 635                 printf("Invalid Controller Index\n");
 636         }
 637
 638         return 0;
 639 }
 640
 641 int board_usb_cleanup(int index, enum usb_init_type init)
 642 {
 643         switch (index) {
 644         case 0:
 645         case 1:
 646                 ti_usb_phy_uboot_exit(index);
 647                 dwc3_uboot_exit(index);
 648                 dwc3_omap_uboot_exit(index);
 649                 break;
 650         default:
 651                 printf("Invalid Controller Index\n");
 652         }
 653         disable_usb_clocks(index);
 654         return 0;
 655 }
 656
 657 int usb_gadget_handle_interrupts(int index)
 658 {
 659         u32 status;
 660
 661         status = dwc3_omap_uboot_interrupt_status(index);
 662         if (status)
 663                 dwc3_uboot_handle_interrupt(index);
 664
 665         return 0;
 666 }
 667 #endif
 668
 669 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 670 int spl_start_uboot(void)
 671 {
 672         /* break into full u-boot on 'c' */
 673         if (serial_tstc() && serial_getc() == 'c')
 674                 return 1;
 675
 676 #ifdef CONFIG_SPL_ENV_SUPPORT
 677         env_init();
 678         env_relocate_spec();
 679         if (getenv_yesno("boot_os") != 1)
 680                 return 1;
 681 #endif
 682
 683         return 0;
 684 }
 685 #endif
 686
 687 #ifdef CONFIG_DRIVER_TI_CPSW
 688 extern u32 *const omap_si_rev;
 689
 690 static void cpsw_control(int enabled)
 691 {
 692         /* VTP can be added here */
 693
 694         return;
 695 }
 696
 697 static struct cpsw_slave_data cpsw_slaves[] = {
 698         {
 699                 .slave_reg_ofs  = 0x208,
 700                 .sliver_reg_ofs = 0xd80,
 701                 .phy_addr       = 2,
 702         },
 703         {
 704                 .slave_reg_ofs  = 0x308,
 705                 .sliver_reg_ofs = 0xdc0,
 706                 .phy_addr       = 3,
 707         },
 708 };
 709
 710 static struct cpsw_platform_data cpsw_data = {
 711         .mdio_base              = CPSW_MDIO_BASE,
 712         .cpsw_base              = CPSW_BASE,
 713         .mdio_div               = 0xff,
 714         .channels               = 8,
 715         .cpdma_reg_ofs          = 0x800,
 716         .slaves                 = 2,
 717         .slave_data             = cpsw_slaves,
 718         .ale_reg_ofs            = 0xd00,
 719         .ale_entries            = 1024,
 720         .host_port_reg_ofs      = 0x108,
 721         .hw_stats_reg_ofs       = 0x900,
 722         .bd_ram_ofs             = 0x2000,
 723         .mac_control            = (1 << 5),
 724         .control                = cpsw_control,
 725         .host_port_num          = 0,
 726         .version                = CPSW_CTRL_VERSION_2,
 727 };
 728
 729 int board_eth_init(bd_t *bis)
 730 {
 731         int ret;
 732         uint8_t mac_addr[6];
 733         uint32_t mac_hi, mac_lo;
 734         uint32_t ctrl_val;
 735
 736         /* try reading mac address from efuse */
 737         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 738         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 739         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 740         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 741         mac_addr[2] = mac_hi & 0xFF;
 742         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 743         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 744         mac_addr[5] = mac_lo & 0xFF;
 745
 746         if (!getenv("ethaddr")) {
 747                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 748
 749                 if (is_valid_ethaddr(mac_addr))
 750                         eth_setenv_enetaddr("ethaddr", mac_addr);
 751         }
 752
 753         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 754         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 755         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 756         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 757         mac_addr[2] = mac_hi & 0xFF;
 758         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 759         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 760         mac_addr[5] = mac_lo & 0xFF;
 761
 762         if (!getenv("eth1addr")) {
 763                 if (is_valid_ethaddr(mac_addr))
 764                         eth_setenv_enetaddr("eth1addr", mac_addr);
 765         }
 766
 767         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 768         ctrl_val |= 0x22;
 769         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 770
 771         if (*omap_si_rev == DRA722_ES1_0)
 772                 cpsw_data.active_slave = 1;
 773
 774         if (board_is_dra72x_revc_or_later()) {
 775                 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
 776                 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
 777         }
 778
 779         ret = cpsw_register(&cpsw_data);
 780         if (ret < 0)
 781                 printf("Error %d registering CPSW switch\n", ret);
 782
 783         return ret;
 784 }
 785 #endif
 786
 787 #ifdef CONFIG_BOARD_EARLY_INIT_F
 788 /* VTT regulator enable */
 789 static inline void vtt_regulator_enable(void)
 790 {
 791         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 792                 return;
 793
 794         /* Do not enable VTT for DRA722 */
 795         if (is_dra72x())
 796                 return;
 797
 798         /*
 799          * EVM Rev G and later use gpio7_11 for DDR3 termination.
 800          * This is safe enough to do on older revs.
 801          */
 802         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 803         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 804 }
 805
 806 int board_early_init_f(void)
 807 {
 808         vtt_regulator_enable();
 809         return 0;
 810 }
 811 #endif
 812
 813 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 814 int ft_board_setup(void *blob, bd_t *bd)
 815 {
 816         ft_cpu_setup(blob, bd);
 817
 818         return 0;
 819 }
 820 #endif
 821
 822 #ifdef CONFIG_SPL_LOAD_FIT
 823 int board_fit_config_name_match(const char *name)
 824 {
 825         if (is_dra72x() && !strcmp(name, "dra72-evm"))
 826                 return 0;
 827         else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
 828                 return 0;
 829         else
 830                 return -1;
 831 }
 832 #endif