board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <asm/gpio.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/mmc_host_def.h>
  20 #include <asm/arch/sata.h>
  21 #include <environment.h>
  22
  23 #include "mux_data.h"
  24
  25 #ifdef CONFIG_DRIVER_TI_CPSW
  26 #include <cpsw.h>
  27 #endif
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 /* GPIO 7_11 */
  32 #define GPIO_DDR_VTT_EN 203
  33
  34 const struct omap_sysinfo sysinfo = {
  35         "Board: DRA7xx\n"
  36 };
  37
  38 /*
  39  * Adjust I/O delays on the Tx control and data lines of each MAC port. This
  40  * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
  41  * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
  42  * essentially need to counteract the DRA7xx internal delay, and we do this
  43  * by delaying the control and data lines. If not using this PHY, you probably
  44  * don't need to do this stuff!
  45  */
  46 static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
  47 {
  48         int i = 0;
  49         u32 reg_val;
  50         u32 delta;
  51         u32 coarse;
  52         u32 fine;
  53
  54         writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
  55
  56         while(io_dly[i].addr) {
  57                 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
  58                        io_dly[i].addr);
  59                 delta = io_dly[i].dly;
  60                 reg_val = readl(io_dly[i].addr) & 0x3ff;
  61                 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
  62                 coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
  63                 fine = (reg_val & 0x1F) + (delta & 0x1F);
  64                 fine = (fine > 0x1F) ? (0x1F) : (fine);
  65                 reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
  66                                 CFG_IO_DELAY_LOCK_MASK |
  67                                 ((coarse << 5) | (fine));
  68                 writel(reg_val, io_dly[i].addr);
  69                 i++;
  70         }
  71
  72         writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
  73 }
  74
  75 /**
  76  * @brief board_init
  77  *
  78  * @return 0
  79  */
  80 int board_init(void)
  81 {
  82         gpmc_init();
  83         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  84
  85         return 0;
  86 }
  87
  88 int board_late_init(void)
  89 {
  90 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  91         if (omap_revision() == DRA722_ES1_0)
  92                 setenv("board_name", "dra72x");
  93         else
  94                 setenv("board_name", "dra7xx");
  95 #endif
  96         return 0;
  97 }
  98
  99 /**
 100  * @brief misc_init_r - Configure EVM board specific configurations
 101  * such as power configurations, ethernet initialization as phase2 of
 102  * boot sequence
 103  *
 104  * @return 0
 105  */
 106 int misc_init_r(void)
 107 {
 108         return 0;
 109 }
 110
 111 static void do_set_mux32(u32 base,
 112                          struct pad_conf_entry const *array, int size)
 113 {
 114         int i;
 115         struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
 116
 117         for (i = 0; i < size; i++, pad++)
 118                 writel(pad->val, base + pad->offset);
 119 }
 120
 121 void set_muxconf_regs_essential(void)
 122 {
 123         do_set_mux32((*ctrl)->control_padconf_core_base,
 124                      core_padconf_array_essential,
 125                      sizeof(core_padconf_array_essential) /
 126                      sizeof(struct pad_conf_entry));
 127 }
 128
 129 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 130 int board_mmc_init(bd_t *bis)
 131 {
 132         omap_mmc_init(0, 0, 0, -1, -1);
 133         omap_mmc_init(1, 0, 0, -1, -1);
 134         return 0;
 135 }
 136 #endif
 137
 138 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 139 int spl_start_uboot(void)
 140 {
 141         /* break into full u-boot on 'c' */
 142         if (serial_tstc() && serial_getc() == 'c')
 143                 return 1;
 144
 145 #ifdef CONFIG_SPL_ENV_SUPPORT
 146         env_init();
 147         env_relocate_spec();
 148         if (getenv_yesno("boot_os") != 1)
 149                 return 1;
 150 #endif
 151
 152         return 0;
 153 }
 154 #endif
 155
 156 #ifdef CONFIG_DRIVER_TI_CPSW
 157
 158 /* Delay value to add to calibrated value */
 159 #define RGMII0_TXCTL_DLY_VAL            ((0x3 << 5) + 0x8)
 160 #define RGMII0_TXD0_DLY_VAL             ((0x3 << 5) + 0x8)
 161 #define RGMII0_TXD1_DLY_VAL             ((0x3 << 5) + 0x2)
 162 #define RGMII0_TXD2_DLY_VAL             ((0x4 << 5) + 0x0)
 163 #define RGMII0_TXD3_DLY_VAL             ((0x4 << 5) + 0x0)
 164 #define VIN2A_D13_DLY_VAL               ((0x3 << 5) + 0x8)
 165 #define VIN2A_D17_DLY_VAL               ((0x3 << 5) + 0x8)
 166 #define VIN2A_D16_DLY_VAL               ((0x3 << 5) + 0x2)
 167 #define VIN2A_D15_DLY_VAL               ((0x4 << 5) + 0x0)
 168 #define VIN2A_D14_DLY_VAL               ((0x4 << 5) + 0x0)
 169
 170 extern u32 *const omap_si_rev;
 171
 172 static void cpsw_control(int enabled)
 173 {
 174         /* VTP can be added here */
 175
 176         return;
 177 }
 178
 179 static struct cpsw_slave_data cpsw_slaves[] = {
 180         {
 181                 .slave_reg_ofs  = 0x208,
 182                 .sliver_reg_ofs = 0xd80,
 183                 .phy_addr       = 2,
 184         },
 185         {
 186                 .slave_reg_ofs  = 0x308,
 187                 .sliver_reg_ofs = 0xdc0,
 188                 .phy_addr       = 3,
 189         },
 190 };
 191
 192 static struct cpsw_platform_data cpsw_data = {
 193         .mdio_base              = CPSW_MDIO_BASE,
 194         .cpsw_base              = CPSW_BASE,
 195         .mdio_div               = 0xff,
 196         .channels               = 8,
 197         .cpdma_reg_ofs          = 0x800,
 198         .slaves                 = 2,
 199         .slave_data             = cpsw_slaves,
 200         .ale_reg_ofs            = 0xd00,
 201         .ale_entries            = 1024,
 202         .host_port_reg_ofs      = 0x108,
 203         .hw_stats_reg_ofs       = 0x900,
 204         .bd_ram_ofs             = 0x2000,
 205         .mac_control            = (1 << 5),
 206         .control                = cpsw_control,
 207         .host_port_num          = 0,
 208         .version                = CPSW_CTRL_VERSION_2,
 209 };
 210
 211 int board_eth_init(bd_t *bis)
 212 {
 213         int ret;
 214         uint8_t mac_addr[6];
 215         uint32_t mac_hi, mac_lo;
 216         uint32_t ctrl_val;
 217         const struct io_delay io_dly[] = {
 218                 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
 219                 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
 220                 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
 221                 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
 222                 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
 223                 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
 224                 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
 225                 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
 226                 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
 227                 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
 228                 {0}
 229         };
 230
 231         /* Adjust IO delay for RGMII tx path */
 232         dra7xx_adj_io_delay(io_dly);
 233
 234         /* try reading mac address from efuse */
 235         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 236         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 237         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 238         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 239         mac_addr[2] = mac_hi & 0xFF;
 240         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 241         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 242         mac_addr[5] = mac_lo & 0xFF;
 243
 244         if (!getenv("ethaddr")) {
 245                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 246
 247                 if (is_valid_ether_addr(mac_addr))
 248                         eth_setenv_enetaddr("ethaddr", mac_addr);
 249         }
 250
 251         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 252         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 253         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 254         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 255         mac_addr[2] = mac_hi & 0xFF;
 256         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 257         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 258         mac_addr[5] = mac_lo & 0xFF;
 259
 260         if (!getenv("eth1addr")) {
 261                 if (is_valid_ether_addr(mac_addr))
 262                         eth_setenv_enetaddr("eth1addr", mac_addr);
 263         }
 264
 265         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 266         ctrl_val |= 0x22;
 267         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 268
 269         if (*omap_si_rev == DRA722_ES1_0)
 270                 cpsw_data.active_slave = 1;
 271
 272         ret = cpsw_register(&cpsw_data);
 273         if (ret < 0)
 274                 printf("Error %d registering CPSW switch\n", ret);
 275
 276         return ret;
 277 }
 278 #endif
 279
 280 #ifdef CONFIG_BOARD_EARLY_INIT_F
 281 /* VTT regulator enable */
 282 static inline void vtt_regulator_enable(void)
 283 {
 284         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 285                 return;
 286
 287         /* Do not enable VTT for DRA722 */
 288         if (omap_revision() == DRA722_ES1_0)
 289                 return;
 290
 291         /*
 292          * EVM Rev G and later use gpio7_11 for DDR3 termination.
 293          * This is safe enough to do on older revs.
 294          */
 295         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 296         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 297 }
 298
 299 int board_early_init_f(void)
 300 {
 301         vtt_regulator_enable();
 302         return 0;
 303 }
 304 #endif