board/ti/dra7xx/evm.c

   1 /*
   2  * (C) Copyright 2013
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  *
   5  * Lokesh Vutla <lokeshvutla@ti.com>
   6  *
   7  * Based on previous work by:
   8  * Aneesh V       <aneesh@ti.com>
   9  * Steve Sakoman  <steve@sakoman.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <sata.h>
  16 #include <asm/gpio.h>
  17 #include <usb.h>
  18 #include <linux/usb/gadget.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/dra7xx_iodelay.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/sata.h>
  24 #include <environment.h>
  25 #include <dwc3-uboot.h>
  26 #include <dwc3-omap-uboot.h>
  27 #include <ti-usb-phy-uboot.h>
  28
  29 #include "mux_data.h"
  30
  31 #ifdef CONFIG_DRIVER_TI_CPSW
  32 #include <cpsw.h>
  33 #endif
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 /* GPIO 7_11 */
  38 #define GPIO_DDR_VTT_EN 203
  39
  40 const struct omap_sysinfo sysinfo = {
  41         "Board: DRA7xx\n"
  42 };
  43
  44 /**
  45  * @brief board_init
  46  *
  47  * @return 0
  48  */
  49 int board_init(void)
  50 {
  51         gpmc_init();
  52         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  53
  54         return 0;
  55 }
  56
  57 int board_late_init(void)
  58 {
  59 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  60         u32 id[4];
  61
  62         if (omap_revision() == DRA722_ES1_0)
  63                 setenv("board_name", "dra72x");
  64         else
  65                 setenv("board_name", "dra7xx");
  66
  67         id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
  68         id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
  69         usb_set_serial_num_from_die_id(id);
  70 #endif
  71         return 0;
  72 }
  73
  74 void set_muxconf_regs_essential(void)
  75 {
  76         do_set_mux32((*ctrl)->control_padconf_core_base,
  77                      early_padconf, ARRAY_SIZE(early_padconf));
  78 }
  79
  80 #ifdef CONFIG_IODELAY_RECALIBRATION
  81 void recalibrate_iodelay(void)
  82 {
  83         if (is_dra72x()) {
  84                 __recalibrate_iodelay(core_padconf_array_essential,
  85                                       ARRAY_SIZE(core_padconf_array_essential),
  86                                       iodelay_cfg_array,
  87                                       ARRAY_SIZE(iodelay_cfg_array));
  88         } else {
  89                 __recalibrate_iodelay(dra74x_core_padconf_array,
  90                                       ARRAY_SIZE(dra74x_core_padconf_array),
  91                                       dra742_iodelay_cfg_array,
  92                                       ARRAY_SIZE(dra742_iodelay_cfg_array));
  93         }
  94 }
  95 #endif
  96
  97 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
  98 int board_mmc_init(bd_t *bis)
  99 {
 100         omap_mmc_init(0, 0, 0, -1, -1);
 101         omap_mmc_init(1, 0, 0, -1, -1);
 102         return 0;
 103 }
 104 #endif
 105
 106 #ifdef CONFIG_USB_DWC3
 107 static struct dwc3_device usb_otg_ss1 = {
 108         .maximum_speed = USB_SPEED_SUPER,
 109         .base = DRA7_USB_OTG_SS1_BASE,
 110         .tx_fifo_resize = false,
 111         .index = 0,
 112 };
 113
 114 static struct dwc3_omap_device usb_otg_ss1_glue = {
 115         .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
 116         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 117         .vbus_id_status = OMAP_DWC3_VBUS_VALID,
 118         .index = 0,
 119 };
 120
 121 static struct ti_usb_phy_device usb_phy1_device = {
 122         .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
 123         .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
 124         .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
 125         .index = 0,
 126 };
 127
 128 static struct dwc3_device usb_otg_ss2 = {
 129         .maximum_speed = USB_SPEED_SUPER,
 130         .base = DRA7_USB_OTG_SS2_BASE,
 131         .tx_fifo_resize = false,
 132         .index = 1,
 133 };
 134
 135 static struct dwc3_omap_device usb_otg_ss2_glue = {
 136         .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
 137         .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
 138         .vbus_id_status = OMAP_DWC3_VBUS_VALID,
 139         .index = 1,
 140 };
 141
 142 static struct ti_usb_phy_device usb_phy2_device = {
 143         .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
 144         .index = 1,
 145 };
 146
 147 int board_usb_init(int index, enum usb_init_type init)
 148 {
 149         switch (index) {
 150         case 0:
 151                 if (init == USB_INIT_DEVICE) {
 152                         usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 153                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 154                 } else {
 155                         usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
 156                         usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 157                 }
 158
 159                 ti_usb_phy_uboot_init(&usb_phy1_device);
 160                 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
 161                 dwc3_uboot_init(&usb_otg_ss1);
 162                 break;
 163         case 1:
 164                 if (init == USB_INIT_DEVICE) {
 165                         usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 166                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
 167                 } else {
 168                         usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
 169                         usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
 170                 }
 171
 172                 ti_usb_phy_uboot_init(&usb_phy2_device);
 173                 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
 174                 dwc3_uboot_init(&usb_otg_ss2);
 175                 break;
 176         default:
 177                 printf("Invalid Controller Index\n");
 178         }
 179
 180         return 0;
 181 }
 182
 183 int board_usb_cleanup(int index, enum usb_init_type init)
 184 {
 185         switch (index) {
 186         case 0:
 187         case 1:
 188                 ti_usb_phy_uboot_exit(index);
 189                 dwc3_uboot_exit(index);
 190                 dwc3_omap_uboot_exit(index);
 191                 break;
 192         default:
 193                 printf("Invalid Controller Index\n");
 194         }
 195         return 0;
 196 }
 197
 198 int usb_gadget_handle_interrupts(int index)
 199 {
 200         u32 status;
 201
 202         status = dwc3_omap_uboot_interrupt_status(index);
 203         if (status)
 204                 dwc3_uboot_handle_interrupt(index);
 205
 206         return 0;
 207 }
 208 #endif
 209
 210 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
 211 int spl_start_uboot(void)
 212 {
 213         /* break into full u-boot on 'c' */
 214         if (serial_tstc() && serial_getc() == 'c')
 215                 return 1;
 216
 217 #ifdef CONFIG_SPL_ENV_SUPPORT
 218         env_init();
 219         env_relocate_spec();
 220         if (getenv_yesno("boot_os") != 1)
 221                 return 1;
 222 #endif
 223
 224         return 0;
 225 }
 226 #endif
 227
 228 #ifdef CONFIG_DRIVER_TI_CPSW
 229 extern u32 *const omap_si_rev;
 230
 231 static void cpsw_control(int enabled)
 232 {
 233         /* VTP can be added here */
 234
 235         return;
 236 }
 237
 238 static struct cpsw_slave_data cpsw_slaves[] = {
 239         {
 240                 .slave_reg_ofs  = 0x208,
 241                 .sliver_reg_ofs = 0xd80,
 242                 .phy_addr       = 2,
 243         },
 244         {
 245                 .slave_reg_ofs  = 0x308,
 246                 .sliver_reg_ofs = 0xdc0,
 247                 .phy_addr       = 3,
 248         },
 249 };
 250
 251 static struct cpsw_platform_data cpsw_data = {
 252         .mdio_base              = CPSW_MDIO_BASE,
 253         .cpsw_base              = CPSW_BASE,
 254         .mdio_div               = 0xff,
 255         .channels               = 8,
 256         .cpdma_reg_ofs          = 0x800,
 257         .slaves                 = 2,
 258         .slave_data             = cpsw_slaves,
 259         .ale_reg_ofs            = 0xd00,
 260         .ale_entries            = 1024,
 261         .host_port_reg_ofs      = 0x108,
 262         .hw_stats_reg_ofs       = 0x900,
 263         .bd_ram_ofs             = 0x2000,
 264         .mac_control            = (1 << 5),
 265         .control                = cpsw_control,
 266         .host_port_num          = 0,
 267         .version                = CPSW_CTRL_VERSION_2,
 268 };
 269
 270 int board_eth_init(bd_t *bis)
 271 {
 272         int ret;
 273         uint8_t mac_addr[6];
 274         uint32_t mac_hi, mac_lo;
 275         uint32_t ctrl_val;
 276
 277         /* try reading mac address from efuse */
 278         mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
 279         mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
 280         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 281         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 282         mac_addr[2] = mac_hi & 0xFF;
 283         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 284         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 285         mac_addr[5] = mac_lo & 0xFF;
 286
 287         if (!getenv("ethaddr")) {
 288                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 289
 290                 if (is_valid_ethaddr(mac_addr))
 291                         eth_setenv_enetaddr("ethaddr", mac_addr);
 292         }
 293
 294         mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 295         mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 296         mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
 297         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 298         mac_addr[2] = mac_hi & 0xFF;
 299         mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
 300         mac_addr[4] = (mac_lo & 0xFF00) >> 8;
 301         mac_addr[5] = mac_lo & 0xFF;
 302
 303         if (!getenv("eth1addr")) {
 304                 if (is_valid_ethaddr(mac_addr))
 305                         eth_setenv_enetaddr("eth1addr", mac_addr);
 306         }
 307
 308         ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
 309         ctrl_val |= 0x22;
 310         writel(ctrl_val, (*ctrl)->control_core_control_io1);
 311
 312         if (*omap_si_rev == DRA722_ES1_0)
 313                 cpsw_data.active_slave = 1;
 314
 315         ret = cpsw_register(&cpsw_data);
 316         if (ret < 0)
 317                 printf("Error %d registering CPSW switch\n", ret);
 318
 319         return ret;
 320 }
 321 #endif
 322
 323 #ifdef CONFIG_BOARD_EARLY_INIT_F
 324 /* VTT regulator enable */
 325 static inline void vtt_regulator_enable(void)
 326 {
 327         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
 328                 return;
 329
 330         /* Do not enable VTT for DRA722 */
 331         if (omap_revision() == DRA722_ES1_0)
 332                 return;
 333
 334         /*
 335          * EVM Rev G and later use gpio7_11 for DDR3 termination.
 336          * This is safe enough to do on older revs.
 337          */
 338         gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 339         gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 340 }
 341
 342 int board_early_init_f(void)
 343 {
 344         vtt_regulator_enable();
 345         return 0;
 346 }
 347 #endif