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board: ti: dra76-evm: Add the pmic data
[people/ms/u-boot.git] / board / ti / dra7xx / evm.c
1 /*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13 #include <common.h>
14 #include <palmas.h>
15 #include <sata.h>
16 #include <linux/string.h>
17 #include <asm/gpio.h>
18 #include <usb.h>
19 #include <linux/usb/gadget.h>
20 #include <asm/omap_common.h>
21 #include <asm/omap_sec_common.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/dra7xx_iodelay.h>
24 #include <asm/emif.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/sata.h>
28 #include <environment.h>
29 #include <dwc3-uboot.h>
30 #include <dwc3-omap-uboot.h>
31 #include <ti-usb-phy-uboot.h>
32 #include <miiphy.h>
33
34 #include "mux_data.h"
35 #include "../common/board_detect.h"
36
37 #define board_is_dra76x_evm() board_ti_is("DRA76/7x")
38 #define board_is_dra74x_evm() board_ti_is("5777xCPU")
39 #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
40 #define board_is_dra71x_evm() board_ti_is("DRA79x,D")
41 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
42 (strncmp("H", board_ti_get_rev(), 1) <= 0))
43 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
44 (strncmp("C", board_ti_get_rev(), 1) <= 0))
45 #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
46 board_ti_get_emif2_size()
47
48 #ifdef CONFIG_DRIVER_TI_CPSW
49 #include <cpsw.h>
50 #endif
51
52 DECLARE_GLOBAL_DATA_PTR;
53
54 /* GPIO 7_11 */
55 #define GPIO_DDR_VTT_EN 203
56
57 #define SYSINFO_BOARD_NAME_MAX_LEN 37
58
59 const struct omap_sysinfo sysinfo = {
60 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
61 };
62
63 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
64 .sdram_config_init = 0x61851ab2,
65 .sdram_config = 0x61851ab2,
66 .sdram_config2 = 0x08000000,
67 .ref_ctrl = 0x000040F1,
68 .ref_ctrl_final = 0x00001035,
69 .sdram_tim1 = 0xCCCF36B3,
70 .sdram_tim2 = 0x308F7FDA,
71 .sdram_tim3 = 0x427F88A8,
72 .read_idle_ctrl = 0x00050000,
73 .zq_config = 0x0007190B,
74 .temp_alert_config = 0x00000000,
75 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
76 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
77 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
78 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
79 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
80 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
81 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
82 .emif_rd_wr_lvl_rmp_win = 0x00000000,
83 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
84 .emif_rd_wr_lvl_ctl = 0x00000000,
85 .emif_rd_wr_exec_thresh = 0x00000305
86 };
87
88 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
89 .sdram_config_init = 0x61851B32,
90 .sdram_config = 0x61851B32,
91 .sdram_config2 = 0x08000000,
92 .ref_ctrl = 0x000040F1,
93 .ref_ctrl_final = 0x00001035,
94 .sdram_tim1 = 0xCCCF36B3,
95 .sdram_tim2 = 0x308F7FDA,
96 .sdram_tim3 = 0x427F88A8,
97 .read_idle_ctrl = 0x00050000,
98 .zq_config = 0x0007190B,
99 .temp_alert_config = 0x00000000,
100 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
101 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
102 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
103 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
104 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
105 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
106 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
107 .emif_rd_wr_lvl_rmp_win = 0x00000000,
108 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
109 .emif_rd_wr_lvl_ctl = 0x00000000,
110 .emif_rd_wr_exec_thresh = 0x00000305
111 };
112
113 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
114 .sdram_config_init = 0x61862B32,
115 .sdram_config = 0x61862B32,
116 .sdram_config2 = 0x08000000,
117 .ref_ctrl = 0x0000514C,
118 .ref_ctrl_final = 0x0000144A,
119 .sdram_tim1 = 0xD113781C,
120 .sdram_tim2 = 0x30717FE3,
121 .sdram_tim3 = 0x409F86A8,
122 .read_idle_ctrl = 0x00050000,
123 .zq_config = 0x5007190B,
124 .temp_alert_config = 0x00000000,
125 .emif_ddr_phy_ctlr_1_init = 0x0024400D,
126 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
127 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
128 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
129 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
130 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
131 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
132 .emif_rd_wr_lvl_rmp_win = 0x00000000,
133 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
134 .emif_rd_wr_lvl_ctl = 0x00000000,
135 .emif_rd_wr_exec_thresh = 0x00000305
136 };
137
138 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
139 .sdram_config_init = 0x61862BB2,
140 .sdram_config = 0x61862BB2,
141 .sdram_config2 = 0x00000000,
142 .ref_ctrl = 0x0000514D,
143 .ref_ctrl_final = 0x0000144A,
144 .sdram_tim1 = 0xD1137824,
145 .sdram_tim2 = 0x30B37FE3,
146 .sdram_tim3 = 0x409F8AD8,
147 .read_idle_ctrl = 0x00050000,
148 .zq_config = 0x5007190B,
149 .temp_alert_config = 0x00000000,
150 .emif_ddr_phy_ctlr_1_init = 0x0824400E,
151 .emif_ddr_phy_ctlr_1 = 0x0E24400E,
152 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
153 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
154 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
155 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
156 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
157 .emif_rd_wr_lvl_rmp_win = 0x00000000,
158 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
159 .emif_rd_wr_lvl_ctl = 0x00000000,
160 .emif_rd_wr_exec_thresh = 0x00000305
161 };
162
163 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
164 .sdram_config_init = 0x61851ab2,
165 .sdram_config = 0x61851ab2,
166 .sdram_config2 = 0x08000000,
167 .ref_ctrl = 0x000040F1,
168 .ref_ctrl_final = 0x00001035,
169 .sdram_tim1 = 0xCCCF36B3,
170 .sdram_tim2 = 0x30BF7FDA,
171 .sdram_tim3 = 0x427F8BA8,
172 .read_idle_ctrl = 0x00050000,
173 .zq_config = 0x0007190B,
174 .temp_alert_config = 0x00000000,
175 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
176 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
177 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
178 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
179 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
180 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
181 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
182 .emif_rd_wr_lvl_rmp_win = 0x00000000,
183 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
184 .emif_rd_wr_lvl_ctl = 0x00000000,
185 .emif_rd_wr_exec_thresh = 0x00000305
186 };
187
188 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
189 .sdram_config_init = 0x61851B32,
190 .sdram_config = 0x61851B32,
191 .sdram_config2 = 0x08000000,
192 .ref_ctrl = 0x000040F1,
193 .ref_ctrl_final = 0x00001035,
194 .sdram_tim1 = 0xCCCF36B3,
195 .sdram_tim2 = 0x308F7FDA,
196 .sdram_tim3 = 0x427F88A8,
197 .read_idle_ctrl = 0x00050000,
198 .zq_config = 0x0007190B,
199 .temp_alert_config = 0x00000000,
200 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
201 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
202 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
203 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
204 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
205 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
206 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
207 .emif_rd_wr_lvl_rmp_win = 0x00000000,
208 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
209 .emif_rd_wr_lvl_ctl = 0x00000000,
210 .emif_rd_wr_exec_thresh = 0x00000305
211 };
212
213 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
214 {
215 u64 ram_size;
216
217 ram_size = board_ti_get_emif_size();
218
219 switch (omap_revision()) {
220 case DRA752_ES1_0:
221 case DRA752_ES1_1:
222 case DRA752_ES2_0:
223 switch (emif_nr) {
224 case 1:
225 if (ram_size > CONFIG_MAX_MEM_MAPPED)
226 *regs = &emif1_ddr3_532_mhz_1cs_2G;
227 else
228 *regs = &emif1_ddr3_532_mhz_1cs;
229 break;
230 case 2:
231 if (ram_size > CONFIG_MAX_MEM_MAPPED)
232 *regs = &emif2_ddr3_532_mhz_1cs_2G;
233 else
234 *regs = &emif2_ddr3_532_mhz_1cs;
235 break;
236 }
237 break;
238 case DRA722_ES1_0:
239 case DRA722_ES2_0:
240 if (ram_size < CONFIG_MAX_MEM_MAPPED)
241 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
242 else
243 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
244 break;
245 default:
246 *regs = &emif1_ddr3_532_mhz_1cs;
247 }
248 }
249
250 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
251 .dmm_lisa_map_0 = 0x0,
252 .dmm_lisa_map_1 = 0x80640300,
253 .dmm_lisa_map_2 = 0xC0500220,
254 .dmm_lisa_map_3 = 0xFF020100,
255 .is_ma_present = 0x1
256 };
257
258 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
259 .dmm_lisa_map_0 = 0x0,
260 .dmm_lisa_map_1 = 0x0,
261 .dmm_lisa_map_2 = 0x80600100,
262 .dmm_lisa_map_3 = 0xFF020100,
263 .is_ma_present = 0x1
264 };
265
266 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
267 .dmm_lisa_map_0 = 0x0,
268 .dmm_lisa_map_1 = 0x0,
269 .dmm_lisa_map_2 = 0x80740300,
270 .dmm_lisa_map_3 = 0xFF020100,
271 .is_ma_present = 0x1
272 };
273
274 /*
275 * DRA722 EVM EMIF1 2GB CONFIGURATION
276 * EMIF1 4 devices of 512Mb x 8 Micron
277 */
278 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
279 .dmm_lisa_map_0 = 0x0,
280 .dmm_lisa_map_1 = 0x0,
281 .dmm_lisa_map_2 = 0x80700100,
282 .dmm_lisa_map_3 = 0xFF020100,
283 .is_ma_present = 0x1
284 };
285
286 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
287 {
288 u64 ram_size;
289
290 ram_size = board_ti_get_emif_size();
291
292 switch (omap_revision()) {
293 case DRA752_ES1_0:
294 case DRA752_ES1_1:
295 case DRA752_ES2_0:
296 if (ram_size > CONFIG_MAX_MEM_MAPPED)
297 *dmm_lisa_regs = &lisa_map_dra7_2GB;
298 else
299 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
300 break;
301 case DRA722_ES1_0:
302 case DRA722_ES2_0:
303 default:
304 if (ram_size < CONFIG_MAX_MEM_MAPPED)
305 *dmm_lisa_regs = &lisa_map_2G_x_2;
306 else
307 *dmm_lisa_regs = &lisa_map_2G_x_4;
308 break;
309 }
310 }
311
312 struct vcores_data dra752_volts = {
313 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
314 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
315 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
316 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
317 .mpu.pmic = &tps659038,
318 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
319
320 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
321 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
322 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
323 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
324 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
325 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
326 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
327 .eve.addr = TPS659038_REG_ADDR_SMPS45,
328 .eve.pmic = &tps659038,
329 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
330
331 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
332 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
333 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
334 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
335 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
336 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
337 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
338 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
339 .gpu.pmic = &tps659038,
340 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
341
342 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
343 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
344 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
345 .core.addr = TPS659038_REG_ADDR_SMPS7,
346 .core.pmic = &tps659038,
347
348 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
349 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
350 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
351 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
352 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
353 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
354 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
355 .iva.addr = TPS659038_REG_ADDR_SMPS8,
356 .iva.pmic = &tps659038,
357 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
358 };
359
360 struct vcores_data dra76x_volts = {
361 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
362 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
363 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
364 .mpu.addr = LP87565_REG_ADDR_BUCK01,
365 .mpu.pmic = &lp87565,
366 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
367
368 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
369 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
370 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
371 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
372 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
373 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
374 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
375 .eve.addr = TPS65917_REG_ADDR_SMPS1,
376 .eve.pmic = &tps659038,
377 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
378
379 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
380 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
381 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
382 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
383 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
384 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
385 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
386 .gpu.addr = LP87565_REG_ADDR_BUCK23,
387 .gpu.pmic = &lp87565,
388 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
389
390 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
391 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
392 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
393 .core.addr = TPS65917_REG_ADDR_SMPS3,
394 .core.pmic = &tps659038,
395
396 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
397 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
398 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
399 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
400 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
401 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
402 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
403 .iva.addr = TPS65917_REG_ADDR_SMPS4,
404 .iva.pmic = &tps659038,
405 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
406 };
407
408 struct vcores_data dra722_volts = {
409 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
410 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
411 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
412 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
413 .mpu.pmic = &tps659038,
414 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
415
416 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
417 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
418 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
419 .core.addr = TPS65917_REG_ADDR_SMPS2,
420 .core.pmic = &tps659038,
421
422 /*
423 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
424 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
425 */
426 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
427 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
428 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
429 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
430 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
431 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
432 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
433 .gpu.addr = TPS65917_REG_ADDR_SMPS3,
434 .gpu.pmic = &tps659038,
435 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
436
437 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
438 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
439 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
440 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
441 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
442 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
443 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
444 .eve.addr = TPS65917_REG_ADDR_SMPS3,
445 .eve.pmic = &tps659038,
446 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
447
448 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
449 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
450 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
451 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
452 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
453 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
454 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
455 .iva.addr = TPS65917_REG_ADDR_SMPS3,
456 .iva.pmic = &tps659038,
457 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
458 };
459
460 struct vcores_data dra718_volts = {
461 /*
462 * In the case of dra71x GPU MPU and CORE
463 * are all powered up by BUCK0 of LP873X PMIC
464 */
465 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
466 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
467 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
468 .mpu.addr = LP873X_REG_ADDR_BUCK0,
469 .mpu.pmic = &lp8733,
470 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
471
472 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
473 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
474 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
475 .core.addr = LP873X_REG_ADDR_BUCK0,
476 .core.pmic = &lp8733,
477
478 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
479 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
480 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
481 .gpu.addr = LP873X_REG_ADDR_BUCK0,
482 .gpu.pmic = &lp8733,
483 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
484
485 /*
486 * The DSPEVE and IVA rails are grouped on DRA71x-evm
487 * and are powered by BUCK1 of LP873X PMIC
488 */
489 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
490 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
491 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
492 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
493 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
494 .eve.addr = LP873X_REG_ADDR_BUCK1,
495 .eve.pmic = &lp8733,
496 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
497
498 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
499 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
500 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
501 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
502 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
503 .iva.addr = LP873X_REG_ADDR_BUCK1,
504 .iva.pmic = &lp8733,
505 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
506 };
507
508 int get_voltrail_opp(int rail_offset)
509 {
510 int opp;
511
512 switch (rail_offset) {
513 case VOLT_MPU:
514 opp = DRA7_MPU_OPP;
515 /* DRA71x supports only OPP_NOM for MPU */
516 if (board_is_dra71x_evm())
517 opp = OPP_NOM;
518 break;
519 case VOLT_CORE:
520 opp = DRA7_CORE_OPP;
521 /* DRA71x supports only OPP_NOM for CORE */
522 if (board_is_dra71x_evm())
523 opp = OPP_NOM;
524 break;
525 case VOLT_GPU:
526 opp = DRA7_GPU_OPP;
527 /* DRA71x supports only OPP_NOM for GPU */
528 if (board_is_dra71x_evm())
529 opp = OPP_NOM;
530 break;
531 case VOLT_EVE:
532 opp = DRA7_DSPEVE_OPP;
533 /*
534 * DRA71x does not support OPP_OD for EVE.
535 * If OPP_OD is selected by menuconfig, fallback
536 * to OPP_NOM.
537 */
538 if (board_is_dra71x_evm() && opp == OPP_OD)
539 opp = OPP_NOM;
540 break;
541 case VOLT_IVA:
542 opp = DRA7_IVA_OPP;
543 /*
544 * DRA71x does not support OPP_OD for IVA.
545 * If OPP_OD is selected by menuconfig, fallback
546 * to OPP_NOM.
547 */
548 if (board_is_dra71x_evm() && opp == OPP_OD)
549 opp = OPP_NOM;
550 break;
551 default:
552 opp = OPP_NOM;
553 }
554
555 return opp;
556 }
557
558 /**
559 * @brief board_init
560 *
561 * @return 0
562 */
563 int board_init(void)
564 {
565 gpmc_init();
566 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
567
568 return 0;
569 }
570
571 int dram_init_banksize(void)
572 {
573 u64 ram_size;
574
575 ram_size = board_ti_get_emif_size();
576
577 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
578 gd->bd->bi_dram[0].size = get_effective_memsize();
579 if (ram_size > CONFIG_MAX_MEM_MAPPED) {
580 gd->bd->bi_dram[1].start = 0x200000000;
581 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
582 }
583
584 return 0;
585 }
586
587 int board_late_init(void)
588 {
589 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
590 char *name = "unknown";
591
592 if (is_dra72x()) {
593 if (board_is_dra72x_revc_or_later())
594 name = "dra72x-revc";
595 else if (board_is_dra71x_evm())
596 name = "dra71x";
597 else
598 name = "dra72x";
599 } else if (is_dra76x()) {
600 name = "dra76x";
601 } else {
602 name = "dra7xx";
603 }
604
605 set_board_info_env(name);
606
607 /*
608 * Default FIT boot on HS devices. Non FIT images are not allowed
609 * on HS devices.
610 */
611 if (get_device_type() == HS_DEVICE)
612 env_set("boot_fit", "1");
613
614 omap_die_id_serial();
615 omap_set_fastboot_vars();
616 #endif
617 return 0;
618 }
619
620 #ifdef CONFIG_SPL_BUILD
621 void do_board_detect(void)
622 {
623 int rc;
624
625 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
626 CONFIG_EEPROM_CHIP_ADDRESS);
627 if (rc)
628 printf("ti_i2c_eeprom_init failed %d\n", rc);
629 }
630
631 #else
632
633 void do_board_detect(void)
634 {
635 char *bname = NULL;
636 int rc;
637
638 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
639 CONFIG_EEPROM_CHIP_ADDRESS);
640 if (rc)
641 printf("ti_i2c_eeprom_init failed %d\n", rc);
642
643 if (board_is_dra74x_evm()) {
644 bname = "DRA74x EVM";
645 } else if (board_is_dra72x_evm()) {
646 bname = "DRA72x EVM";
647 } else if (board_is_dra71x_evm()) {
648 bname = "DRA71x EVM";
649 } else if (board_is_dra76x_evm()) {
650 bname = "DRA76x EVM";
651 } else {
652 /* If EEPROM is not populated */
653 if (is_dra72x())
654 bname = "DRA72x EVM";
655 else
656 bname = "DRA74x EVM";
657 }
658
659 if (bname)
660 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
661 "Board: %s REV %s\n", bname, board_ti_get_rev());
662 }
663 #endif /* CONFIG_SPL_BUILD */
664
665 void vcores_init(void)
666 {
667 if (board_is_dra74x_evm()) {
668 *omap_vcores = &dra752_volts;
669 } else if (board_is_dra72x_evm()) {
670 *omap_vcores = &dra722_volts;
671 } else if (board_is_dra71x_evm()) {
672 *omap_vcores = &dra718_volts;
673 } else if (board_is_dra76x_evm()) {
674 *omap_vcores = &dra76x_volts;
675 } else {
676 /* If EEPROM is not populated */
677 if (is_dra72x())
678 *omap_vcores = &dra722_volts;
679 else
680 *omap_vcores = &dra752_volts;
681 }
682 }
683
684 void set_muxconf_regs(void)
685 {
686 do_set_mux32((*ctrl)->control_padconf_core_base,
687 early_padconf, ARRAY_SIZE(early_padconf));
688 }
689
690 #ifdef CONFIG_IODELAY_RECALIBRATION
691 void recalibrate_iodelay(void)
692 {
693 struct pad_conf_entry const *pads, *delta_pads = NULL;
694 struct iodelay_cfg_entry const *iodelay;
695 int npads, niodelays, delta_npads = 0;
696 int ret;
697
698 switch (omap_revision()) {
699 case DRA722_ES1_0:
700 case DRA722_ES2_0:
701 pads = dra72x_core_padconf_array_common;
702 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
703 if (board_is_dra71x_evm()) {
704 pads = dra71x_core_padconf_array;
705 npads = ARRAY_SIZE(dra71x_core_padconf_array);
706 iodelay = dra71_iodelay_cfg_array;
707 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
708 } else if (board_is_dra72x_revc_or_later()) {
709 delta_pads = dra72x_rgmii_padconf_array_revc;
710 delta_npads =
711 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
712 iodelay = dra72_iodelay_cfg_array_revc;
713 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
714 } else {
715 delta_pads = dra72x_rgmii_padconf_array_revb;
716 delta_npads =
717 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
718 iodelay = dra72_iodelay_cfg_array_revb;
719 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
720 }
721 break;
722 case DRA752_ES1_0:
723 case DRA752_ES1_1:
724 pads = dra74x_core_padconf_array;
725 npads = ARRAY_SIZE(dra74x_core_padconf_array);
726 iodelay = dra742_es1_1_iodelay_cfg_array;
727 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
728 break;
729 default:
730 case DRA752_ES2_0:
731 pads = dra74x_core_padconf_array;
732 npads = ARRAY_SIZE(dra74x_core_padconf_array);
733 iodelay = dra742_es2_0_iodelay_cfg_array;
734 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
735 /* Setup port1 and port2 for rgmii with 'no-id' mode */
736 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
737 RGMII1_ID_MODE_N_MASK);
738 break;
739 }
740 /* Setup I/O isolation */
741 ret = __recalibrate_iodelay_start();
742 if (ret)
743 goto err;
744
745 /* Do the muxing here */
746 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
747
748 /* Now do the weird minor deltas that should be safe */
749 if (delta_npads)
750 do_set_mux32((*ctrl)->control_padconf_core_base,
751 delta_pads, delta_npads);
752
753 /* Setup IOdelay configuration */
754 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
755 err:
756 /* Closeup.. remove isolation */
757 __recalibrate_iodelay_end(ret);
758 }
759 #endif
760
761 #if defined(CONFIG_MMC)
762 int board_mmc_init(bd_t *bis)
763 {
764 omap_mmc_init(0, 0, 0, -1, -1);
765 omap_mmc_init(1, 0, 0, -1, -1);
766 return 0;
767 }
768
769 void board_mmc_poweron_ldo(uint voltage)
770 {
771 if (board_is_dra71x_evm()) {
772 if (voltage == LDO_VOLT_3V0)
773 voltage = 0x19;
774 else if (voltage == LDO_VOLT_1V8)
775 voltage = 0xa;
776 lp873x_mmc1_poweron_ldo(voltage);
777 } else {
778 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
779 }
780 }
781 #endif
782
783 #ifdef CONFIG_USB_DWC3
784 static struct dwc3_device usb_otg_ss1 = {
785 .maximum_speed = USB_SPEED_SUPER,
786 .base = DRA7_USB_OTG_SS1_BASE,
787 .tx_fifo_resize = false,
788 .index = 0,
789 };
790
791 static struct dwc3_omap_device usb_otg_ss1_glue = {
792 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
793 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
794 .index = 0,
795 };
796
797 static struct ti_usb_phy_device usb_phy1_device = {
798 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
799 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
800 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
801 .index = 0,
802 };
803
804 static struct dwc3_device usb_otg_ss2 = {
805 .maximum_speed = USB_SPEED_SUPER,
806 .base = DRA7_USB_OTG_SS2_BASE,
807 .tx_fifo_resize = false,
808 .index = 1,
809 };
810
811 static struct dwc3_omap_device usb_otg_ss2_glue = {
812 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
813 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
814 .index = 1,
815 };
816
817 static struct ti_usb_phy_device usb_phy2_device = {
818 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
819 .index = 1,
820 };
821
822 int omap_xhci_board_usb_init(int index, enum usb_init_type init)
823 {
824 enable_usb_clocks(index);
825 switch (index) {
826 case 0:
827 if (init == USB_INIT_DEVICE) {
828 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
829 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
830 } else {
831 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
832 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
833 }
834
835 ti_usb_phy_uboot_init(&usb_phy1_device);
836 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
837 dwc3_uboot_init(&usb_otg_ss1);
838 break;
839 case 1:
840 if (init == USB_INIT_DEVICE) {
841 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
842 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
843 } else {
844 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
845 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
846 }
847
848 ti_usb_phy_uboot_init(&usb_phy2_device);
849 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
850 dwc3_uboot_init(&usb_otg_ss2);
851 break;
852 default:
853 printf("Invalid Controller Index\n");
854 }
855
856 return 0;
857 }
858
859 int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
860 {
861 switch (index) {
862 case 0:
863 case 1:
864 ti_usb_phy_uboot_exit(index);
865 dwc3_uboot_exit(index);
866 dwc3_omap_uboot_exit(index);
867 break;
868 default:
869 printf("Invalid Controller Index\n");
870 }
871 disable_usb_clocks(index);
872 return 0;
873 }
874
875 int usb_gadget_handle_interrupts(int index)
876 {
877 u32 status;
878
879 status = dwc3_omap_uboot_interrupt_status(index);
880 if (status)
881 dwc3_uboot_handle_interrupt(index);
882
883 return 0;
884 }
885 #endif
886
887 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
888 int spl_start_uboot(void)
889 {
890 /* break into full u-boot on 'c' */
891 if (serial_tstc() && serial_getc() == 'c')
892 return 1;
893
894 #ifdef CONFIG_SPL_ENV_SUPPORT
895 env_init();
896 env_load();
897 if (env_get_yesno("boot_os") != 1)
898 return 1;
899 #endif
900
901 return 0;
902 }
903 #endif
904
905 #ifdef CONFIG_DRIVER_TI_CPSW
906 extern u32 *const omap_si_rev;
907
908 static void cpsw_control(int enabled)
909 {
910 /* VTP can be added here */
911
912 return;
913 }
914
915 static struct cpsw_slave_data cpsw_slaves[] = {
916 {
917 .slave_reg_ofs = 0x208,
918 .sliver_reg_ofs = 0xd80,
919 .phy_addr = 2,
920 },
921 {
922 .slave_reg_ofs = 0x308,
923 .sliver_reg_ofs = 0xdc0,
924 .phy_addr = 3,
925 },
926 };
927
928 static struct cpsw_platform_data cpsw_data = {
929 .mdio_base = CPSW_MDIO_BASE,
930 .cpsw_base = CPSW_BASE,
931 .mdio_div = 0xff,
932 .channels = 8,
933 .cpdma_reg_ofs = 0x800,
934 .slaves = 2,
935 .slave_data = cpsw_slaves,
936 .ale_reg_ofs = 0xd00,
937 .ale_entries = 1024,
938 .host_port_reg_ofs = 0x108,
939 .hw_stats_reg_ofs = 0x900,
940 .bd_ram_ofs = 0x2000,
941 .mac_control = (1 << 5),
942 .control = cpsw_control,
943 .host_port_num = 0,
944 .version = CPSW_CTRL_VERSION_2,
945 };
946
947 int board_eth_init(bd_t *bis)
948 {
949 int ret;
950 uint8_t mac_addr[6];
951 uint32_t mac_hi, mac_lo;
952 uint32_t ctrl_val;
953
954 /* try reading mac address from efuse */
955 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
956 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
957 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
958 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
959 mac_addr[2] = mac_hi & 0xFF;
960 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
961 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
962 mac_addr[5] = mac_lo & 0xFF;
963
964 if (!env_get("ethaddr")) {
965 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
966
967 if (is_valid_ethaddr(mac_addr))
968 eth_env_set_enetaddr("ethaddr", mac_addr);
969 }
970
971 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
972 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
973 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
974 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
975 mac_addr[2] = mac_hi & 0xFF;
976 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
977 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
978 mac_addr[5] = mac_lo & 0xFF;
979
980 if (!env_get("eth1addr")) {
981 if (is_valid_ethaddr(mac_addr))
982 eth_env_set_enetaddr("eth1addr", mac_addr);
983 }
984
985 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
986 ctrl_val |= 0x22;
987 writel(ctrl_val, (*ctrl)->control_core_control_io1);
988
989 if (*omap_si_rev == DRA722_ES1_0)
990 cpsw_data.active_slave = 1;
991
992 if (board_is_dra72x_revc_or_later()) {
993 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
994 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
995 }
996
997 ret = cpsw_register(&cpsw_data);
998 if (ret < 0)
999 printf("Error %d registering CPSW switch\n", ret);
1000
1001 return ret;
1002 }
1003 #endif
1004
1005 #ifdef CONFIG_BOARD_EARLY_INIT_F
1006 /* VTT regulator enable */
1007 static inline void vtt_regulator_enable(void)
1008 {
1009 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1010 return;
1011
1012 /* Do not enable VTT for DRA722 */
1013 if (is_dra72x())
1014 return;
1015
1016 /*
1017 * EVM Rev G and later use gpio7_11 for DDR3 termination.
1018 * This is safe enough to do on older revs.
1019 */
1020 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1021 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1022 }
1023
1024 int board_early_init_f(void)
1025 {
1026 vtt_regulator_enable();
1027 return 0;
1028 }
1029 #endif
1030
1031 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1032 int ft_board_setup(void *blob, bd_t *bd)
1033 {
1034 ft_cpu_setup(blob, bd);
1035
1036 return 0;
1037 }
1038 #endif
1039
1040 #ifdef CONFIG_SPL_LOAD_FIT
1041 int board_fit_config_name_match(const char *name)
1042 {
1043 if (is_dra72x()) {
1044 if (board_is_dra71x_evm()) {
1045 if (!strcmp(name, "dra71-evm"))
1046 return 0;
1047 }else if(board_is_dra72x_revc_or_later()) {
1048 if (!strcmp(name, "dra72-evm-revc"))
1049 return 0;
1050 } else if (!strcmp(name, "dra72-evm")) {
1051 return 0;
1052 }
1053 } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
1054 return 0;
1055 }
1056
1057 return -1;
1058 }
1059 #endif
1060
1061 #ifdef CONFIG_TI_SECURE_DEVICE
1062 void board_fit_image_post_process(void **p_image, size_t *p_size)
1063 {
1064 secure_boot_verify_image(p_image, p_size);
1065 }
1066
1067 void board_tee_image_process(ulong tee_image, size_t tee_size)
1068 {
1069 secure_tee_install((u32)tee_image);
1070 }
1071
1072 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
1073 #endif
"Das U-Boot" Source Tree