board/ti/ks2_evm/ddr3_k2hk.c

   1 /*
   2  * Keystone2: DDR3 initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include "ddr3_cfg.h"
  12 #include <asm/arch/ddr3.h>
  13 #include <asm/arch/hardware.h>
  14
  15 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
  16 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
  17
  18 u32 ddr3_init(void)
  19 {
  20         char dimm_name[32];
  21         u32 ddr3_size;
  22
  23         ddr3_get_dimm_params(dimm_name);
  24
  25         printf("Detected SO-DIMM [%s]\n", dimm_name);
  26
  27         if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
  28                 init_pll(&ddr3a_400);
  29                 if (cpu_revision() > 0) {
  30                         if (cpu_revision() > 1) {
  31                                 /* PG 2.0 */
  32                                 /* Reset DDR3A PHY after PLL enabled */
  33                                 ddr3_reset_ddrphy();
  34                                 ddr3phy_1600_8g.zq0cr1 |= 0x10000;
  35                                 ddr3phy_1600_8g.zq1cr1 |= 0x10000;
  36                                 ddr3phy_1600_8g.zq2cr1 |= 0x10000;
  37                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  38                                                  &ddr3phy_1600_8g);
  39                         } else {
  40                                 /* PG 1.1 */
  41                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  42                                                  &ddr3phy_1600_8g);
  43                         }
  44
  45                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  46                                           &ddr3_1600_8g);
  47                         printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
  48                         ddr3_size = 8;
  49                 } else {
  50                         ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
  51                         ddr3_1600_8g.sdcfg |= 0x1000;
  52                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  53                                           &ddr3_1600_8g);
  54                         printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
  55                         ddr3_size = 4;
  56                 }
  57         } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
  58                 init_pll(&ddr3a_333);
  59                 if (cpu_revision() > 0) {
  60                         if (cpu_revision() > 1) {
  61                                 /* PG 2.0 */
  62                                 /* Reset DDR3A PHY after PLL enabled */
  63                                 ddr3_reset_ddrphy();
  64                                 ddr3phy_1333_2g.zq0cr1 |= 0x10000;
  65                                 ddr3phy_1333_2g.zq1cr1 |= 0x10000;
  66                                 ddr3phy_1333_2g.zq2cr1 |= 0x10000;
  67                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  68                                                  &ddr3phy_1333_2g);
  69                         } else {
  70                                 /* PG 1.1 */
  71                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  72                                                  &ddr3phy_1333_2g);
  73                         }
  74                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  75                                           &ddr3_1333_2g);
  76                         ddr3_size = 2;
  77                         printf("DRAM:  2 GiB");
  78                 } else {
  79                         ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
  80                         ddr3_1333_2g.sdcfg |= 0x1000;
  81                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  82                                           &ddr3_1333_2g);
  83                         ddr3_size = 1;
  84                         printf("DRAM:  1 GiB");
  85                 }
  86         } else {
  87                 printf("Unknown SO-DIMM. Cannot configure DDR3\n");
  88                 while (1)
  89                         ;
  90         }
  91
  92         /* Apply the workaround for PG 1.0 and 1.1 Silicons */
  93         if (cpu_revision() <= 1)
  94                 ddr3_err_reset_workaround();
  95
  96         return ddr3_size;
  97 }