board/ti/omap5912osk/lowlevel_init.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2003
   5  * Texas Instruments, <www.ti.com>
   6  * Kshitij Gupta <Kshitij@ti.com>
   7  *
   8  * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
   9  *
  10  * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <config.h>
  15 #include <version.h>
  16
  17 #if defined(CONFIG_OMAP1610)
  18 #include <./configs/omap1510.h>
  19 #endif
  20
  21
  22 _TEXT_BASE:
  23         .word   CONFIG_SYS_TEXT_BASE    /* sdram load addr from config.mk */
  24
  25 .globl lowlevel_init
  26 lowlevel_init:
  27
  28         /*------------------------------------------------------*
  29          * Ensure i-cache is enabled                            *
  30          * To configure TC regs without fetching instruction    *
  31          *------------------------------------------------------*/
  32         mrc     p15, 0, r0, c1, c0
  33         orr     r0, r0, #0x1000
  34         mcr     p15, 0, r0, c1, c0
  35
  36         /*------------------------------------------------------*
  37          *mask all IRQs by setting all bits in the INTMR default*
  38          *------------------------------------------------------*/
  39         mov     r1, #0xffffffff
  40         ldr     r0, =REG_IHL1_MIR
  41         str     r1, [r0]
  42         ldr     r0, =REG_IHL2_MIR
  43         str     r1, [r0]
  44
  45         /*------------------------------------------------------*
  46          * Set up ARM CLM registers (IDLECT1)                   *
  47          *------------------------------------------------------*/
  48         ldr     r0,     REG_ARM_IDLECT1
  49         ldr     r1,     VAL_ARM_IDLECT1
  50         str     r1,     [r0]
  51
  52         /*------------------------------------------------------*
  53          * Set up ARM CLM registers (IDLECT2)                   *
  54          *------------------------------------------------------*/
  55         ldr     r0,     REG_ARM_IDLECT2
  56         ldr     r1,     VAL_ARM_IDLECT2
  57         str     r1,     [r0]
  58
  59         /*------------------------------------------------------*
  60          * Set up ARM CLM registers (IDLECT3)                   *
  61          *------------------------------------------------------*/
  62         ldr     r0,     REG_ARM_IDLECT3
  63         ldr     r1,     VAL_ARM_IDLECT3
  64         str     r1,     [r0]
  65
  66         mov     r1,     #0x01               /* PER_EN bit */
  67         ldr     r0,     REG_ARM_RSTCT2
  68         strh    r1,     [r0]            /* CLKM; Peripheral reset. */
  69
  70         /* Set CLKM to Sync-Scalable */
  71         mov     r1,     #0x1000
  72         ldr     r0,     REG_ARM_SYSST
  73
  74         mov     r2,     #0
  75 1:      cmp     r2,     #1
  76         streqh  r1,     [r0]
  77         add     r2,     r2,     #1
  78         cmp     r2,     #0x100              /* wait for any bubbles to finish */
  79         bne     1b
  80
  81         ldr     r1,     VAL_ARM_CKCTL
  82         ldr     r0,     REG_ARM_CKCTL
  83         strh    r1,     [r0]
  84
  85         /* a few nops to let settle */
  86         nop
  87         nop
  88         nop
  89         nop
  90         nop
  91         nop
  92         nop
  93         nop
  94         nop
  95         nop
  96
  97         /* setup DPLL 1 */
  98         /* Ramp up the clock to 96Mhz */
  99         ldr     r1,     VAL_DPLL1_CTL
 100         ldr     r0,     REG_DPLL1_CTL
 101         strh    r1,     [r0]
 102         ands    r1,     r1,     #0x10       /* Check if PLL is enabled. */
 103         beq     lock_end                /* Do not look for lock if BYPASS selected */
 104 2:
 105         ldrh    r1,     [r0]
 106         ands    r1,     r1,     #0x01       /* Check the LOCK bit.*/
 107         beq 2b                      /* loop until bit goes hi. */
 108 lock_end:
 109
 110         /*------------------------------------------------------*
 111          * Turn off the watchdog during init...                 *
 112          *------------------------------------------------------*/
 113         ldr     r0,     REG_WATCHDOG
 114         ldr     r1,     WATCHDOG_VAL1
 115         str     r1,     [r0]
 116         ldr     r1,     WATCHDOG_VAL2
 117         str     r1,     [r0]
 118         ldr     r0,     REG_WSPRDOG
 119         ldr     r1,     WSPRDOG_VAL1
 120         str     r1,     [r0]
 121         ldr     r0,     REG_WWPSDOG
 122
 123 watch1Wait:
 124         ldr     r1,     [r0]
 125         tst     r1,     #0x10
 126         bne     watch1Wait
 127
 128         ldr     r0,     REG_WSPRDOG
 129         ldr     r1,     WSPRDOG_VAL2
 130         str     r1,     [r0]
 131         ldr     r0,     REG_WWPSDOG
 132 watch2Wait:
 133         ldr     r1,     [r0]
 134         tst     r1,     #0x10
 135         bne     watch2Wait
 136
 137         /* Set memory timings corresponding to the new clock speed */
 138         ldr     r3, VAL_SDRAM_CONFIG_SDF0
 139
 140         /* Check execution location to determine current execution location
 141          * and branch to appropriate initialization code.
 142          */
 143         mov     r0,     #0x10000000         /* Load physical SDRAM base. */
 144         mov     r1,     pc                  /* Get current execution location. */
 145         cmp     r1,     r0                  /* Compare. */
 146         bge     skip_sdram              /* Skip over EMIF-fast initialization if running from SDRAM. */
 147
 148         /* identify the device revision, -- TMX or TMP(TMS) */
 149         ldr     r0, REG_DEVICE_ID
 150         ldr     r1, [r0]
 151
 152         ldr     r0, VAL_DEVICE_ID_TMP
 153         mov     r1, r1, lsl #15
 154         mov     r1, r1, lsr #16
 155         cmp     r0, r1
 156         bne     skip_TMP_Patch
 157
 158         /* Enable TMP/TMS device new features */
 159         mov     r0, #1
 160         ldr     r1, REG_TC_EMIFF_DOUBLER
 161         str     r0, [r1]
 162
 163         /* Enable new ac parameters */
 164         mov     r0, #0x0b
 165         ldr     r1, REG_SDRAM_CONFIG2
 166         str     r0, [r1]
 167
 168         ldr     r3, VAL_SDRAM_CONFIG_SDF1
 169
 170 skip_TMP_Patch:
 171
 172         /*
 173         * Delay for SDRAM initialization.
 174         */
 175         mov     r0,     #0x1800         /* value should be checked */
 176 3:
 177         subs    r0,     r0,     #0x1    /* Decrement count */
 178         bne     3b
 179
 180         /*
 181          * Set SDRAM control values. Disable refresh before MRS command.
 182          */
 183
 184         /* mobile ddr operation */
 185         ldr     r0,     REG_SDRAM_OPERATION
 186         mov     r2,     #07
 187         str     r2,     [r0]
 188
 189         /* config register */
 190         ldr     r0,     REG_SDRAM_CONFIG
 191         str     r3,     [r0]
 192
 193         /* manual command register */
 194         ldr     r0,     REG_SDRAM_MANUAL_CMD
 195
 196         /* issue set cke high */
 197         mov     r1,     #CMD_SDRAM_CKE_SET_HIGH
 198         str     r1,     [r0]
 199
 200         /* issue nop */
 201         mov     r1,     #CMD_SDRAM_NOP
 202         str     r1,     [r0]
 203
 204         mov     r2,     #0x0100
 205 waitMDDR1:
 206         subs    r2,     r2,      #1
 207         bne     waitMDDR1       /* delay loop */
 208
 209         /* issue precharge */
 210         mov     r1,     #CMD_SDRAM_PRECHARGE
 211         str     r1,     [r0]
 212
 213         /* issue autorefresh x 2 */
 214         mov     r1,     #CMD_SDRAM_AUTOREFRESH
 215         str     r1,     [r0]
 216         str     r1,     [r0]
 217
 218         /* mrs register ddr mobile */
 219         ldr     r0,     REG_SDRAM_MRS
 220         mov     r1,     #0x33
 221         str     r1,     [r0]
 222
 223         /* emrs1 low-power register */
 224         ldr     r0,     REG_SDRAM_EMRS1
 225         /* self refresh on all banks */
 226         mov     r1,     #0
 227         str     r1,     [r0]
 228
 229         ldr     r0,     REG_DLL_URD_CONTROL
 230         ldr     r1,     DLL_URD_CONTROL_VAL
 231         str     r1,     [r0]
 232
 233         ldr     r0,     REG_DLL_LRD_CONTROL
 234         ldr     r1,     DLL_LRD_CONTROL_VAL
 235         str     r1,     [r0]
 236
 237         ldr     r0,     REG_DLL_WRT_CONTROL
 238         ldr     r1,     DLL_WRT_CONTROL_VAL
 239         str     r1,     [r0]
 240
 241         /* delay loop */
 242         mov     r0,     #0x0100
 243 waitMDDR2:
 244         subs    r0,     r0,     #1
 245         bne     waitMDDR2
 246
 247         /*
 248          * Delay for SDRAM initialization.
 249          */
 250         mov     r0,     #0x1800
 251 4:
 252         subs    r0,     r0,     #1      /* Decrement count. */
 253         bne     4b
 254         b       common_tc
 255
 256 skip_sdram:
 257         ldr     r0,     REG_SDRAM_CONFIG
 258         str     r3,     [r0]
 259
 260 common_tc:
 261         /* slow interface */
 262         ldr     r1,     VAL_TC_EMIFS_CS0_CONFIG
 263         ldr     r0,     REG_TC_EMIFS_CS0_CONFIG
 264         str     r1,     [r0] /* Chip Select 0 */
 265
 266         ldr     r1,     VAL_TC_EMIFS_CS1_CONFIG
 267         ldr     r0,     REG_TC_EMIFS_CS1_CONFIG
 268         str     r1,     [r0] /* Chip Select 1 */
 269
 270         ldr     r1,     VAL_TC_EMIFS_CS3_CONFIG
 271         ldr     r0,     REG_TC_EMIFS_CS3_CONFIG
 272         str     r1,     [r0] /* Chip Select 3 */
 273
 274         ldr     r1,     VAL_TC_EMIFS_DWS
 275         ldr     r0,     REG_TC_EMIFS_DWS
 276         str     r1,     [r0] /* Enable EMIFS.RDY for CS1 (ether) */
 277
 278 #ifdef CONFIG_H2_OMAP1610
 279         /* inserting additional 2 clock cycle hold time for LAN */
 280         ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
 281         ldr     r1,     VAL_TC_EMIFS_CS1_ADVANCED
 282         str     r1,     [r0]
 283 #endif
 284         /* Start MPU Timer 1 */
 285         ldr     r0,     REG_MPU_LOAD_TIMER
 286         ldr     r1,     VAL_MPU_LOAD_TIMER
 287         str     r1,     [r0]
 288
 289         ldr     r0,     REG_MPU_CNTL_TIMER
 290         ldr     r1,     VAL_MPU_CNTL_TIMER
 291         str     r1,     [r0]
 292
 293         /*
 294          * Setup a temporary stack
 295          */
 296         ldr     sp,     SRAM_STACK
 297         bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 298
 299         /*
 300          * Save the old lr(passed in ip) and the current lr to stack
 301          */
 302         push    {ip, lr}
 303
 304         /*
 305          * go setup pll, mux, memory
 306          */
 307         bl      s_init
 308         pop     {ip, pc}
 309
 310         /* back to arch calling code */
 311         mov     pc,     lr
 312
 313         /* the literal pools origin */
 314         .ltorg
 315
 316 REG_DEVICE_ID:                  /* 32 bits */
 317         .word 0xfffe2004
 318 REG_TC_EMIFS_CONFIG:
 319         .word 0xfffecc0c
 320 REG_TC_EMIFS_CS0_CONFIG:        /* 32 bits */
 321         .word 0xfffecc10
 322 REG_TC_EMIFS_CS1_CONFIG:        /* 32 bits */
 323         .word 0xfffecc14
 324 REG_TC_EMIFS_CS2_CONFIG:        /* 32 bits */
 325         .word 0xfffecc18
 326 REG_TC_EMIFS_CS3_CONFIG:        /* 32 bits */
 327         .word 0xfffecc1c
 328 REG_TC_EMIFS_DWS:               /* 32 bits */
 329         .word 0xfffecc40
 330 #ifdef CONFIG_H2_OMAP1610
 331 REG_TC_EMIFS_CS1_ADVANCED:      /* 32 bits */
 332         .word 0xfffecc54
 333 #endif
 334
 335 /* MPU clock/reset/power mode control registers */
 336 REG_ARM_CKCTL:                  /* 16 bits */
 337         .word 0xfffece00
 338 REG_ARM_IDLECT3:                /* 16 bits */
 339         .word 0xfffece24
 340 REG_ARM_IDLECT2:                /* 16 bits */
 341         .word 0xfffece08
 342 REG_ARM_IDLECT1:                /* 16 bits */
 343         .word 0xfffece04
 344 REG_ARM_RSTCT2:                 /* 16 bits */
 345         .word 0xfffece14
 346 REG_ARM_SYSST:                  /* 16 bits */
 347         .word 0xfffece18
 348
 349 /* DPLL control registers */
 350 REG_DPLL1_CTL:                  /* 16 bits */
 351         .word 0xfffecf00
 352
 353 /* Watch Dog register */
 354 /* secure watchdog stop */
 355 REG_WSPRDOG:
 356         .word 0xfffeb048
 357 /* watchdog write pending */
 358 REG_WWPSDOG:
 359         .word 0xfffeb034
 360
 361 WSPRDOG_VAL1:
 362         .word 0x0000aaaa
 363 WSPRDOG_VAL2:
 364         .word 0x00005555
 365
 366 /* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
 367  counter @8192 rows, 10 ns, 8 burst */
 368 REG_SDRAM_CONFIG:
 369         .word 0xfffecc20
 370 REG_SDRAM_CONFIG2:
 371         .word 0xfffecc3c
 372 REG_TC_EMIFF_DOUBLER:           /* 32 bits */
 373         .word 0xfffecc60
 374
 375 /* Operation register */
 376 REG_SDRAM_OPERATION:
 377         .word 0xfffecc80
 378
 379 /* Manual command register */
 380 REG_SDRAM_MANUAL_CMD:
 381         .word 0xfffecc84
 382
 383 /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
 384 REG_SDRAM_MRS:
 385         .word 0xfffecc70
 386
 387 /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
 388 REG_SDRAM_EMRS1:
 389         .word 0xfffecc78
 390
 391 /* WRT DLL register */
 392 REG_DLL_WRT_CONTROL:
 393         .word 0xfffecc68
 394 DLL_WRT_CONTROL_VAL:
 395         .word 0x03f00002    /* Phase of 72deg, write offset +31  */
 396
 397 /* URD DLL register */
 398 REG_DLL_URD_CONTROL:
 399         .word 0xfffeccc0
 400 DLL_URD_CONTROL_VAL:
 401         .word 0x00800002    /* Phase of 72deg, read offset +31  */
 402
 403 /* LRD DLL register */
 404 REG_DLL_LRD_CONTROL:
 405         .word 0xfffecccc
 406 DLL_LRD_CONTROL_VAL:
 407         .word 0x00800002    /* read offset +31  */
 408
 409 REG_WATCHDOG:
 410         .word 0xfffec808
 411 WATCHDOG_VAL1:
 412         .word 0x000000f5
 413 WATCHDOG_VAL2:
 414         .word 0x000000a0
 415
 416 REG_MPU_LOAD_TIMER:
 417         .word 0xfffec504
 418 REG_MPU_CNTL_TIMER:
 419         .word 0xfffec500
 420 VAL_MPU_LOAD_TIMER:
 421         .word 0xffffffff
 422 VAL_MPU_CNTL_TIMER:
 423         .word 0xffffffa1
 424
 425 /* 96 MHz Samsung Mobile DDR */
 426 /* Original setting for TMX device */
 427 VAL_SDRAM_CONFIG_SDF0:
 428     .word 0x0014e6fe
 429
 430 /* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
 431 VAL_SDRAM_CONFIG_SDF1:
 432     .word 0x0114e6fe
 433
 434 VAL_ARM_CKCTL:
 435         .word 0x2000            /* was: 0x3000, now use CLK_REF for timer input */
 436 VAL_DPLL1_CTL:
 437         .word 0x2830
 438
 439 #ifdef CONFIG_OSK_OMAP5912
 440 VAL_TC_EMIFS_CS0_CONFIG:
 441         .word 0x002130b0
 442 VAL_TC_EMIFS_CS1_CONFIG:
 443         .word 0x00001133
 444 VAL_TC_EMIFS_CS2_CONFIG:
 445         .word 0x000055f0
 446 VAL_TC_EMIFS_CS3_CONFIG:
 447         .word 0x88013141
 448 VAL_TC_EMIFS_DWS:       /* Enable EMIFS.RDY for CS1 access (ether) */
 449         .word 0x000000c0
 450 VAL_DEVICE_ID_TMP:      /* TMP/TMS=0xb65f, TMX=0xb58c */
 451         .word 0xb65f
 452 #endif
 453
 454 #ifdef CONFIG_H2_OMAP1610
 455 VAL_TC_EMIFS_CS0_CONFIG:
 456         .word 0x00203331
 457 VAL_TC_EMIFS_CS1_CONFIG:
 458         .word 0x8180fff3
 459 VAL_TC_EMIFS_CS2_CONFIG:
 460         .word 0xf800f22a
 461 VAL_TC_EMIFS_CS3_CONFIG:
 462         .word 0x88013141
 463 VAL_TC_EMIFS_CS1_ADVANCED:
 464         .word 0x00000022
 465 #endif
 466
 467 VAL_ARM_IDLECT1:
 468         .word 0x00000400
 469 VAL_ARM_IDLECT2:
 470         .word 0x00000886
 471 VAL_ARM_IDLECT3:
 472         .word 0x00000015
 473
 474 SRAM_STACK:
 475         .word CONFIG_SYS_INIT_SP_ADDR
 476
 477 /* command values */
 478 .equ CMD_SDRAM_NOP,             0x00000000
 479 .equ CMD_SDRAM_PRECHARGE,       0x00000001
 480 .equ CMD_SDRAM_AUTOREFRESH,     0x00000002
 481 .equ CMD_SDRAM_CKE_SET_HIGH,    0x00000007