board/ti/ti816x/evm.c

   1 /*
   2  * evm.c
   3  *
   4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   5  * Antoine Tenart, <atenart@adeneo-embedded.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <spl.h>
  12 #include <netdev.h>
  13 #include <asm/cache.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/mmc_host_def.h>
  21 #include <asm/arch/mem.h>
  22 #include <asm/arch/mux.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 int board_init(void)
  27 {
  28         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  29 #if defined(CONFIG_NAND)
  30         gpmc_init();
  31 #endif
  32         return 0;
  33 }
  34
  35 int board_eth_init(bd_t *bis)
  36 {
  37         uint8_t mac_addr[6];
  38         uint32_t mac_hi, mac_lo;
  39         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  40
  41         if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  42                 printf("<ethaddr> not set. Reading from E-fuse\n");
  43                 /* try reading mac address from efuse */
  44                 mac_lo = readl(&cdev->macid0l);
  45                 mac_hi = readl(&cdev->macid0h);
  46                 mac_addr[0] = mac_hi & 0xFF;
  47                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  48                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  49                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  50                 mac_addr[4] = mac_lo & 0xFF;
  51                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  52
  53                 if (is_valid_ethaddr(mac_addr))
  54                         eth_env_set_enetaddr("ethaddr", mac_addr);
  55                 else
  56                         printf("Unable to read MAC address. Set <ethaddr>\n");
  57         }
  58
  59         return davinci_emac_initialize();
  60 }
  61
  62 #ifdef CONFIG_SPL_BUILD
  63 static struct module_pin_mux mmc_pin_mux[] = {
  64         { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
  65         { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
  66         { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  67         { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  68         { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  69         { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  70         { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  71         { -1 },
  72 };
  73
  74 void set_uart_mux_conf(void) {}
  75
  76 void set_mux_conf_regs(void)
  77 {
  78         configure_module_pin_mux(mmc_pin_mux);
  79 }
  80
  81 /*
  82  * EMIF Paramters.  Refer the EMIF register documentation and the
  83  * memory datasheet for details.  This is for 796 MHz.
  84  */
  85 #define EMIF_TIM1   0x1779C9FE
  86 #define EMIF_TIM2   0x50608074
  87 #define EMIF_TIM3   0x009F857F
  88 #define EMIF_SDREF  0x10001841
  89 #define EMIF_SDCFG  0x62A73832
  90 #define EMIF_PHYCFG 0x00000110
  91 static const struct emif_regs ddr3_emif_regs = {
  92         .sdram_config           = EMIF_SDCFG,
  93         .ref_ctrl               = EMIF_SDREF,
  94         .sdram_tim1             = EMIF_TIM1,
  95         .sdram_tim2             = EMIF_TIM2,
  96         .sdram_tim3             = EMIF_TIM3,
  97         .emif_ddr_phy_ctlr_1    = EMIF_PHYCFG,
  98 };
  99
 100 static const struct cmd_control ddr3_ctrl = {
 101         .cmd0csratio    = 0x100,
 102         .cmd0iclkout    = 0x001,
 103         .cmd1csratio    = 0x100,
 104         .cmd1iclkout    = 0x001,
 105         .cmd2csratio    = 0x100,
 106         .cmd2iclkout    = 0x001,
 107 };
 108
 109 /* These values are obtained from the CCS app */
 110 #define RD_DQS_GATE     (0x1B3)
 111 #define RD_DQS          (0x35)
 112 #define WR_DQS          (0x93)
 113 static struct ddr_data ddr3_data = {
 114         .datardsratio0          = ((RD_DQS<<10) | (RD_DQS<<0)),
 115         .datawdsratio0          = ((WR_DQS<<10) | (WR_DQS<<0)),
 116         .datawiratio0           = ((0x20<<10) | 0x20<<0),
 117         .datagiratio0           = ((0x20<<10) | 0x20<<0),
 118         .datafwsratio0          = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
 119         .datawrsratio0          = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
 120 };
 121
 122 static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
 123         .dmm_lisa_map_0 = 0x00000000,
 124         .dmm_lisa_map_1 = 0x00000000,
 125         .dmm_lisa_map_2 = 0x80640300,
 126         .dmm_lisa_map_3 = 0xC0640320,
 127 };
 128
 129 void sdram_init(void)
 130 {
 131         /*
 132          * Pass in our DDR3 config information and that we have 2 EMIFs to
 133          * configure.
 134          */
 135         config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
 136                         &evm_lisa_map_regs, 2);
 137 }
 138 #endif /* CONFIG_SPL_BUILD */