board/timll/devkit8000/devkit8000.c

   1 /*
   2  * (C) Copyright 2004-2008
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *      Sunil Kumar <sunilsaini05@gmail.com>
   7  *      Shashi Ranjan <shashiranjanmca05@gmail.com>
   8  *
   9  * (C) Copyright 2009
  10  * Frederik Kriewitz <frederik@kriewitz.eu>
  11  *
  12  * Derived from Beagle Board and 3430 SDP code by
  13  *      Richard Woodruff <r-woodruff2@ti.com>
  14  *      Syed Mohammed Khasim <khasim@ti.com>
  15  *
  16  *
  17  * SPDX-License-Identifier:     GPL-2.0+
  18  */
  19 #include <common.h>
  20 #include <twl4030.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/mmc_host_def.h>
  23 #include <asm/arch/mux.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/arch/mem.h>
  26 #include <asm/mach-types.h>
  27 #include "devkit8000.h"
  28 #include <asm/gpio.h>
  29 #ifdef CONFIG_DRIVER_DM9000
  30 #include <net.h>
  31 #include <netdev.h>
  32 #endif
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 static u32 gpmc_net_config[GPMC_MAX_REG] = {
  37         NET_GPMC_CONFIG1,
  38         NET_GPMC_CONFIG2,
  39         NET_GPMC_CONFIG3,
  40         NET_GPMC_CONFIG4,
  41         NET_GPMC_CONFIG5,
  42         NET_GPMC_CONFIG6,
  43         0
  44 };
  45
  46 /*
  47  * Routine: board_init
  48  * Description: Early hardware init.
  49  */
  50 int board_init(void)
  51 {
  52         gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  53         /* board id for Linux */
  54         gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
  55         /* boot param addr */
  56         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  57
  58         return 0;
  59 }
  60
  61 /* Configure GPMC registers for DM9000 */
  62 static void gpmc_dm9000_config(void)
  63 {
  64         enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
  65                 CONFIG_DM9000_BASE, GPMC_SIZE_16M);
  66 }
  67
  68 /*
  69  * Routine: misc_init_r
  70  * Description: Configure board specific parts
  71  */
  72 int misc_init_r(void)
  73 {
  74         struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
  75 #ifdef CONFIG_DRIVER_DM9000
  76         uchar enetaddr[6];
  77         u32 die_id_0;
  78 #endif
  79
  80         twl4030_power_init();
  81 #ifdef CONFIG_TWL4030_LED
  82         twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
  83 #endif
  84
  85 #ifdef CONFIG_DRIVER_DM9000
  86         /* Configure GPMC registers for DM9000 */
  87         enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
  88                         CONFIG_DM9000_BASE, GPMC_SIZE_16M);
  89
  90         /* Use OMAP DIE_ID as MAC address */
  91         if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
  92                 printf("ethaddr not set, using Die ID\n");
  93                 die_id_0 = readl(&id_base->die_id_0);
  94                 enetaddr[0] = 0x02; /* locally administered */
  95                 enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
  96                 enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
  97                 enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
  98                 enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
  99                 enetaddr[5] = (die_id_0 & 0x000000ff);
 100                 eth_setenv_enetaddr("ethaddr", enetaddr);
 101         }
 102 #endif
 103
 104         dieid_num_r();
 105
 106         return 0;
 107 }
 108
 109 /*
 110  * Routine: set_muxconf_regs
 111  * Description: Setting up the configuration Mux registers specific to the
 112  *              hardware. Many pins need to be moved from protect to primary
 113  *              mode.
 114  */
 115 void set_muxconf_regs(void)
 116 {
 117         MUX_DEVKIT8000();
 118 }
 119
 120 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 121 int board_mmc_init(bd_t *bis)
 122 {
 123         return omap_mmc_init(0, 0, 0, -1, -1);
 124 }
 125 #endif
 126
 127 #if defined(CONFIG_GENERIC_MMC)
 128 void board_mmc_power_init(void)
 129 {
 130         twl4030_power_mmc_init(0);
 131 }
 132 #endif
 133
 134 #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
 135 /*
 136  * Routine: board_eth_init
 137  * Description: Setting up the Ethernet hardware.
 138  */
 139 int board_eth_init(bd_t *bis)
 140 {
 141         return dm9000_initialize(bis);
 142 }
 143 #endif
 144
 145 #ifdef CONFIG_SPL_OS_BOOT
 146 /*
 147  * Do board specific preperation before SPL
 148  * Linux boot
 149  */
 150 void spl_board_prepare_for_linux(void)
 151 {
 152         gpmc_dm9000_config();
 153 }
 154
 155 /*
 156  * devkit8000 specific implementation of spl_start_uboot()
 157  *
 158  * RETURN
 159  * 0 if the button is not pressed
 160  * 1 if the button is pressed
 161  */
 162 int spl_start_uboot(void)
 163 {
 164         int val = 0;
 165         if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
 166                 gpio_direction_input(SPL_OS_BOOT_KEY);
 167                 val = gpio_get_value(SPL_OS_BOOT_KEY);
 168                 gpio_free(SPL_OS_BOOT_KEY);
 169         }
 170         return !val;
 171 }
 172 #endif
 173
 174 /*
 175  * Routine: get_board_mem_timings
 176  * Description: If we use SPL then there is no x-loader nor config header
 177  * so we have to setup the DDR timings ourself on the first bank.  This
 178  * provides the timing values back to the function that configures
 179  * the memory.  We have either one or two banks of 128MB DDR.
 180  */
 181 void get_board_mem_timings(struct board_sdrc_timings *timings)
 182 {
 183         /* General SDRC config */
 184         timings->mcfg = MICRON_V_MCFG_165(128 << 20);
 185         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 186
 187         /* AC timings */
 188         timings->ctrla = MICRON_V_ACTIMA_165;
 189         timings->ctrlb = MICRON_V_ACTIMB_165;
 190
 191         timings->mr = MICRON_V_MR_165;
 192 }